mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
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1105 lines
34 KiB
C
1105 lines
34 KiB
C
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/** @file
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16550 UART Serial Port library functions
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(C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2018, AMD Incorporated. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <IndustryStandard/Pci.h>
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#include <Library/SerialPortLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciLib.h>
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#include <Library/PlatformHookLib.h>
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#include <Library/BaseLib.h>
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//
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// PCI Defintions.
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//
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#define PCI_BRIDGE_32_BIT_IO_SPACE 0x01
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//
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// 16550 UART register offsets and bitfields
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//
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#define R_UART_RXBUF 0 // LCR_DLAB = 0
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#define R_UART_TXBUF 0 // LCR_DLAB = 0
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#define R_UART_BAUD_LOW 0 // LCR_DLAB = 1
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#define R_UART_BAUD_HIGH 1 // LCR_DLAB = 1
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#define R_UART_IER 1 // LCR_DLAB = 0
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#define R_UART_FCR 2
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#define B_UART_FCR_FIFOE BIT0
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#define B_UART_FCR_FIFO64 BIT5
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#define R_UART_LCR 3
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#define B_UART_LCR_DLAB BIT7
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#define R_UART_MCR 4
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#define B_UART_MCR_DTRC BIT0
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#define B_UART_MCR_RTS BIT1
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#define R_UART_LSR 5
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#define B_UART_LSR_RXRDY BIT0
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#define B_UART_LSR_TXRDY BIT5
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#define B_UART_LSR_TEMT BIT6
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#define R_UART_MSR 6
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#define B_UART_MSR_CTS BIT4
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#define B_UART_MSR_DSR BIT5
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#define B_UART_MSR_RI BIT6
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#define B_UART_MSR_DCD BIT7
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//
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// 4-byte structure for each PCI node in PcdSerialPciDeviceInfo
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//
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typedef struct {
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UINT8 Device;
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UINT8 Function;
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UINT16 PowerManagementStatusAndControlRegister;
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} PCI_UART_DEVICE_INFO;
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/**
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Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
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MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
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parameter Offset is added to the base address of the 16550 registers that is specified
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by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO space access
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width and defaults to 8 bit access, and supports 8 or 32 bit access.
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@param Base The base address register of UART device.
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@param Offset The offset of the 16550 register to read.
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@return The value read from the 16550 register.
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**/
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UINT8
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SerialPortReadRegister (
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UINTN Base,
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UINTN Offset
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)
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{
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if (PcdGetBool (PcdSerialUseMmio)) {
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if (PcdGet8 (PcdSerialRegisterAccessWidth) == 32) {
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return (UINT8) MmioRead32 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
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}
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return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
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} else {
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return IoRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
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}
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}
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/**
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Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is written to
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MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O space. The
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parameter Offset is added to the base address of the 16550 registers that is specified
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by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO space access
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width and defaults to 8 bit access, and supports 8 or 32 bit access.
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@param Base The base address register of UART device.
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@param Offset The offset of the 16550 register to write.
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@param Value The value to write to the 16550 register specified by Offset.
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@return The value written to the 16550 register.
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**/
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UINT8
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SerialPortWriteRegister (
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UINTN Base,
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UINTN Offset,
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UINT8 Value
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)
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{
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if (PcdGetBool (PcdSerialUseMmio)) {
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if (PcdGet8 (PcdSerialRegisterAccessWidth) == 32) {
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return (UINT8) MmioWrite32 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), (UINT8)Value);
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}
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return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);
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} else {
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return IoWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);
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}
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}
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/**
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Update the value of an 16-bit PCI configuration register in a PCI device. If the
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PCI Configuration register specified by PciAddress is already programmed with a
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non-zero value, then return the current value. Otherwise update the PCI configuration
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register specified by PciAddress with the value specified by Value and return the
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value programmed into the PCI configuration register. All values must be masked
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using the bitmask specified by Mask.
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@param PciAddress PCI Library address of the PCI Configuration register to update.
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@param Value The value to program into the PCI Configuration Register.
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@param Mask Bitmask of the bits to check and update in the PCI configuration register.
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**/
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UINT16
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SerialPortLibUpdatePciRegister16 (
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UINTN PciAddress,
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UINT16 Value,
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UINT16 Mask
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)
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{
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UINT16 CurrentValue;
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CurrentValue = PciRead16 (PciAddress) & Mask;
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if (CurrentValue != 0) {
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return CurrentValue;
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}
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return PciWrite16 (PciAddress, Value & Mask);
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}
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/**
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Update the value of an 32-bit PCI configuration register in a PCI device. If the
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PCI Configuration register specified by PciAddress is already programmed with a
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non-zero value, then return the current value. Otherwise update the PCI configuration
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register specified by PciAddress with the value specified by Value and return the
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value programmed into the PCI configuration register. All values must be masked
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using the bitmask specified by Mask.
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@param PciAddress PCI Library address of the PCI Configuration register to update.
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@param Value The value to program into the PCI Configuration Register.
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@param Mask Bitmask of the bits to check and update in the PCI configuration register.
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@return The Secondary bus number that is actually programed into the PCI to PCI Bridge device.
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**/
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UINT32
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SerialPortLibUpdatePciRegister32 (
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UINTN PciAddress,
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UINT32 Value,
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UINT32 Mask
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)
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{
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UINT32 CurrentValue;
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CurrentValue = PciRead32 (PciAddress) & Mask;
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if (CurrentValue != 0) {
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return CurrentValue;
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}
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return PciWrite32 (PciAddress, Value & Mask);
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}
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/**
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Retrieve the I/O or MMIO base address register for the PCI UART device.
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This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART
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Device if they are not already enabled.
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@return The base address register of the UART device.
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**/
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UINTN
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GetSerialRegisterBase (
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VOID
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)
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{
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UINTN PciLibAddress;
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UINTN BusNumber;
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UINTN SubordinateBusNumber;
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UINT32 ParentIoBase;
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UINT32 ParentIoLimit;
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UINT16 ParentMemoryBase;
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UINT16 ParentMemoryLimit;
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UINT32 IoBase;
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UINT32 IoLimit;
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UINT16 MemoryBase;
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UINT16 MemoryLimit;
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UINTN SerialRegisterBase;
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UINTN BarIndex;
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UINT32 RegisterBaseMask;
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PCI_UART_DEVICE_INFO *DeviceInfo;
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//
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// Get PCI Device Info
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//
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DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo);
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//
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// If PCI Device Info is empty, then assume fixed address UART and return PcdSerialRegisterBase
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//
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if (DeviceInfo->Device == 0xff) {
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return (UINTN)PcdGet64 (PcdSerialRegisterBase);
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}
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//
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// Assume PCI Bus 0 I/O window is 0-64KB and MMIO windows is 0-4GB
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//
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ParentMemoryBase = 0 >> 16;
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ParentMemoryLimit = 0xfff00000 >> 16;
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ParentIoBase = 0 >> 12;
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ParentIoLimit = 0xf000 >> 12;
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//
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// Enable I/O and MMIO in PCI Bridge
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// Assume Root Bus Numer is Zero.
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//
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for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) {
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//
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// Compute PCI Lib Address to PCI to PCI Bridge
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//
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PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
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//
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// Retrieve and verify the bus numbers in the PCI to PCI Bridge
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//
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BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
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SubordinateBusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
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if (BusNumber == 0 || BusNumber > SubordinateBusNumber) {
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return 0;
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}
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//
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// Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge
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//
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if (PcdGetBool (PcdSerialUseMmio)) {
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MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xfff0;
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MemoryBase = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase)) & 0xfff0;
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//
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// If PCI Bridge MMIO window is disabled, then return 0
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//
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if (MemoryLimit < MemoryBase) {
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return 0;
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}
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//
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// If PCI Bridge MMIO window is not in the address range decoded by the parent PCI Bridge, then return 0
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//
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if (MemoryBase < ParentMemoryBase || MemoryBase > ParentMemoryLimit || MemoryLimit > ParentMemoryLimit) {
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return 0;
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}
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ParentMemoryBase = MemoryBase;
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ParentMemoryLimit = MemoryLimit;
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} else {
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IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit));
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if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
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IoLimit = IoLimit >> 4;
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} else {
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IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimitUpper16)) << 4) | (IoLimit >> 4);
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}
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IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
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if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
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IoBase = IoBase >> 4;
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} else {
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IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4);
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}
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//
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// If PCI Bridge I/O window is disabled, then return 0
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//
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if (IoLimit < IoBase) {
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return 0;
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}
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//
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// If PCI Bridge I/O window is not in the address range decoded by the parent PCI Bridge, then return 0
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//
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if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > ParentIoLimit) {
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return 0;
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}
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ParentIoBase = IoBase;
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ParentIoLimit = IoLimit;
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}
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}
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//
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// Compute PCI Lib Address to PCI UART
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//
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PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
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//
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// Find the first IO or MMIO BAR
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//
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RegisterBaseMask = 0xFFFFFFF0;
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for (BarIndex = 0; BarIndex < PCI_MAX_BAR; BarIndex ++) {
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SerialRegisterBase = PciRead32 (PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4);
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if (PcdGetBool (PcdSerialUseMmio) && ((SerialRegisterBase & BIT0) == 0)) {
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//
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// MMIO BAR is found
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//
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RegisterBaseMask = 0xFFFFFFF0;
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break;
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}
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if ((!PcdGetBool (PcdSerialUseMmio)) && ((SerialRegisterBase & BIT0) != 0)) {
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//
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// IO BAR is found
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//
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RegisterBaseMask = 0xFFFFFFF8;
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break;
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}
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}
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//
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// MMIO or IO BAR is not found.
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//
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if (BarIndex == PCI_MAX_BAR) {
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return 0;
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}
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//
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// Program UART BAR
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//
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SerialRegisterBase = SerialPortLibUpdatePciRegister32 (
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PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4,
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(UINT32)PcdGet64 (PcdSerialRegisterBase),
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RegisterBaseMask
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);
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//
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// Verify that the UART BAR is in the address range decoded by the parent PCI Bridge
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//
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if (PcdGetBool (PcdSerialUseMmio)) {
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if (((SerialRegisterBase >> 16) & 0xfff0) < ParentMemoryBase || ((SerialRegisterBase >> 16) & 0xfff0) > ParentMemoryLimit) {
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return 0;
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}
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} else {
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if ((SerialRegisterBase >> 12) < ParentIoBase || (SerialRegisterBase >> 12) > ParentIoLimit) {
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return 0;
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}
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}
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//
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// Enable I/O and MMIO in PCI UART Device if they are not already enabled
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//
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PciOr16 (
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PciLibAddress + PCI_COMMAND_OFFSET,
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PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE
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);
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//
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// Force D0 state if a Power Management and Status Register is specified
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//
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if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) {
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if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {
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PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));
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//
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// If PCI UART was not in D0, then make sure FIFOs are enabled, but do not reset FIFOs
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//
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SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
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}
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}
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//
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// Get PCI Device Info
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//
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DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo);
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//
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// Enable I/O or MMIO in PCI Bridge
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// Assume Root Bus Numer is Zero.
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//
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for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) {
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//
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// Compute PCI Lib Address to PCI to PCI Bridge
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|
//
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PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
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|
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|
//
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// Enable the I/O or MMIO decode windows in the PCI to PCI Bridge
|
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|
//
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PciOr16 (
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PciLibAddress + PCI_COMMAND_OFFSET,
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PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE
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);
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|
//
|
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// Force D0 state if a Power Management and Status Register is specified
|
||
|
//
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|
if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) {
|
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|
if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {
|
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PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));
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|
}
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}
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|
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|
BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
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|
}
|
||
|
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||
|
return SerialRegisterBase;
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||
|
}
|
||
|
|
||
|
/**
|
||
|
Return whether the hardware flow control signal allows writing.
|
||
|
|
||
|
@param SerialRegisterBase The base address register of UART device.
|
||
|
|
||
|
@retval TRUE The serial port is writable.
|
||
|
@retval FALSE The serial port is not writable.
|
||
|
**/
|
||
|
BOOLEAN
|
||
|
SerialPortWritable (
|
||
|
UINTN SerialRegisterBase
|
||
|
)
|
||
|
{
|
||
|
if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
|
||
|
if (PcdGetBool (PcdSerialDetectCable)) {
|
||
|
//
|
||
|
// Wait for both DSR and CTS to be set
|
||
|
// DSR is set if a cable is connected.
|
||
|
// CTS is set if it is ok to transmit data
|
||
|
//
|
||
|
// DSR CTS Description Action
|
||
|
// === === ======================================== ========
|
||
|
// 0 0 No cable connected. Wait
|
||
|
// 0 1 No cable connected. Wait
|
||
|
// 1 0 Cable connected, but not clear to send. Wait
|
||
|
// 1 1 Cable connected, and clear to send. Transmit
|
||
|
//
|
||
|
return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS));
|
||
|
} else {
|
||
|
//
|
||
|
// Wait for both DSR and CTS to be set OR for DSR to be clear.
|
||
|
// DSR is set if a cable is connected.
|
||
|
// CTS is set if it is ok to transmit data
|
||
|
//
|
||
|
// DSR CTS Description Action
|
||
|
// === === ======================================== ========
|
||
|
// 0 0 No cable connected. Transmit
|
||
|
// 0 1 No cable connected. Transmit
|
||
|
// 1 0 Cable connected, but not clear to send. Wait
|
||
|
// 1 1 Cable connected, and clar to send. Transmit
|
||
|
//
|
||
|
return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) != (B_UART_MSR_DSR));
|
||
|
}
|
||
|
}
|
||
|
|
||
|
return TRUE;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
Initialize the serial device hardware.
|
||
|
|
||
|
If no initialization is required, then return RETURN_SUCCESS.
|
||
|
If the serial device was successfully initialized, then return RETURN_SUCCESS.
|
||
|
If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
|
||
|
|
||
|
@retval RETURN_SUCCESS The serial device was initialized.
|
||
|
@retval RETURN_DEVICE_ERROR The serial device could not be initialized.
|
||
|
|
||
|
**/
|
||
|
RETURN_STATUS
|
||
|
EFIAPI
|
||
|
SerialPortInitialize (
|
||
|
VOID
|
||
|
)
|
||
|
{
|
||
|
RETURN_STATUS Status;
|
||
|
UINTN SerialRegisterBase;
|
||
|
UINT32 Divisor;
|
||
|
UINT32 CurrentDivisor;
|
||
|
BOOLEAN Initialized;
|
||
|
|
||
|
//
|
||
|
// Perform platform specific initialization required to enable use of the 16550 device
|
||
|
// at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
|
||
|
//
|
||
|
Status = PlatformHookSerialPortInitialize ();
|
||
|
if (RETURN_ERROR (Status)) {
|
||
|
return Status;
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// Calculate divisor for baud generator
|
||
|
// Ref_Clk_Rate / Baud_Rate / 16
|
||
|
//
|
||
|
Divisor = PcdGet32 (PcdSerialClockRate) / (PcdGet32 (PcdSerialBaudRate) * 16);
|
||
|
if ((PcdGet32 (PcdSerialClockRate) % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32 (PcdSerialBaudRate) * 8) {
|
||
|
Divisor++;
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// Get the base address of the serial port in either I/O or MMIO space
|
||
|
//
|
||
|
SerialRegisterBase = GetSerialRegisterBase ();
|
||
|
if (SerialRegisterBase ==0) {
|
||
|
return RETURN_DEVICE_ERROR;
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// See if the serial port is already initialized
|
||
|
//
|
||
|
Initialized = TRUE;
|
||
|
if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
|
||
|
Initialized = FALSE;
|
||
|
}
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) | B_UART_LCR_DLAB));
|
||
|
CurrentDivisor = SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_HIGH) << 8;
|
||
|
CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_LOW);
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & ~B_UART_LCR_DLAB));
|
||
|
if (CurrentDivisor != Divisor) {
|
||
|
Initialized = FALSE;
|
||
|
}
|
||
|
if (Initialized) {
|
||
|
return RETURN_SUCCESS;
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// Wait for the serial port to be ready.
|
||
|
// Verify that both the transmit FIFO and the shift register are empty.
|
||
|
//
|
||
|
while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
|
||
|
|
||
|
//
|
||
|
// Configure baud rate
|
||
|
//
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
|
||
|
|
||
|
//
|
||
|
// Clear DLAB and configure Data Bits, Parity, and Stop Bits.
|
||
|
// Strip reserved bits from PcdSerialLineControl
|
||
|
//
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F));
|
||
|
|
||
|
//
|
||
|
// Enable and reset FIFOs
|
||
|
// Strip reserved bits from PcdSerialFifoControl
|
||
|
//
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
|
||
|
|
||
|
//
|
||
|
// Set FIFO Polled Mode by clearing IER after setting FCR
|
||
|
//
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00);
|
||
|
|
||
|
//
|
||
|
// Put Modem Control Register(MCR) into its reset state of 0x00.
|
||
|
//
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
|
||
|
|
||
|
return RETURN_SUCCESS;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
Write data from buffer to serial device.
|
||
|
|
||
|
Writes NumberOfBytes data bytes from Buffer to the serial device.
|
||
|
The number of bytes actually written to the serial device is returned.
|
||
|
If the return value is less than NumberOfBytes, then the write operation failed.
|
||
|
|
||
|
If Buffer is NULL, then ASSERT().
|
||
|
|
||
|
If NumberOfBytes is zero, then return 0.
|
||
|
|
||
|
@param Buffer Pointer to the data buffer to be written.
|
||
|
@param NumberOfBytes Number of bytes to written to the serial device.
|
||
|
|
||
|
@retval 0 NumberOfBytes is 0.
|
||
|
@retval >0 The number of bytes written to the serial device.
|
||
|
If this value is less than NumberOfBytes, then the write operation failed.
|
||
|
|
||
|
**/
|
||
|
UINTN
|
||
|
EFIAPI
|
||
|
SerialPortWrite (
|
||
|
IN UINT8 *Buffer,
|
||
|
IN UINTN NumberOfBytes
|
||
|
)
|
||
|
{
|
||
|
UINTN SerialRegisterBase;
|
||
|
UINTN Result;
|
||
|
UINTN Index;
|
||
|
UINTN FifoSize;
|
||
|
|
||
|
if (Buffer == NULL) {
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
SerialRegisterBase = GetSerialRegisterBase ();
|
||
|
if (SerialRegisterBase ==0) {
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
if (NumberOfBytes == 0) {
|
||
|
//
|
||
|
// Flush the hardware
|
||
|
//
|
||
|
|
||
|
//
|
||
|
// Wait for both the transmit FIFO and shift register empty.
|
||
|
//
|
||
|
while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
|
||
|
|
||
|
//
|
||
|
// Wait for the hardware flow control signal
|
||
|
//
|
||
|
while (!SerialPortWritable (SerialRegisterBase));
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// Compute the maximum size of the Tx FIFO
|
||
|
//
|
||
|
FifoSize = 1;
|
||
|
if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFOE) != 0) {
|
||
|
if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFO64) == 0) {
|
||
|
FifoSize = 16;
|
||
|
} else {
|
||
|
FifoSize = PcdGet32 (PcdSerialExtendedTxFifoSize);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
Result = NumberOfBytes;
|
||
|
while (NumberOfBytes != 0) {
|
||
|
//
|
||
|
// Wait for the serial port to be ready, to make sure both the transmit FIFO
|
||
|
// and shift register empty.
|
||
|
//
|
||
|
while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_TEMT) == 0);
|
||
|
|
||
|
//
|
||
|
// Fill then entire Tx FIFO
|
||
|
//
|
||
|
for (Index = 0; Index < FifoSize && NumberOfBytes != 0; Index++, NumberOfBytes--, Buffer++) {
|
||
|
//
|
||
|
// Wait for the hardware flow control signal
|
||
|
//
|
||
|
while (!SerialPortWritable (SerialRegisterBase));
|
||
|
|
||
|
//
|
||
|
// Write byte to the transmit buffer.
|
||
|
//
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_TXBUF, *Buffer);
|
||
|
}
|
||
|
}
|
||
|
return Result;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
Reads data from a serial device into a buffer.
|
||
|
|
||
|
@param Buffer Pointer to the data buffer to store the data read from the serial device.
|
||
|
@param NumberOfBytes Number of bytes to read from the serial device.
|
||
|
|
||
|
@retval 0 NumberOfBytes is 0.
|
||
|
@retval >0 The number of bytes read from the serial device.
|
||
|
If this value is less than NumberOfBytes, then the read operation failed.
|
||
|
|
||
|
**/
|
||
|
UINTN
|
||
|
EFIAPI
|
||
|
SerialPortRead (
|
||
|
OUT UINT8 *Buffer,
|
||
|
IN UINTN NumberOfBytes
|
||
|
)
|
||
|
{
|
||
|
UINTN SerialRegisterBase;
|
||
|
UINTN Result;
|
||
|
UINT8 Mcr;
|
||
|
|
||
|
if (NULL == Buffer) {
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
SerialRegisterBase = GetSerialRegisterBase ();
|
||
|
if (SerialRegisterBase ==0) {
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
Mcr = (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS);
|
||
|
|
||
|
for (Result = 0; NumberOfBytes-- != 0; Result++, Buffer++) {
|
||
|
//
|
||
|
// Wait for the serial port to have some data.
|
||
|
//
|
||
|
while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) == 0) {
|
||
|
if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
|
||
|
//
|
||
|
// Set RTS to let the peer send some data
|
||
|
//
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Mcr | B_UART_MCR_RTS));
|
||
|
}
|
||
|
}
|
||
|
if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
|
||
|
//
|
||
|
// Clear RTS to prevent peer from sending data
|
||
|
//
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// Read byte from the receive buffer.
|
||
|
//
|
||
|
*Buffer = SerialPortReadRegister (SerialRegisterBase, R_UART_RXBUF);
|
||
|
}
|
||
|
|
||
|
return Result;
|
||
|
}
|
||
|
|
||
|
|
||
|
/**
|
||
|
Polls a serial device to see if there is any data waiting to be read.
|
||
|
|
||
|
Polls aserial device to see if there is any data waiting to be read.
|
||
|
If there is data waiting to be read from the serial device, then TRUE is returned.
|
||
|
If there is no data waiting to be read from the serial device, then FALSE is returned.
|
||
|
|
||
|
@retval TRUE Data is waiting to be read from the serial device.
|
||
|
@retval FALSE There is no data waiting to be read from the serial device.
|
||
|
|
||
|
**/
|
||
|
BOOLEAN
|
||
|
EFIAPI
|
||
|
SerialPortPoll (
|
||
|
VOID
|
||
|
)
|
||
|
{
|
||
|
UINTN SerialRegisterBase;
|
||
|
|
||
|
SerialRegisterBase = GetSerialRegisterBase ();
|
||
|
if (SerialRegisterBase ==0) {
|
||
|
return FALSE;
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// Read the serial port status
|
||
|
//
|
||
|
if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) != 0) {
|
||
|
if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
|
||
|
//
|
||
|
// Clear RTS to prevent peer from sending data
|
||
|
//
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS));
|
||
|
}
|
||
|
return TRUE;
|
||
|
}
|
||
|
|
||
|
if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
|
||
|
//
|
||
|
// Set RTS to let the peer send some data
|
||
|
//
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) | B_UART_MCR_RTS));
|
||
|
}
|
||
|
|
||
|
return FALSE;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
Sets the control bits on a serial device.
|
||
|
|
||
|
@param Control Sets the bits of Control that are settable.
|
||
|
|
||
|
@retval RETURN_SUCCESS The new control bits were set on the serial device.
|
||
|
@retval RETURN_UNSUPPORTED The serial device does not support this operation.
|
||
|
@retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
|
||
|
|
||
|
**/
|
||
|
RETURN_STATUS
|
||
|
EFIAPI
|
||
|
SerialPortSetControl (
|
||
|
IN UINT32 Control
|
||
|
)
|
||
|
{
|
||
|
UINTN SerialRegisterBase;
|
||
|
UINT8 Mcr;
|
||
|
|
||
|
//
|
||
|
// First determine the parameter is invalid.
|
||
|
//
|
||
|
if ((Control & (~(EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY |
|
||
|
EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) != 0) {
|
||
|
return RETURN_UNSUPPORTED;
|
||
|
}
|
||
|
|
||
|
SerialRegisterBase = GetSerialRegisterBase ();
|
||
|
if (SerialRegisterBase ==0) {
|
||
|
return RETURN_UNSUPPORTED;
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// Read the Modem Control Register.
|
||
|
//
|
||
|
Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
|
||
|
Mcr &= (~(B_UART_MCR_DTRC | B_UART_MCR_RTS));
|
||
|
|
||
|
if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) == EFI_SERIAL_DATA_TERMINAL_READY) {
|
||
|
Mcr |= B_UART_MCR_DTRC;
|
||
|
}
|
||
|
|
||
|
if ((Control & EFI_SERIAL_REQUEST_TO_SEND) == EFI_SERIAL_REQUEST_TO_SEND) {
|
||
|
Mcr |= B_UART_MCR_RTS;
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// Write the Modem Control Register.
|
||
|
//
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
|
||
|
|
||
|
return RETURN_SUCCESS;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
Retrieve the status of the control bits on a serial device.
|
||
|
|
||
|
@param Control A pointer to return the current control signals from the serial device.
|
||
|
|
||
|
@retval RETURN_SUCCESS The control bits were read from the serial device.
|
||
|
@retval RETURN_UNSUPPORTED The serial device does not support this operation.
|
||
|
@retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
|
||
|
|
||
|
**/
|
||
|
RETURN_STATUS
|
||
|
EFIAPI
|
||
|
SerialPortGetControl (
|
||
|
OUT UINT32 *Control
|
||
|
)
|
||
|
{
|
||
|
UINTN SerialRegisterBase;
|
||
|
UINT8 Msr;
|
||
|
UINT8 Mcr;
|
||
|
UINT8 Lsr;
|
||
|
|
||
|
SerialRegisterBase = GetSerialRegisterBase ();
|
||
|
if (SerialRegisterBase ==0) {
|
||
|
return RETURN_UNSUPPORTED;
|
||
|
}
|
||
|
|
||
|
*Control = 0;
|
||
|
|
||
|
//
|
||
|
// Read the Modem Status Register.
|
||
|
//
|
||
|
Msr = SerialPortReadRegister (SerialRegisterBase, R_UART_MSR);
|
||
|
|
||
|
if ((Msr & B_UART_MSR_CTS) == B_UART_MSR_CTS) {
|
||
|
*Control |= EFI_SERIAL_CLEAR_TO_SEND;
|
||
|
}
|
||
|
|
||
|
if ((Msr & B_UART_MSR_DSR) == B_UART_MSR_DSR) {
|
||
|
*Control |= EFI_SERIAL_DATA_SET_READY;
|
||
|
}
|
||
|
|
||
|
if ((Msr & B_UART_MSR_RI) == B_UART_MSR_RI) {
|
||
|
*Control |= EFI_SERIAL_RING_INDICATE;
|
||
|
}
|
||
|
|
||
|
if ((Msr & B_UART_MSR_DCD) == B_UART_MSR_DCD) {
|
||
|
*Control |= EFI_SERIAL_CARRIER_DETECT;
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// Read the Modem Control Register.
|
||
|
//
|
||
|
Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
|
||
|
|
||
|
if ((Mcr & B_UART_MCR_DTRC) == B_UART_MCR_DTRC) {
|
||
|
*Control |= EFI_SERIAL_DATA_TERMINAL_READY;
|
||
|
}
|
||
|
|
||
|
if ((Mcr & B_UART_MCR_RTS) == B_UART_MCR_RTS) {
|
||
|
*Control |= EFI_SERIAL_REQUEST_TO_SEND;
|
||
|
}
|
||
|
|
||
|
if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
|
||
|
*Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// Read the Line Status Register.
|
||
|
//
|
||
|
Lsr = SerialPortReadRegister (SerialRegisterBase, R_UART_LSR);
|
||
|
|
||
|
if ((Lsr & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) == (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) {
|
||
|
*Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
|
||
|
}
|
||
|
|
||
|
if ((Lsr & B_UART_LSR_RXRDY) == 0) {
|
||
|
*Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
|
||
|
}
|
||
|
|
||
|
return RETURN_SUCCESS;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
|
||
|
data bits, and stop bits on a serial device.
|
||
|
|
||
|
@param BaudRate The requested baud rate. A BaudRate value of 0 will use the
|
||
|
device's default interface speed.
|
||
|
On output, the value actually set.
|
||
|
@param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the
|
||
|
serial interface. A ReceiveFifoDepth value of 0 will use
|
||
|
the device's default FIFO depth.
|
||
|
On output, the value actually set.
|
||
|
@param Timeout The requested time out for a single character in microseconds.
|
||
|
This timeout applies to both the transmit and receive side of the
|
||
|
interface. A Timeout value of 0 will use the device's default time
|
||
|
out value.
|
||
|
On output, the value actually set.
|
||
|
@param Parity The type of parity to use on this serial device. A Parity value of
|
||
|
DefaultParity will use the device's default parity value.
|
||
|
On output, the value actually set.
|
||
|
@param DataBits The number of data bits to use on the serial device. A DataBits
|
||
|
vaule of 0 will use the device's default data bit setting.
|
||
|
On output, the value actually set.
|
||
|
@param StopBits The number of stop bits to use on this serial device. A StopBits
|
||
|
value of DefaultStopBits will use the device's default number of
|
||
|
stop bits.
|
||
|
On output, the value actually set.
|
||
|
|
||
|
@retval RETURN_SUCCESS The new attributes were set on the serial device.
|
||
|
@retval RETURN_UNSUPPORTED The serial device does not support this operation.
|
||
|
@retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
|
||
|
@retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
|
||
|
|
||
|
**/
|
||
|
RETURN_STATUS
|
||
|
EFIAPI
|
||
|
SerialPortSetAttributes (
|
||
|
IN OUT UINT64 *BaudRate,
|
||
|
IN OUT UINT32 *ReceiveFifoDepth,
|
||
|
IN OUT UINT32 *Timeout,
|
||
|
IN OUT EFI_PARITY_TYPE *Parity,
|
||
|
IN OUT UINT8 *DataBits,
|
||
|
IN OUT EFI_STOP_BITS_TYPE *StopBits
|
||
|
)
|
||
|
{
|
||
|
UINTN SerialRegisterBase;
|
||
|
UINT32 SerialBaudRate;
|
||
|
UINTN Divisor;
|
||
|
UINT8 Lcr;
|
||
|
UINT8 LcrData;
|
||
|
UINT8 LcrParity;
|
||
|
UINT8 LcrStop;
|
||
|
|
||
|
SerialRegisterBase = GetSerialRegisterBase ();
|
||
|
if (SerialRegisterBase ==0) {
|
||
|
return RETURN_UNSUPPORTED;
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// Check for default settings and fill in actual values.
|
||
|
//
|
||
|
if (*BaudRate == 0) {
|
||
|
*BaudRate = PcdGet32 (PcdSerialBaudRate);
|
||
|
}
|
||
|
SerialBaudRate = (UINT32) *BaudRate;
|
||
|
|
||
|
if (*DataBits == 0) {
|
||
|
LcrData = (UINT8) (PcdGet8 (PcdSerialLineControl) & 0x3);
|
||
|
*DataBits = LcrData + 5;
|
||
|
} else {
|
||
|
if ((*DataBits < 5) || (*DataBits > 8)) {
|
||
|
return RETURN_INVALID_PARAMETER;
|
||
|
}
|
||
|
//
|
||
|
// Map 5..8 to 0..3
|
||
|
//
|
||
|
LcrData = (UINT8) (*DataBits - (UINT8) 5);
|
||
|
}
|
||
|
|
||
|
if (*Parity == DefaultParity) {
|
||
|
LcrParity = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 3) & 0x7);
|
||
|
switch (LcrParity) {
|
||
|
case 0:
|
||
|
*Parity = NoParity;
|
||
|
break;
|
||
|
|
||
|
case 3:
|
||
|
*Parity = EvenParity;
|
||
|
break;
|
||
|
|
||
|
case 1:
|
||
|
*Parity = OddParity;
|
||
|
break;
|
||
|
|
||
|
case 7:
|
||
|
*Parity = SpaceParity;
|
||
|
break;
|
||
|
|
||
|
case 5:
|
||
|
*Parity = MarkParity;
|
||
|
break;
|
||
|
|
||
|
default:
|
||
|
break;
|
||
|
}
|
||
|
} else {
|
||
|
switch (*Parity) {
|
||
|
case NoParity:
|
||
|
LcrParity = 0;
|
||
|
break;
|
||
|
|
||
|
case EvenParity:
|
||
|
LcrParity = 3;
|
||
|
break;
|
||
|
|
||
|
case OddParity:
|
||
|
LcrParity = 1;
|
||
|
break;
|
||
|
|
||
|
case SpaceParity:
|
||
|
LcrParity = 7;
|
||
|
break;
|
||
|
|
||
|
case MarkParity:
|
||
|
LcrParity = 5;
|
||
|
break;
|
||
|
|
||
|
default:
|
||
|
return RETURN_INVALID_PARAMETER;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (*StopBits == DefaultStopBits) {
|
||
|
LcrStop = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 2) & 0x1);
|
||
|
switch (LcrStop) {
|
||
|
case 0:
|
||
|
*StopBits = OneStopBit;
|
||
|
break;
|
||
|
|
||
|
case 1:
|
||
|
if (*DataBits == 5) {
|
||
|
*StopBits = OneFiveStopBits;
|
||
|
} else {
|
||
|
*StopBits = TwoStopBits;
|
||
|
}
|
||
|
break;
|
||
|
|
||
|
default:
|
||
|
break;
|
||
|
}
|
||
|
} else {
|
||
|
switch (*StopBits) {
|
||
|
case OneStopBit:
|
||
|
LcrStop = 0;
|
||
|
break;
|
||
|
|
||
|
case OneFiveStopBits:
|
||
|
case TwoStopBits:
|
||
|
LcrStop = 1;
|
||
|
break;
|
||
|
|
||
|
default:
|
||
|
return RETURN_INVALID_PARAMETER;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// Calculate divisor for baud generator
|
||
|
// Ref_Clk_Rate / Baud_Rate / 16
|
||
|
//
|
||
|
Divisor = PcdGet32 (PcdSerialClockRate) / (SerialBaudRate * 16);
|
||
|
if ((PcdGet32 (PcdSerialClockRate) % (SerialBaudRate * 16)) >= SerialBaudRate * 8) {
|
||
|
Divisor++;
|
||
|
}
|
||
|
|
||
|
//
|
||
|
// Configure baud rate
|
||
|
//
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
|
||
|
|
||
|
//
|
||
|
// Clear DLAB and configure Data Bits, Parity, and Stop Bits.
|
||
|
// Strip reserved bits from line control value
|
||
|
//
|
||
|
Lcr = (UINT8) ((LcrParity << 3) | (LcrStop << 2) | LcrData);
|
||
|
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8) (Lcr & 0x3F));
|
||
|
|
||
|
return RETURN_SUCCESS;
|
||
|
}
|
||
|
|