mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
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350 lines
14 KiB
C
350 lines
14 KiB
C
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/** @file
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The NvmExpressPei driver is used to manage non-volatile memory subsystem
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which follows NVM Express specification at PEI phase.
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Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _NVM_EXPRESS_PEI_H_
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#define _NVM_EXPRESS_PEI_H_
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#include <PiPei.h>
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#include <IndustryStandard/Nvme.h>
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#include <Ppi/NvmExpressHostController.h>
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#include <Ppi/BlockIo.h>
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#include <Ppi/BlockIo2.h>
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#include <Ppi/StorageSecurityCommand.h>
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#include <Ppi/NvmExpressPassThru.h>
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#include <Ppi/IoMmu.h>
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#include <Ppi/EndOfPeiPhase.h>
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#include <Library/DebugLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/IoLib.h>
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#include <Library/TimerLib.h>
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//
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// Structure forward declarations
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//
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typedef struct _PEI_NVME_NAMESPACE_INFO PEI_NVME_NAMESPACE_INFO;
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typedef struct _PEI_NVME_CONTROLLER_PRIVATE_DATA PEI_NVME_CONTROLLER_PRIVATE_DATA;
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#include "NvmExpressPeiHci.h"
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#include "NvmExpressPeiPassThru.h"
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#include "NvmExpressPeiBlockIo.h"
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#include "NvmExpressPeiStorageSecurity.h"
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//
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// NVME PEI driver implementation related definitions
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//
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#define NVME_MAX_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
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#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
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#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
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#define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based
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#define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based
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#define NVME_PRP_SIZE (8) // Pages of PRP list
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#define NVME_MEM_MAX_PAGES \
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( \
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1 /* ASQ */ + \
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1 /* ACQ */ + \
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1 /* SQs */ + \
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1 /* CQs */ + \
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NVME_PRP_SIZE) /* PRPs */
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#define NVME_ADMIN_QUEUE 0x00
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#define NVME_IO_QUEUE 0x01
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#define NVME_GENERIC_TIMEOUT 5000000 // Generic PassThru command timeout value, in us unit
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#define NVME_POLL_INTERVAL 100 // Poll interval for PassThru command, in us unit
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//
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// Nvme namespace data structure.
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//
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struct _PEI_NVME_NAMESPACE_INFO {
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UINT32 NamespaceId;
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UINT64 NamespaceUuid;
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EFI_PEI_BLOCK_IO2_MEDIA Media;
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PEI_NVME_CONTROLLER_PRIVATE_DATA *Controller;
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};
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#define NVME_CONTROLLER_NSID 0
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//
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// Unique signature for private data structure.
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//
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#define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','P','C')
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//
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// Nvme controller private data structure.
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//
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struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {
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UINT32 Signature;
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UINTN MmioBase;
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EFI_NVM_EXPRESS_PASS_THRU_MODE PassThruMode;
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UINTN DevicePathLength;
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EFI_DEVICE_PATH_PROTOCOL *DevicePath;
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EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi;
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EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi;
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EDKII_PEI_STORAGE_SECURITY_CMD_PPI StorageSecurityPpi;
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EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI NvmePassThruPpi;
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EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;
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EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;
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EFI_PEI_PPI_DESCRIPTOR StorageSecurityPpiList;
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EFI_PEI_PPI_DESCRIPTOR NvmePassThruPpiList;
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EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
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//
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// Pointer to identify controller data
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//
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NVME_ADMIN_CONTROLLER_DATA *ControllerData;
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//
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// (4 + NVME_PRP_SIZE) x 4kB aligned buffers will be carved out of this buffer
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// 1st 4kB boundary is the start of the admin submission queue
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// 2nd 4kB boundary is the start of the admin completion queue
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// 3rd 4kB boundary is the start of I/O submission queue
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// 4th 4kB boundary is the start of I/O completion queue
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// 5th 4kB boundary is the start of PRP list buffers
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//
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VOID *Buffer;
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VOID *BufferMapping;
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//
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// Pointers to 4kB aligned submission & completion queues
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//
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NVME_SQ *SqBuffer[NVME_MAX_QUEUES];
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NVME_CQ *CqBuffer[NVME_MAX_QUEUES];
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//
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// Submission and completion queue indices
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//
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NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];
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NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];
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UINT8 Pt[NVME_MAX_QUEUES];
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UINT16 Cid[NVME_MAX_QUEUES];
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//
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// Nvme controller capabilities
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//
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NVME_CAP Cap;
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//
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// Namespaces information on the controller
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//
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UINT32 ActiveNamespaceNum;
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PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
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};
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#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a) \
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CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIoPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
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#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a) \
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CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
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#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_STROAGE_SECURITY(a) \
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CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, StorageSecurityPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
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#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NVME_PASSTHRU(a) \
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CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, NvmePassThruPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
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#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a) \
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CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
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//
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// Internal functions
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//
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/**
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Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
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OperationBusMasterCommonBuffer64 mapping.
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@param Pages The number of pages to allocate.
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@param HostAddress A pointer to store the base system memory address of the
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allocated range.
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@param DeviceAddress The resulting map address for the bus master PCI controller to use to
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access the hosts HostAddress.
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@param Mapping A resulting value to pass to Unmap().
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@retval EFI_SUCCESS The requested memory pages were allocated.
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@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
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MEMORY_WRITE_COMBINE and MEMORY_CACHED.
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@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
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@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
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**/
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EFI_STATUS
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IoMmuAllocateBuffer (
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IN UINTN Pages,
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OUT VOID **HostAddress,
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OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
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OUT VOID **Mapping
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);
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/**
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Frees memory that was allocated with AllocateBuffer().
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@param Pages The number of pages to free.
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@param HostAddress The base system memory address of the allocated range.
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@param Mapping The mapping value returned from Map().
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@retval EFI_SUCCESS The requested memory pages were freed.
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@retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
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was not allocated with AllocateBuffer().
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**/
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EFI_STATUS
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IoMmuFreeBuffer (
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IN UINTN Pages,
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IN VOID *HostAddress,
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IN VOID *Mapping
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);
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/**
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Provides the controller-specific addresses required to access system memory from a
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DMA bus master.
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@param Operation Indicates if the bus master is going to read or write to system memory.
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@param HostAddress The system memory address to map to the PCI controller.
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@param NumberOfBytes On input the number of bytes to map. On output the number of bytes
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that were mapped.
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@param DeviceAddress The resulting map address for the bus master PCI controller to use to
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access the hosts HostAddress.
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@param Mapping A resulting value to pass to Unmap().
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@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
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@retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
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@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
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@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
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@retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
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**/
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EFI_STATUS
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IoMmuMap (
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IN EDKII_IOMMU_OPERATION Operation,
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IN VOID *HostAddress,
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IN OUT UINTN *NumberOfBytes,
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OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
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OUT VOID **Mapping
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);
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/**
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Completes the Map() operation and releases any corresponding resources.
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@param Mapping The mapping value returned from Map().
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@retval EFI_SUCCESS The range was unmapped.
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@retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
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@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
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**/
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EFI_STATUS
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IoMmuUnmap (
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IN VOID *Mapping
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);
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/**
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One notified function to cleanup the allocated resources at the end of PEI.
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@param[in] PeiServices Pointer to PEI Services Table.
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@param[in] NotifyDescriptor Pointer to the descriptor for the Notification
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event that caused this function to execute.
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@param[in] Ppi Pointer to the PPI data associated with this function.
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@retval EFI_SUCCESS The function completes successfully
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**/
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EFI_STATUS
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EFIAPI
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NvmePeimEndOfPei (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
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IN VOID *Ppi
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);
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/**
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Get the size of the current device path instance.
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@param[in] DevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL
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structure.
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@param[out] InstanceSize The size of the current device path instance.
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@param[out] EntireDevicePathEnd Indicate whether the instance is the last
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one in the device path strucure.
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@retval EFI_SUCCESS The size of the current device path instance is fetched.
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@retval Others Fails to get the size of the current device path instance.
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**/
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EFI_STATUS
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GetDevicePathInstanceSize (
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IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
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OUT UINTN *InstanceSize,
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OUT BOOLEAN *EntireDevicePathEnd
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);
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/**
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Check the validity of the device path of a NVM Express host controller.
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@param[in] DevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL
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structure.
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@param[in] DevicePathLength The length of the device path.
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@retval EFI_SUCCESS The device path is valid.
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@retval EFI_INVALID_PARAMETER The device path is invalid.
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**/
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EFI_STATUS
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NvmeIsHcDevicePathValid (
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IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
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IN UINTN DevicePathLength
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);
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/**
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Build the device path for an Nvm Express device with given namespace identifier
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and namespace extended unique identifier.
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@param[in] Private A pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA
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data structure.
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@param[in] NamespaceId The given namespace identifier.
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@param[in] NamespaceUuid The given namespace extended unique identifier.
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@param[out] DevicePathLength The length of the device path in bytes specified
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by DevicePath.
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@param[out] DevicePath The device path of Nvm Express device.
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@retval EFI_SUCCESS The operation succeeds.
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@retval EFI_INVALID_PARAMETER The parameters are invalid.
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@retval EFI_OUT_OF_RESOURCES The operation fails due to lack of resources.
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**/
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EFI_STATUS
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NvmeBuildDevicePath (
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IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN UINT32 NamespaceId,
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IN UINT64 NamespaceUuid,
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OUT UINTN *DevicePathLength,
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OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
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);
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/**
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Determine if a specific NVM Express controller can be skipped for S3 phase.
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@param[in] HcDevicePath Device path of the controller.
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@param[in] HcDevicePathLength Length of the device path specified by
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HcDevicePath.
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@retval The number of ports that need to be enumerated.
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**/
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BOOLEAN
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NvmeS3SkipThisController (
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IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,
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IN UINTN HcDevicePathLength
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);
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#endif
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