mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
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411 lines
12 KiB
Perl
411 lines
12 KiB
Perl
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#!/usr/bin/env perl
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# ====================================================================
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# [Re]written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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# At some point it became apparent that the original SSLeay RC4
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# assembler implementation performs suboptimally on latest IA-32
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# microarchitectures. After re-tuning performance has changed as
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# following:
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#
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# Pentium -10%
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# Pentium III +12%
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# AMD +50%(*)
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# P4 +250%(**)
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#
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# (*) This number is actually a trade-off:-) It's possible to
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# achieve +72%, but at the cost of -48% off PIII performance.
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# In other words code performing further 13% faster on AMD
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# would perform almost 2 times slower on Intel PIII...
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# For reference! This code delivers ~80% of rc4-amd64.pl
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# performance on the same Opteron machine.
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# (**) This number requires compressed key schedule set up by
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# RC4_set_key [see commentary below for further details].
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#
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# <appro@fy.chalmers.se>
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# May 2011
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#
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# Optimize for Core2 and Westmere [and incidentally Opteron]. Current
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# performance in cycles per processed byte (less is better) and
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# improvement relative to previous version of this module is:
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#
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# Pentium 10.2 # original numbers
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# Pentium III 7.8(*)
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# Intel P4 7.5
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#
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# Opteron 6.1/+20% # new MMX numbers
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# Core2 5.3/+67%(**)
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# Westmere 5.1/+94%(**)
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# Sandy Bridge 5.0/+8%
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# Atom 12.6/+6%
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#
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# (*) PIII can actually deliver 6.6 cycles per byte with MMX code,
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# but this specific code performs poorly on Core2. And vice
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# versa, below MMX/SSE code delivering 5.8/7.1 on Core2 performs
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# poorly on PIII, at 8.0/14.5:-( As PIII is not a "hot" CPU
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# [anymore], I chose to discard PIII-specific code path and opt
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# for original IALU-only code, which is why MMX/SSE code path
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# is guarded by SSE2 bit (see below), not MMX/SSE.
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# (**) Performance vs. block size on Core2 and Westmere had a maximum
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# at ... 64 bytes block size. And it was quite a maximum, 40-60%
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# in comparison to largest 8KB block size. Above improvement
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# coefficients are for the largest block size.
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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push(@INC,"${dir}","${dir}../../perlasm");
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require "x86asm.pl";
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&asm_init($ARGV[0],"rc4-586.pl");
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$xx="eax";
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$yy="ebx";
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$tx="ecx";
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$ty="edx";
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$inp="esi";
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$out="ebp";
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$dat="edi";
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sub RC4_loop {
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my $i=shift;
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my $func = ($i==0)?*mov:*or;
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&add (&LB($yy),&LB($tx));
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&mov ($ty,&DWP(0,$dat,$yy,4));
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&mov (&DWP(0,$dat,$yy,4),$tx);
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&mov (&DWP(0,$dat,$xx,4),$ty);
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&add ($ty,$tx);
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&inc (&LB($xx));
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&and ($ty,0xff);
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&ror ($out,8) if ($i!=0);
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if ($i<3) {
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&mov ($tx,&DWP(0,$dat,$xx,4));
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} else {
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&mov ($tx,&wparam(3)); # reload [re-biased] out
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}
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&$func ($out,&DWP(0,$dat,$ty,4));
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}
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if ($alt=0) {
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# >20% faster on Atom and Sandy Bridge[!], 8% faster on Opteron,
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# but ~40% slower on Core2 and Westmere... Attempt to add movz
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# brings down Opteron by 25%, Atom and Sandy Bridge by 15%, yet
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# on Core2 with movz it's almost 20% slower than below alternative
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# code... Yes, it's a total mess...
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my @XX=($xx,$out);
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$RC4_loop_mmx = sub { # SSE actually...
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my $i=shift;
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my $j=$i<=0?0:$i>>1;
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my $mm=$i<=0?"mm0":"mm".($i&1);
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&add (&LB($yy),&LB($tx));
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&lea (@XX[1],&DWP(1,@XX[0]));
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&pxor ("mm2","mm0") if ($i==0);
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&psllq ("mm1",8) if ($i==0);
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&and (@XX[1],0xff);
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&pxor ("mm0","mm0") if ($i<=0);
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&mov ($ty,&DWP(0,$dat,$yy,4));
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&mov (&DWP(0,$dat,$yy,4),$tx);
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&pxor ("mm1","mm2") if ($i==0);
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&mov (&DWP(0,$dat,$XX[0],4),$ty);
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&add (&LB($ty),&LB($tx));
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&movd (@XX[0],"mm7") if ($i==0);
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&mov ($tx,&DWP(0,$dat,@XX[1],4));
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&pxor ("mm1","mm1") if ($i==1);
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&movq ("mm2",&QWP(0,$inp)) if ($i==1);
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&movq (&QWP(-8,(@XX[0],$inp)),"mm1") if ($i==0);
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&pinsrw ($mm,&DWP(0,$dat,$ty,4),$j);
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push (@XX,shift(@XX)) if ($i>=0);
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}
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} else {
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# Using pinsrw here improves performane on Intel CPUs by 2-3%, but
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# brings down AMD by 7%...
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$RC4_loop_mmx = sub {
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my $i=shift;
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&add (&LB($yy),&LB($tx));
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&psllq ("mm1",8*(($i-1)&7)) if (abs($i)!=1);
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&mov ($ty,&DWP(0,$dat,$yy,4));
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&mov (&DWP(0,$dat,$yy,4),$tx);
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&mov (&DWP(0,$dat,$xx,4),$ty);
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&inc ($xx);
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&add ($ty,$tx);
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&movz ($xx,&LB($xx)); # (*)
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&movz ($ty,&LB($ty)); # (*)
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&pxor ("mm2",$i==1?"mm0":"mm1") if ($i>=0);
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&movq ("mm0",&QWP(0,$inp)) if ($i<=0);
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&movq (&QWP(-8,($out,$inp)),"mm2") if ($i==0);
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&mov ($tx,&DWP(0,$dat,$xx,4));
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&movd ($i>0?"mm1":"mm2",&DWP(0,$dat,$ty,4));
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# (*) This is the key to Core2 and Westmere performance.
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# Whithout movz out-of-order execution logic confuses
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# itself and fails to reorder loads and stores. Problem
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# appears to be fixed in Sandy Bridge...
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}
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}
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&external_label("OPENSSL_ia32cap_P");
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# void RC4(RC4_KEY *key,size_t len,const unsigned char *inp,unsigned char *out);
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&function_begin("RC4");
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&mov ($dat,&wparam(0)); # load key schedule pointer
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&mov ($ty, &wparam(1)); # load len
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&mov ($inp,&wparam(2)); # load inp
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&mov ($out,&wparam(3)); # load out
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&xor ($xx,$xx); # avoid partial register stalls
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&xor ($yy,$yy);
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&cmp ($ty,0); # safety net
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&je (&label("abort"));
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&mov (&LB($xx),&BP(0,$dat)); # load key->x
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&mov (&LB($yy),&BP(4,$dat)); # load key->y
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&add ($dat,8);
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&lea ($tx,&DWP(0,$inp,$ty));
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&sub ($out,$inp); # re-bias out
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&mov (&wparam(1),$tx); # save input+len
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&inc (&LB($xx));
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# detect compressed key schedule...
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&cmp (&DWP(256,$dat),-1);
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&je (&label("RC4_CHAR"));
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&mov ($tx,&DWP(0,$dat,$xx,4));
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&and ($ty,-4); # how many 4-byte chunks?
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&jz (&label("loop1"));
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&test ($ty,-8);
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&mov (&wparam(3),$out); # $out as accumulator in these loops
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&jz (&label("go4loop4"));
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&picmeup($out,"OPENSSL_ia32cap_P");
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&bt (&DWP(0,$out),26); # check SSE2 bit [could have been MMX]
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&jnc (&label("go4loop4"));
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&mov ($out,&wparam(3)) if (!$alt);
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&movd ("mm7",&wparam(3)) if ($alt);
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&and ($ty,-8);
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&lea ($ty,&DWP(-8,$inp,$ty));
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&mov (&DWP(-4,$dat),$ty); # save input+(len/8)*8-8
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&$RC4_loop_mmx(-1);
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&jmp(&label("loop_mmx_enter"));
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&set_label("loop_mmx",16);
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&$RC4_loop_mmx(0);
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&set_label("loop_mmx_enter");
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for ($i=1;$i<8;$i++) { &$RC4_loop_mmx($i); }
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&mov ($ty,$yy);
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&xor ($yy,$yy); # this is second key to Core2
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&mov (&LB($yy),&LB($ty)); # and Westmere performance...
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&cmp ($inp,&DWP(-4,$dat));
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&lea ($inp,&DWP(8,$inp));
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&jb (&label("loop_mmx"));
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if ($alt) {
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&movd ($out,"mm7");
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&pxor ("mm2","mm0");
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&psllq ("mm1",8);
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&pxor ("mm1","mm2");
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&movq (&QWP(-8,$out,$inp),"mm1");
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} else {
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&psllq ("mm1",56);
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&pxor ("mm2","mm1");
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&movq (&QWP(-8,$out,$inp),"mm2");
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}
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&emms ();
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&cmp ($inp,&wparam(1)); # compare to input+len
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&je (&label("done"));
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&jmp (&label("loop1"));
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&set_label("go4loop4",16);
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&lea ($ty,&DWP(-4,$inp,$ty));
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&mov (&wparam(2),$ty); # save input+(len/4)*4-4
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&set_label("loop4");
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for ($i=0;$i<4;$i++) { RC4_loop($i); }
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&ror ($out,8);
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&xor ($out,&DWP(0,$inp));
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&cmp ($inp,&wparam(2)); # compare to input+(len/4)*4-4
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&mov (&DWP(0,$tx,$inp),$out);# $tx holds re-biased out here
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&lea ($inp,&DWP(4,$inp));
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&mov ($tx,&DWP(0,$dat,$xx,4));
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&jb (&label("loop4"));
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&cmp ($inp,&wparam(1)); # compare to input+len
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&je (&label("done"));
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&mov ($out,&wparam(3)); # restore $out
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&set_label("loop1",16);
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&add (&LB($yy),&LB($tx));
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&mov ($ty,&DWP(0,$dat,$yy,4));
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&mov (&DWP(0,$dat,$yy,4),$tx);
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&mov (&DWP(0,$dat,$xx,4),$ty);
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&add ($ty,$tx);
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&inc (&LB($xx));
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&and ($ty,0xff);
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&mov ($ty,&DWP(0,$dat,$ty,4));
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&xor (&LB($ty),&BP(0,$inp));
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&lea ($inp,&DWP(1,$inp));
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&mov ($tx,&DWP(0,$dat,$xx,4));
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&cmp ($inp,&wparam(1)); # compare to input+len
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&mov (&BP(-1,$out,$inp),&LB($ty));
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&jb (&label("loop1"));
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&jmp (&label("done"));
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# this is essentially Intel P4 specific codepath...
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&set_label("RC4_CHAR",16);
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&movz ($tx,&BP(0,$dat,$xx));
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# strangely enough unrolled loop performs over 20% slower...
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&set_label("cloop1");
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&add (&LB($yy),&LB($tx));
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&movz ($ty,&BP(0,$dat,$yy));
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&mov (&BP(0,$dat,$yy),&LB($tx));
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&mov (&BP(0,$dat,$xx),&LB($ty));
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&add (&LB($ty),&LB($tx));
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&movz ($ty,&BP(0,$dat,$ty));
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&add (&LB($xx),1);
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&xor (&LB($ty),&BP(0,$inp));
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&lea ($inp,&DWP(1,$inp));
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&movz ($tx,&BP(0,$dat,$xx));
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&cmp ($inp,&wparam(1));
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&mov (&BP(-1,$out,$inp),&LB($ty));
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&jb (&label("cloop1"));
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&set_label("done");
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&dec (&LB($xx));
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&mov (&DWP(-4,$dat),$yy); # save key->y
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&mov (&BP(-8,$dat),&LB($xx)); # save key->x
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&set_label("abort");
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&function_end("RC4");
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########################################################################
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$inp="esi";
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$out="edi";
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$idi="ebp";
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$ido="ecx";
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$idx="edx";
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# void RC4_set_key(RC4_KEY *key,int len,const unsigned char *data);
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&function_begin("private_RC4_set_key");
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&mov ($out,&wparam(0)); # load key
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&mov ($idi,&wparam(1)); # load len
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&mov ($inp,&wparam(2)); # load data
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&picmeup($idx,"OPENSSL_ia32cap_P");
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&lea ($out,&DWP(2*4,$out)); # &key->data
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&lea ($inp,&DWP(0,$inp,$idi)); # $inp to point at the end
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&neg ($idi);
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&xor ("eax","eax");
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&mov (&DWP(-4,$out),$idi); # borrow key->y
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&bt (&DWP(0,$idx),20); # check for bit#20
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&jc (&label("c1stloop"));
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&set_label("w1stloop",16);
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&mov (&DWP(0,$out,"eax",4),"eax"); # key->data[i]=i;
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&add (&LB("eax"),1); # i++;
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&jnc (&label("w1stloop"));
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&xor ($ido,$ido);
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&xor ($idx,$idx);
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&set_label("w2ndloop",16);
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&mov ("eax",&DWP(0,$out,$ido,4));
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&add (&LB($idx),&BP(0,$inp,$idi));
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&add (&LB($idx),&LB("eax"));
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&add ($idi,1);
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&mov ("ebx",&DWP(0,$out,$idx,4));
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&jnz (&label("wnowrap"));
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&mov ($idi,&DWP(-4,$out));
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&set_label("wnowrap");
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&mov (&DWP(0,$out,$idx,4),"eax");
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&mov (&DWP(0,$out,$ido,4),"ebx");
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&add (&LB($ido),1);
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&jnc (&label("w2ndloop"));
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&jmp (&label("exit"));
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# Unlike all other x86 [and x86_64] implementations, Intel P4 core
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# [including EM64T] was found to perform poorly with above "32-bit" key
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# schedule, a.k.a. RC4_INT. Performance improvement for IA-32 hand-coded
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# assembler turned out to be 3.5x if re-coded for compressed 8-bit one,
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# a.k.a. RC4_CHAR! It's however inappropriate to just switch to 8-bit
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# schedule for x86[_64], because non-P4 implementations suffer from
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# significant performance losses then, e.g. PIII exhibits >2x
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# deterioration, and so does Opteron. In order to assure optimal
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# all-round performance, we detect P4 at run-time and set up compressed
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# key schedule, which is recognized by RC4 procedure.
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&set_label("c1stloop",16);
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&mov (&BP(0,$out,"eax"),&LB("eax")); # key->data[i]=i;
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&add (&LB("eax"),1); # i++;
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&jnc (&label("c1stloop"));
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&xor ($ido,$ido);
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&xor ($idx,$idx);
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&xor ("ebx","ebx");
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&set_label("c2ndloop",16);
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&mov (&LB("eax"),&BP(0,$out,$ido));
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&add (&LB($idx),&BP(0,$inp,$idi));
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&add (&LB($idx),&LB("eax"));
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&add ($idi,1);
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&mov (&LB("ebx"),&BP(0,$out,$idx));
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&jnz (&label("cnowrap"));
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&mov ($idi,&DWP(-4,$out));
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&set_label("cnowrap");
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&mov (&BP(0,$out,$idx),&LB("eax"));
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&mov (&BP(0,$out,$ido),&LB("ebx"));
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&add (&LB($ido),1);
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&jnc (&label("c2ndloop"));
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|
||
|
&mov (&DWP(256,$out),-1); # mark schedule as compressed
|
||
|
|
||
|
&set_label("exit");
|
||
|
&xor ("eax","eax");
|
||
|
&mov (&DWP(-8,$out),"eax"); # key->x=0;
|
||
|
&mov (&DWP(-4,$out),"eax"); # key->y=0;
|
||
|
&function_end("private_RC4_set_key");
|
||
|
|
||
|
# const char *RC4_options(void);
|
||
|
&function_begin_B("RC4_options");
|
||
|
&call (&label("pic_point"));
|
||
|
&set_label("pic_point");
|
||
|
&blindpop("eax");
|
||
|
&lea ("eax",&DWP(&label("opts")."-".&label("pic_point"),"eax"));
|
||
|
&picmeup("edx","OPENSSL_ia32cap_P");
|
||
|
&mov ("edx",&DWP(0,"edx"));
|
||
|
&bt ("edx",20);
|
||
|
&jc (&label("1xchar"));
|
||
|
&bt ("edx",26);
|
||
|
&jnc (&label("ret"));
|
||
|
&add ("eax",25);
|
||
|
&ret ();
|
||
|
&set_label("1xchar");
|
||
|
&add ("eax",12);
|
||
|
&set_label("ret");
|
||
|
&ret ();
|
||
|
&set_label("opts",64);
|
||
|
&asciz ("rc4(4x,int)");
|
||
|
&asciz ("rc4(1x,char)");
|
||
|
&asciz ("rc4(8x,mmx)");
|
||
|
&asciz ("RC4 for x86, CRYPTOGAMS by <appro\@openssl.org>");
|
||
|
&align (64);
|
||
|
&function_end_B("RC4_options");
|
||
|
|
||
|
&asm_finish();
|
||
|
|