mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-12-05 13:33:33 +01:00
640 lines
21 KiB
C
640 lines
21 KiB
C
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/** @file
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Provides some data structure definitions used by the SD/MMC host controller driver.
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Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SD_MMC_PCI_HCI_H_
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#define _SD_MMC_PCI_HCI_H_
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//
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// SD Host Controller SlotInfo Register Offset
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//
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#define SD_MMC_HC_SLOT_OFFSET 0x40
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#define SD_MMC_HC_MAX_SLOT 6
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//
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// SD Host Controller MMIO Register Offset
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//
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#define SD_MMC_HC_SDMA_ADDR 0x00
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#define SD_MMC_HC_ARG2 0x00
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#define SD_MMC_HC_BLK_SIZE 0x04
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#define SD_MMC_HC_BLK_COUNT 0x06
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#define SD_MMC_HC_ARG1 0x08
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#define SD_MMC_HC_TRANS_MOD 0x0C
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#define SD_MMC_HC_COMMAND 0x0E
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#define SD_MMC_HC_RESPONSE 0x10
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#define SD_MMC_HC_BUF_DAT_PORT 0x20
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#define SD_MMC_HC_PRESENT_STATE 0x24
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#define SD_MMC_HC_HOST_CTRL1 0x28
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#define SD_MMC_HC_POWER_CTRL 0x29
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#define SD_MMC_HC_BLK_GAP_CTRL 0x2A
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#define SD_MMC_HC_WAKEUP_CTRL 0x2B
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#define SD_MMC_HC_CLOCK_CTRL 0x2C
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#define SD_MMC_HC_TIMEOUT_CTRL 0x2E
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#define SD_MMC_HC_SW_RST 0x2F
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#define SD_MMC_HC_NOR_INT_STS 0x30
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#define SD_MMC_HC_ERR_INT_STS 0x32
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#define SD_MMC_HC_NOR_INT_STS_EN 0x34
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#define SD_MMC_HC_ERR_INT_STS_EN 0x36
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#define SD_MMC_HC_NOR_INT_SIG_EN 0x38
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#define SD_MMC_HC_ERR_INT_SIG_EN 0x3A
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#define SD_MMC_HC_AUTO_CMD_ERR_STS 0x3C
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#define SD_MMC_HC_HOST_CTRL2 0x3E
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#define SD_MMC_HC_CAP 0x40
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#define SD_MMC_HC_MAX_CURRENT_CAP 0x48
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#define SD_MMC_HC_FORCE_EVT_AUTO_CMD 0x50
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#define SD_MMC_HC_FORCE_EVT_ERR_INT 0x52
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#define SD_MMC_HC_ADMA_ERR_STS 0x54
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#define SD_MMC_HC_ADMA_SYS_ADDR 0x58
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#define SD_MMC_HC_PRESET_VAL 0x60
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#define SD_MMC_HC_SHARED_BUS_CTRL 0xE0
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#define SD_MMC_HC_SLOT_INT_STS 0xFC
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#define SD_MMC_HC_CTRL_VER 0xFE
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//
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// SD Host Controller bits to HOST_CTRL2 register
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//
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#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
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#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
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#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
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#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
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#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
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#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
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#define SD_MMC_HC_CTRL_MMC_LEGACY 0x0000
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#define SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001
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#define SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004
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#define SD_MMC_HC_CTRL_MMC_HS200 0x0003
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#define SD_MMC_HC_CTRL_MMC_HS400 0x0005
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#define SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK 0x0030
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//
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// The transfer modes supported by SD Host Controller
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//
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typedef enum {
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SdMmcNoData,
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SdMmcPioMode,
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SdMmcSdmaMode,
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SdMmcAdma32bMode,
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SdMmcAdma64bV3Mode,
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SdMmcAdma64bV4Mode
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} SD_MMC_HC_TRANSFER_MODE;
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//
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// The ADMA transfer lengths supported by SD Host Controller
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//
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typedef enum {
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SdMmcAdmaLen16b,
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SdMmcAdmaLen26b
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} SD_MMC_HC_ADMA_LENGTH_MODE;
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//
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// The maximum data length of each descriptor line
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//
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#define ADMA_MAX_DATA_PER_LINE_16B SIZE_64KB
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#define ADMA_MAX_DATA_PER_LINE_26B SIZE_64MB
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//
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// ADMA descriptor for 32b addressing.
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//
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typedef struct {
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UINT32 Valid:1;
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UINT32 End:1;
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UINT32 Int:1;
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UINT32 Reserved:1;
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UINT32 Act:2;
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UINT32 UpperLength:10;
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UINT32 LowerLength:16;
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UINT32 Address;
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} SD_MMC_HC_ADMA_32_DESC_LINE;
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//
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// ADMA descriptor for 64b addressing.
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//
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typedef struct {
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UINT32 Valid:1;
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UINT32 End:1;
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UINT32 Int:1;
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UINT32 Reserved:1;
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UINT32 Act:2;
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UINT32 UpperLength:10;
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UINT32 LowerLength:16;
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UINT32 LowerAddress;
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UINT32 UpperAddress;
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} SD_MMC_HC_ADMA_64_V3_DESC_LINE;
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typedef struct {
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UINT32 Valid:1;
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UINT32 End:1;
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UINT32 Int:1;
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UINT32 Reserved:1;
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UINT32 Act:2;
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UINT32 UpperLength:10;
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UINT32 LowerLength:16;
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UINT32 LowerAddress;
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UINT32 UpperAddress;
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UINT32 Reserved1;
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} SD_MMC_HC_ADMA_64_V4_DESC_LINE;
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#define SD_MMC_SDMA_BOUNDARY 512 * 1024
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#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))
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typedef struct {
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UINT8 FirstBar:3; // bit 0:2
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UINT8 Reserved:1; // bit 3
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UINT8 SlotNum:3; // bit 4:6
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UINT8 Reserved1:1; // bit 7
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} SD_MMC_HC_SLOT_INFO;
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typedef struct {
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UINT32 TimeoutFreq:6; // bit 0:5
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UINT32 Reserved:1; // bit 6
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UINT32 TimeoutUnit:1; // bit 7
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UINT32 BaseClkFreq:8; // bit 8:15
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UINT32 MaxBlkLen:2; // bit 16:17
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UINT32 BusWidth8:1; // bit 18
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UINT32 Adma2:1; // bit 19
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UINT32 Reserved2:1; // bit 20
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UINT32 HighSpeed:1; // bit 21
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UINT32 Sdma:1; // bit 22
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UINT32 SuspRes:1; // bit 23
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UINT32 Voltage33:1; // bit 24
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UINT32 Voltage30:1; // bit 25
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UINT32 Voltage18:1; // bit 26
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UINT32 SysBus64V4:1; // bit 27
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UINT32 SysBus64V3:1; // bit 28
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UINT32 AsyncInt:1; // bit 29
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UINT32 SlotType:2; // bit 30:31
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UINT32 Sdr50:1; // bit 32
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UINT32 Sdr104:1; // bit 33
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UINT32 Ddr50:1; // bit 34
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UINT32 Reserved3:1; // bit 35
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UINT32 DriverTypeA:1; // bit 36
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UINT32 DriverTypeC:1; // bit 37
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UINT32 DriverTypeD:1; // bit 38
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UINT32 DriverType4:1; // bit 39
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UINT32 TimerCount:4; // bit 40:43
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UINT32 Reserved4:1; // bit 44
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UINT32 TuningSDR50:1; // bit 45
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UINT32 RetuningMod:2; // bit 46:47
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UINT32 ClkMultiplier:8; // bit 48:55
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UINT32 Reserved5:7; // bit 56:62
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UINT32 Hs400:1; // bit 63
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} SD_MMC_HC_SLOT_CAP;
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//
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// SD Host controller version
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//
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#define SD_MMC_HC_CTRL_VER_100 0x00
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#define SD_MMC_HC_CTRL_VER_200 0x01
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#define SD_MMC_HC_CTRL_VER_300 0x02
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#define SD_MMC_HC_CTRL_VER_400 0x03
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#define SD_MMC_HC_CTRL_VER_410 0x04
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#define SD_MMC_HC_CTRL_VER_420 0x05
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//
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// SD Host controller V4 enhancements
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//
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#define SD_MMC_HC_V4_EN BIT12
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#define SD_MMC_HC_64_ADDR_EN BIT13
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#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10
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/**
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Dump the content of SD/MMC host controller's Capability Register.
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@param[in] Slot The slot number of the SD card to send the command to.
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@param[in] Capability The buffer to store the capability data.
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**/
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VOID
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DumpCapabilityReg (
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IN UINT8 Slot,
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IN SD_MMC_HC_SLOT_CAP *Capability
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);
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/**
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Read SlotInfo register from SD/MMC host controller pci config space.
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@param[in] PciIo The PCI IO protocol instance.
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@param[out] FirstBar The buffer to store the first BAR value.
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@param[out] SlotNum The buffer to store the supported slot number.
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@retval EFI_SUCCESS The operation succeeds.
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@retval Others The operation fails.
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**/
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EFI_STATUS
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EFIAPI
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SdMmcHcGetSlotInfo (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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OUT UINT8 *FirstBar,
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OUT UINT8 *SlotNum
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);
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/**
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Read/Write specified SD/MMC host controller mmio register.
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@param[in] PciIo The PCI IO protocol instance.
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@param[in] BarIndex The BAR index of the standard PCI Configuration
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header to use as the base address for the memory
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operation to perform.
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@param[in] Offset The offset within the selected BAR to start the
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memory operation.
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@param[in] Read A boolean to indicate it's read or write operation.
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@param[in] Count The width of the mmio register in bytes.
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Must be 1, 2 , 4 or 8 bytes.
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@param[in, out] Data For read operations, the destination buffer to store
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the results. For write operations, the source buffer
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to write data from. The caller is responsible for
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having ownership of the data buffer and ensuring its
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size not less than Count bytes.
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@retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
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@retval EFI_SUCCESS The read/write operation succeeds.
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@retval Others The read/write operation fails.
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**/
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EFI_STATUS
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EFIAPI
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SdMmcHcRwMmio (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 BarIndex,
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IN UINT32 Offset,
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IN BOOLEAN Read,
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IN UINT8 Count,
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IN OUT VOID *Data
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);
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/**
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Do OR operation with the value of the specified SD/MMC host controller mmio register.
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@param[in] PciIo The PCI IO protocol instance.
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@param[in] BarIndex The BAR index of the standard PCI Configuration
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header to use as the base address for the memory
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operation to perform.
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@param[in] Offset The offset within the selected BAR to start the
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memory operation.
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@param[in] Count The width of the mmio register in bytes.
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Must be 1, 2 , 4 or 8 bytes.
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@param[in] OrData The pointer to the data used to do OR operation.
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The caller is responsible for having ownership of
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the data buffer and ensuring its size not less than
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Count bytes.
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@retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
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@retval EFI_SUCCESS The OR operation succeeds.
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@retval Others The OR operation fails.
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**/
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EFI_STATUS
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EFIAPI
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SdMmcHcOrMmio (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 BarIndex,
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IN UINT32 Offset,
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IN UINT8 Count,
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IN VOID *OrData
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);
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/**
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Do AND operation with the value of the specified SD/MMC host controller mmio register.
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@param[in] PciIo The PCI IO protocol instance.
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@param[in] BarIndex The BAR index of the standard PCI Configuration
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header to use as the base address for the memory
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operation to perform.
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@param[in] Offset The offset within the selected BAR to start the
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memory operation.
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@param[in] Count The width of the mmio register in bytes.
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Must be 1, 2 , 4 or 8 bytes.
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@param[in] AndData The pointer to the data used to do AND operation.
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The caller is responsible for having ownership of
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the data buffer and ensuring its size not less than
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Count bytes.
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@retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
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@retval EFI_SUCCESS The AND operation succeeds.
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@retval Others The AND operation fails.
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**/
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EFI_STATUS
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EFIAPI
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SdMmcHcAndMmio (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 BarIndex,
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IN UINT32 Offset,
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IN UINT8 Count,
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IN VOID *AndData
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);
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/**
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Wait for the value of the specified MMIO register set to the test value.
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@param[in] PciIo The PCI IO protocol instance.
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@param[in] BarIndex The BAR index of the standard PCI Configuration
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header to use as the base address for the memory
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operation to perform.
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@param[in] Offset The offset within the selected BAR to start the
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memory operation.
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@param[in] Count The width of the mmio register in bytes.
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Must be 1, 2, 4 or 8 bytes.
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@param[in] MaskValue The mask value of memory.
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@param[in] TestValue The test value of memory.
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@param[in] Timeout The time out value for wait memory set, uses 1
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microsecond as a unit.
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@retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
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range.
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@retval EFI_SUCCESS The MMIO register has expected value.
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@retval Others The MMIO operation fails.
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**/
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EFI_STATUS
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EFIAPI
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SdMmcHcWaitMmioSet (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 BarIndex,
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IN UINT32 Offset,
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IN UINT8 Count,
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IN UINT64 MaskValue,
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IN UINT64 TestValue,
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IN UINT64 Timeout
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);
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/**
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Get the controller version information from the specified slot.
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@param[in] PciIo The PCI IO protocol instance.
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@param[in] Slot The slot number of the SD card to send the command to.
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@param[out] Version The buffer to store the version information.
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@retval EFI_SUCCESS The operation executes successfully.
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@retval Others The operation fails.
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**/
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EFI_STATUS
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SdMmcHcGetControllerVersion (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 Slot,
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OUT UINT16 *Version
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);
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/**
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Set all interrupt status bits in Normal and Error Interrupt Status Enable
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register.
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@param[in] PciIo The PCI IO protocol instance.
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@param[in] Slot The slot number of the SD card to send the command to.
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@retval EFI_SUCCESS The operation executes successfully.
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@retval Others The operation fails.
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**/
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EFI_STATUS
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SdMmcHcEnableInterrupt (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 Slot
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);
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/**
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Get the capability data from the specified slot.
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@param[in] PciIo The PCI IO protocol instance.
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@param[in] Slot The slot number of the SD card to send the command to.
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@param[out] Capability The buffer to store the capability data.
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@retval EFI_SUCCESS The operation executes successfully.
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||
|
@retval Others The operation fails.
|
||
|
|
||
|
**/
|
||
|
EFI_STATUS
|
||
|
SdMmcHcGetCapability (
|
||
|
IN EFI_PCI_IO_PROTOCOL *PciIo,
|
||
|
IN UINT8 Slot,
|
||
|
OUT SD_MMC_HC_SLOT_CAP *Capability
|
||
|
);
|
||
|
|
||
|
/**
|
||
|
Get the maximum current capability data from the specified slot.
|
||
|
|
||
|
@param[in] PciIo The PCI IO protocol instance.
|
||
|
@param[in] Slot The slot number of the SD card to send the command to.
|
||
|
@param[out] MaxCurrent The buffer to store the maximum current capability data.
|
||
|
|
||
|
@retval EFI_SUCCESS The operation executes successfully.
|
||
|
@retval Others The operation fails.
|
||
|
|
||
|
**/
|
||
|
EFI_STATUS
|
||
|
SdMmcHcGetMaxCurrent (
|
||
|
IN EFI_PCI_IO_PROTOCOL *PciIo,
|
||
|
IN UINT8 Slot,
|
||
|
OUT UINT64 *MaxCurrent
|
||
|
);
|
||
|
|
||
|
/**
|
||
|
Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
|
||
|
slot.
|
||
|
|
||
|
Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
|
||
|
|
||
|
@param[in] PciIo The PCI IO protocol instance.
|
||
|
@param[in] Slot The slot number of the SD card to send the command to.
|
||
|
@param[out] MediaPresent The pointer to the media present boolean value.
|
||
|
|
||
|
@retval EFI_SUCCESS There is no media change happened.
|
||
|
@retval EFI_MEDIA_CHANGED There is media change happened.
|
||
|
@retval Others The detection fails.
|
||
|
|
||
|
**/
|
||
|
EFI_STATUS
|
||
|
SdMmcHcCardDetect (
|
||
|
IN EFI_PCI_IO_PROTOCOL *PciIo,
|
||
|
IN UINT8 Slot,
|
||
|
OUT BOOLEAN *MediaPresent
|
||
|
);
|
||
|
|
||
|
/**
|
||
|
Stop SD/MMC card clock.
|
||
|
|
||
|
Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
|
||
|
|
||
|
@param[in] PciIo The PCI IO protocol instance.
|
||
|
@param[in] Slot The slot number of the SD card to send the command to.
|
||
|
|
||
|
@retval EFI_SUCCESS Succeed to stop SD/MMC clock.
|
||
|
@retval Others Fail to stop SD/MMC clock.
|
||
|
|
||
|
**/
|
||
|
EFI_STATUS
|
||
|
SdMmcHcStopClock (
|
||
|
IN EFI_PCI_IO_PROTOCOL *PciIo,
|
||
|
IN UINT8 Slot
|
||
|
);
|
||
|
|
||
|
/**
|
||
|
SD/MMC card clock supply.
|
||
|
|
||
|
Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
|
||
|
|
||
|
@param[in] PciIo The PCI IO protocol instance.
|
||
|
@param[in] Slot The slot number of the SD card to send the command to.
|
||
|
@param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
|
||
|
@param[in] BaseClkFreq The base clock frequency of host controller in MHz.
|
||
|
@param[in] ControllerVer The version of host controller.
|
||
|
|
||
|
@retval EFI_SUCCESS The clock is supplied successfully.
|
||
|
@retval Others The clock isn't supplied successfully.
|
||
|
|
||
|
**/
|
||
|
EFI_STATUS
|
||
|
SdMmcHcClockSupply (
|
||
|
IN EFI_PCI_IO_PROTOCOL *PciIo,
|
||
|
IN UINT8 Slot,
|
||
|
IN UINT64 ClockFreq,
|
||
|
IN UINT32 BaseClkFreq,
|
||
|
IN UINT16 ControllerVer
|
||
|
);
|
||
|
|
||
|
/**
|
||
|
SD/MMC bus power control.
|
||
|
|
||
|
Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
|
||
|
|
||
|
@param[in] PciIo The PCI IO protocol instance.
|
||
|
@param[in] Slot The slot number of the SD card to send the command to.
|
||
|
@param[in] PowerCtrl The value setting to the power control register.
|
||
|
|
||
|
@retval TRUE There is a SD/MMC card attached.
|
||
|
@retval FALSE There is no a SD/MMC card attached.
|
||
|
|
||
|
**/
|
||
|
EFI_STATUS
|
||
|
SdMmcHcPowerControl (
|
||
|
IN EFI_PCI_IO_PROTOCOL *PciIo,
|
||
|
IN UINT8 Slot,
|
||
|
IN UINT8 PowerCtrl
|
||
|
);
|
||
|
|
||
|
/**
|
||
|
Set the SD/MMC bus width.
|
||
|
|
||
|
Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
|
||
|
|
||
|
@param[in] PciIo The PCI IO protocol instance.
|
||
|
@param[in] Slot The slot number of the SD card to send the command to.
|
||
|
@param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
|
||
|
|
||
|
@retval EFI_SUCCESS The bus width is set successfully.
|
||
|
@retval Others The bus width isn't set successfully.
|
||
|
|
||
|
**/
|
||
|
EFI_STATUS
|
||
|
SdMmcHcSetBusWidth (
|
||
|
IN EFI_PCI_IO_PROTOCOL *PciIo,
|
||
|
IN UINT8 Slot,
|
||
|
IN UINT16 BusWidth
|
||
|
);
|
||
|
|
||
|
/**
|
||
|
Supply SD/MMC card with lowest clock frequency at initialization.
|
||
|
|
||
|
@param[in] PciIo The PCI IO protocol instance.
|
||
|
@param[in] Slot The slot number of the SD card to send the command to.
|
||
|
@param[in] BaseClkFreq The base clock frequency of host controller in MHz.
|
||
|
@param[in] ControllerVer The version of host controller.
|
||
|
|
||
|
@retval EFI_SUCCESS The clock is supplied successfully.
|
||
|
@retval Others The clock isn't supplied successfully.
|
||
|
|
||
|
**/
|
||
|
EFI_STATUS
|
||
|
SdMmcHcInitClockFreq (
|
||
|
IN EFI_PCI_IO_PROTOCOL *PciIo,
|
||
|
IN UINT8 Slot,
|
||
|
IN UINT32 BaseClkFreq,
|
||
|
IN UINT16 ControllerVer
|
||
|
);
|
||
|
|
||
|
/**
|
||
|
Supply SD/MMC card with maximum voltage at initialization.
|
||
|
|
||
|
Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
|
||
|
|
||
|
@param[in] PciIo The PCI IO protocol instance.
|
||
|
@param[in] Slot The slot number of the SD card to send the command to.
|
||
|
@param[in] Capability The capability of the slot.
|
||
|
|
||
|
@retval EFI_SUCCESS The voltage is supplied successfully.
|
||
|
@retval Others The voltage isn't supplied successfully.
|
||
|
|
||
|
**/
|
||
|
EFI_STATUS
|
||
|
SdMmcHcInitPowerVoltage (
|
||
|
IN EFI_PCI_IO_PROTOCOL *PciIo,
|
||
|
IN UINT8 Slot,
|
||
|
IN SD_MMC_HC_SLOT_CAP Capability
|
||
|
);
|
||
|
|
||
|
/**
|
||
|
Initialize the Timeout Control register with most conservative value at initialization.
|
||
|
|
||
|
Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
|
||
|
|
||
|
@param[in] PciIo The PCI IO protocol instance.
|
||
|
@param[in] Slot The slot number of the SD card to send the command to.
|
||
|
|
||
|
@retval EFI_SUCCESS The timeout control register is configured successfully.
|
||
|
@retval Others The timeout control register isn't configured successfully.
|
||
|
|
||
|
**/
|
||
|
EFI_STATUS
|
||
|
SdMmcHcInitTimeoutCtrl (
|
||
|
IN EFI_PCI_IO_PROTOCOL *PciIo,
|
||
|
IN UINT8 Slot
|
||
|
);
|
||
|
|
||
|
/**
|
||
|
Set SD Host Controller control 2 registry according to selected speed.
|
||
|
|
||
|
@param[in] ControllerHandle The handle of the controller.
|
||
|
@param[in] PciIo The PCI IO protocol instance.
|
||
|
@param[in] Slot The slot number of the SD card to send the command to.
|
||
|
@param[in] Timing The timing to select.
|
||
|
|
||
|
@retval EFI_SUCCESS The timing is set successfully.
|
||
|
@retval Others The timing isn't set successfully.
|
||
|
**/
|
||
|
EFI_STATUS
|
||
|
SdMmcHcUhsSignaling (
|
||
|
IN EFI_HANDLE ControllerHandle,
|
||
|
IN EFI_PCI_IO_PROTOCOL *PciIo,
|
||
|
IN UINT8 Slot,
|
||
|
IN SD_MMC_BUS_MODE Timing
|
||
|
);
|
||
|
|
||
|
/**
|
||
|
Set driver strength in host controller.
|
||
|
|
||
|
@param[in] PciIo The PCI IO protocol instance.
|
||
|
@param[in] SlotIndex The slot index of the card.
|
||
|
@param[in] DriverStrength DriverStrength to set in the controller.
|
||
|
|
||
|
@retval EFI_SUCCESS Driver strength programmed successfully.
|
||
|
@retval Others Failed to set driver strength.
|
||
|
**/
|
||
|
EFI_STATUS
|
||
|
SdMmcSetDriverStrength (
|
||
|
IN EFI_PCI_IO_PROTOCOL *PciIo,
|
||
|
IN UINT8 SlotIndex,
|
||
|
IN SD_DRIVER_STRENGTH_TYPE DriverStrength
|
||
|
);
|
||
|
|
||
|
#endif
|