diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c b/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c
index b71a1a305..e3af49c8c 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c
@@ -21,15 +21,15 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gXhciComponentName =
//
// EFI Component Name 2 Protocol
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2 = {
- (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) XhciComponentNameGetDriverName,
- (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) XhciComponentNameGetControllerName,
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)XhciComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)XhciComponentNameGetControllerName,
"en"
};
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mXhciDriverNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mXhciDriverNameTable[] = {
{ "eng;en", L"Usb Xhci Driver" },
- { NULL , NULL }
+ { NULL, NULL }
};
/**
@@ -166,9 +166,9 @@ XhciComponentNameGetControllerName (
OUT CHAR16 **ControllerName
)
{
- EFI_STATUS Status;
- EFI_USB2_HC_PROTOCOL *Usb2Hc;
- USB_XHCI_INSTANCE *XhciDev;
+ EFI_STATUS Status;
+ EFI_USB2_HC_PROTOCOL *Usb2Hc;
+ USB_XHCI_INSTANCE *XhciDev;
//
// This is a device driver, so ChildHandle must be NULL.
@@ -185,7 +185,7 @@ XhciComponentNameGetControllerName (
gXhciDriverBinding.DriverBindingHandle,
&gEfiPciIoProtocolGuid
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -195,12 +195,12 @@ XhciComponentNameGetControllerName (
Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiUsb2HcProtocolGuid,
- (VOID **) &Usb2Hc,
+ (VOID **)&Usb2Hc,
gXhciDriverBinding.DriverBindingHandle,
ControllerHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -213,5 +213,4 @@ XhciComponentNameGetControllerName (
ControllerName,
(BOOLEAN)(This == &gXhciComponentName)
);
-
}
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h b/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h
index 13fbde165..103ad6057 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h
@@ -57,7 +57,6 @@ XhciComponentNameGetDriverName (
OUT CHAR16 **DriverName
);
-
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@@ -137,4 +136,3 @@ XhciComponentNameGetControllerName (
);
#endif
-
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
index d347ba022..99fb3521d 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
@@ -7,10 +7,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-
#include "Xhci.h"
-
/**
Allocate a block of memory to be used by the buffer pool.
@@ -22,21 +20,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Pages
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Pages
)
{
- USBHC_MEM_BLOCK *Block;
- EFI_PCI_IO_PROTOCOL *PciIo;
- VOID *BufHost;
- VOID *Mapping;
- EFI_PHYSICAL_ADDRESS MappedAddr;
- UINTN Bytes;
- EFI_STATUS Status;
+ USBHC_MEM_BLOCK *Block;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ VOID *BufHost;
+ VOID *Mapping;
+ EFI_PHYSICAL_ADDRESS MappedAddr;
+ UINTN Bytes;
+ EFI_STATUS Status;
PciIo = Pool->PciIo;
- Block = AllocateZeroPool(sizeof (USBHC_MEM_BLOCK));
+ Block = AllocateZeroPool (sizeof (USBHC_MEM_BLOCK));
if (Block == NULL) {
return NULL;
}
@@ -47,12 +45,12 @@ UsbHcAllocMemBlock (
//
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
- Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
- Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
- Block->Bits = AllocateZeroPool(Block->BitsLen);
+ Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
+ Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
+ Block->Bits = AllocateZeroPool (Block->BitsLen);
if (Block->Bits == NULL) {
- gBS->FreePool(Block);
+ gBS->FreePool (Block);
return NULL;
}
@@ -69,11 +67,11 @@ UsbHcAllocMemBlock (
0
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto FREE_BITARRAY;
}
- Bytes = EFI_PAGES_TO_SIZE (Pages);
+ Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
@@ -83,13 +81,13 @@ UsbHcAllocMemBlock (
&Mapping
);
- if (EFI_ERROR(Status) || (Bytes != EFI_PAGES_TO_SIZE (Pages))) {
+ if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (Pages))) {
goto FREE_BUFFER;
}
- Block->BufHost = BufHost;
- Block->Buf = (UINT8 *) ((UINTN) MappedAddr);
- Block->Mapping = Mapping;
+ Block->BufHost = BufHost;
+ Block->Buf = (UINT8 *)((UINTN)MappedAddr);
+ Block->Mapping = Mapping;
return Block;
@@ -97,12 +95,11 @@ FREE_BUFFER:
PciIo->FreeBuffer (PciIo, Pages, BufHost);
FREE_BITARRAY:
- gBS->FreePool(Block->Bits);
- gBS->FreePool(Block);
+ gBS->FreePool (Block->Bits);
+ gBS->FreePool (Block);
return NULL;
}
-
/**
Free the memory block from the memory pool.
@@ -112,11 +109,11 @@ FREE_BITARRAY:
**/
VOID
UsbHcFreeMemBlock (
- IN USBHC_MEM_POOL *Pool,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_POOL *Pool,
+ IN USBHC_MEM_BLOCK *Block
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
ASSERT ((Pool != NULL) && (Block != NULL));
@@ -128,11 +125,10 @@ UsbHcFreeMemBlock (
PciIo->Unmap (PciIo, Block->Mapping);
PciIo->FreeBuffer (PciIo, EFI_SIZE_TO_PAGES (Block->BufLen), Block->BufHost);
- gBS->FreePool(Block->Bits);
- gBS->FreePool(Block);
+ gBS->FreePool (Block->Bits);
+ gBS->FreePool (Block);
}
-
/**
Alloc some memory from the block.
@@ -145,22 +141,22 @@ UsbHcFreeMemBlock (
**/
VOID *
UsbHcAllocMemFromBlock (
- IN USBHC_MEM_BLOCK *Block,
- IN UINTN Units
+ IN USBHC_MEM_BLOCK *Block,
+ IN UINTN Units
)
{
- UINTN Byte;
- UINT8 Bit;
- UINTN StartByte;
- UINT8 StartBit;
- UINTN Available;
- UINTN Count;
+ UINTN Byte;
+ UINT8 Bit;
+ UINTN StartByte;
+ UINT8 StartBit;
+ UINTN Available;
+ UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
- StartByte = 0;
- StartBit = 0;
- Available = 0;
+ StartByte = 0;
+ StartBit = 0;
+ Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@@ -176,13 +172,12 @@ UsbHcAllocMemFromBlock (
}
NEXT_BIT (Byte, Bit);
-
} else {
NEXT_BIT (Byte, Bit);
- Available = 0;
- StartByte = Byte;
- StartBit = Bit;
+ Available = 0;
+ StartByte = Byte;
+ StartBit = Bit;
}
}
@@ -193,13 +188,13 @@ UsbHcAllocMemFromBlock (
//
// Mark the memory as allocated
//
- Byte = StartByte;
- Bit = StartBit;
+ Byte = StartByte;
+ Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -218,16 +213,16 @@ UsbHcAllocMemFromBlock (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINTN AllocSize;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINTN Offset;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINTN AllocSize;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -241,7 +236,7 @@ UsbHcGetPciAddrForHostAddr (
// scan the memory block list for the memory block that
// completely contains the allocated memory.
//
- if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
+ if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@@ -250,8 +245,8 @@ UsbHcGetPciAddrForHostAddr (
//
// calculate the pci memory address for host memory address.
//
- Offset = (UINT8 *)Mem - Block->BufHost;
- PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);
+ Offset = (UINT8 *)Mem - Block->BufHost;
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
@@ -267,16 +262,16 @@ UsbHcGetPciAddrForHostAddr (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINTN AllocSize;
- EFI_PHYSICAL_ADDRESS HostAddr;
- UINTN Offset;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINTN AllocSize;
+ EFI_PHYSICAL_ADDRESS HostAddr;
+ UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -290,7 +285,7 @@ UsbHcGetHostAddrForPciAddr (
// scan the memory block list for the memory block that
// completely contains the allocated memory.
//
- if ((Block->Buf <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->Buf + Block->BufLen))) {
+ if ((Block->Buf <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->Buf + Block->BufLen))) {
break;
}
}
@@ -299,8 +294,8 @@ UsbHcGetHostAddrForPciAddr (
//
// calculate the pci memory address for host memory address.
//
- Offset = (UINT8 *)Mem - Block->Buf;
- HostAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->BufHost + Offset);
+ Offset = (UINT8 *)Mem - Block->Buf;
+ HostAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->BufHost + Offset);
return HostAddr;
}
@@ -313,8 +308,8 @@ UsbHcGetHostAddrForPciAddr (
**/
VOID
UsbHcInsertMemBlockToPool (
- IN USBHC_MEM_BLOCK *Head,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Head,
+ IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@@ -322,7 +317,6 @@ UsbHcInsertMemBlockToPool (
Head->Next = Block;
}
-
/**
Is the memory block empty?
@@ -334,10 +328,10 @@ UsbHcInsertMemBlockToPool (
**/
BOOLEAN
UsbHcIsMemBlockEmpty (
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Block
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@@ -348,7 +342,6 @@ UsbHcIsMemBlockEmpty (
return TRUE;
}
-
/**
Unlink the memory block from the pool's list.
@@ -358,11 +351,11 @@ UsbHcIsMemBlockEmpty (
**/
VOID
UsbHcUnlinkMemBlock (
- IN USBHC_MEM_BLOCK *Head,
- IN USBHC_MEM_BLOCK *BlockToUnlink
+ IN USBHC_MEM_BLOCK *Head,
+ IN USBHC_MEM_BLOCK *BlockToUnlink
)
{
- USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *Block;
ASSERT ((Head != NULL) && (BlockToUnlink != NULL));
@@ -375,7 +368,6 @@ UsbHcUnlinkMemBlock (
}
}
-
/**
Initialize the memory management pool for the host controller.
@@ -390,7 +382,7 @@ UsbHcInitMemPool (
IN EFI_PCI_IO_PROTOCOL *PciIo
)
{
- USBHC_MEM_POOL *Pool;
+ USBHC_MEM_POOL *Pool;
Pool = AllocatePool (sizeof (USBHC_MEM_POOL));
@@ -398,18 +390,17 @@ UsbHcInitMemPool (
return Pool;
}
- Pool->PciIo = PciIo;
- Pool->Head = UsbHcAllocMemBlock (Pool, USBHC_MEM_DEFAULT_PAGES);
+ Pool->PciIo = PciIo;
+ Pool->Head = UsbHcAllocMemBlock (Pool, USBHC_MEM_DEFAULT_PAGES);
if (Pool->Head == NULL) {
- gBS->FreePool(Pool);
+ gBS->FreePool (Pool);
Pool = NULL;
}
return Pool;
}
-
/**
Release the memory management pool.
@@ -421,10 +412,10 @@ UsbHcInitMemPool (
**/
EFI_STATUS
UsbHcFreeMemPool (
- IN USBHC_MEM_POOL *Pool
+ IN USBHC_MEM_POOL *Pool
)
{
- USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@@ -439,11 +430,10 @@ UsbHcFreeMemPool (
}
UsbHcFreeMemBlock (Pool, Pool->Head);
- gBS->FreePool(Pool);
+ gBS->FreePool (Pool);
return EFI_SUCCESS;
}
-
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -456,16 +446,16 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- USBHC_MEM_BLOCK *NewBlock;
- VOID *Mem;
- UINTN AllocSize;
- UINTN Pages;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *NewBlock;
+ VOID *Mem;
+ UINTN AllocSize;
+ UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -503,7 +493,7 @@ UsbHcAllocateMem (
NewBlock = UsbHcAllocMemBlock (Pool, Pages);
if (NewBlock == NULL) {
- DEBUG ((EFI_D_ERROR, "UsbHcAllocateMem: failed to allocate block\n"));
+ DEBUG ((DEBUG_ERROR, "UsbHcAllocateMem: failed to allocate block\n"));
return NULL;
}
@@ -520,7 +510,6 @@ UsbHcAllocateMem (
return Mem;
}
-
/**
Free the allocated memory back to the memory pool.
@@ -531,22 +520,22 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINT8 *ToFree;
- UINTN AllocSize;
- UINTN Byte;
- UINTN Bit;
- UINTN Count;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINT8 *ToFree;
+ UINTN AllocSize;
+ UINTN Byte;
+ UINTN Bit;
+ UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
- ToFree = (UINT8 *) Mem;
+ ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@@ -557,8 +546,8 @@ UsbHcFreeMem (
//
// compute the start byte and bit in the bit array
//
- Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
- Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
+ Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
+ Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@@ -566,7 +555,7 @@ UsbHcFreeMem (
for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -589,7 +578,7 @@ UsbHcFreeMem (
UsbHcFreeMemBlock (Pool, Block);
}
- return ;
+ return;
}
/**
@@ -621,13 +610,13 @@ UsbHcAllocateAlignedPages (
OUT VOID **Mapping
)
{
- EFI_STATUS Status;
- VOID *Memory;
- UINTN AlignedMemory;
- UINTN AlignmentMask;
- UINTN UnalignedPages;
- UINTN RealPages;
- UINTN Bytes;
+ EFI_STATUS Status;
+ VOID *Memory;
+ UINTN AlignedMemory;
+ UINTN AlignmentMask;
+ UINTN UnalignedPages;
+ UINTN RealPages;
+ UINTN Bytes;
//
// Alignment must be a power of two or zero.
@@ -641,12 +630,13 @@ UsbHcAllocateAlignedPages (
if (Pages == 0) {
return EFI_INVALID_PARAMETER;
}
+
if (Alignment > EFI_PAGE_SIZE) {
//
// Calculate the total number of pages since alignment is larger than page size.
//
- AlignmentMask = Alignment - 1;
- RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
+ AlignmentMask = Alignment - 1;
+ RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
//
// Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
//
@@ -656,22 +646,24 @@ UsbHcAllocateAlignedPages (
PciIo,
AllocateAnyPages,
EfiBootServicesData,
- Pages,
+ RealPages,
&Memory,
0
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;
- UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);
+
+ AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;
+ UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);
if (UnalignedPages > 0) {
//
// Free first unaligned page(s).
//
Status = PciIo->FreeBuffer (PciIo, UnalignedPages, Memory);
- ASSERT_EFI_ERROR(Status);
+ ASSERT_EFI_ERROR (Status);
}
+
Memory = (VOID *)(UINTN)(AlignedMemory + EFI_PAGES_TO_SIZE (Pages));
UnalignedPages = RealPages - Pages - UnalignedPages;
if (UnalignedPages > 0) {
@@ -679,7 +671,7 @@ UsbHcAllocateAlignedPages (
// Free last unaligned page(s).
//
Status = PciIo->FreeBuffer (PciIo, UnalignedPages, Memory);
- ASSERT_EFI_ERROR(Status);
+ ASSERT_EFI_ERROR (Status);
}
} else {
//
@@ -693,28 +685,29 @@ UsbHcAllocateAlignedPages (
&Memory,
0
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- AlignedMemory = (UINTN) Memory;
+
+ AlignedMemory = (UINTN)Memory;
}
- Bytes = EFI_PAGES_TO_SIZE (Pages);
+ Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
- (VOID *) AlignedMemory,
+ (VOID *)AlignedMemory,
&Bytes,
DeviceAddress,
Mapping
);
- if (EFI_ERROR(Status) || (Bytes != EFI_PAGES_TO_SIZE (Pages))) {
- Status = PciIo->FreeBuffer (PciIo, Pages, (VOID *) AlignedMemory);
+ if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (Pages))) {
+ Status = PciIo->FreeBuffer (PciIo, Pages, (VOID *)AlignedMemory);
return EFI_OUT_OF_RESOURCES;
}
- *HostAddress = (VOID *) AlignedMemory;
+ *HostAddress = (VOID *)AlignedMemory;
return EFI_SUCCESS;
}
@@ -730,23 +723,23 @@ UsbHcAllocateAlignedPages (
**/
VOID
UsbHcFreeAlignedPages (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN VOID *HostAddress,
- IN UINTN Pages,
- VOID *Mapping
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN VOID *HostAddress,
+ IN UINTN Pages,
+ VOID *Mapping
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Pages != 0);
Status = PciIo->Unmap (PciIo, Mapping);
- ASSERT_EFI_ERROR(Status);
+ ASSERT_EFI_ERROR (Status);
Status = PciIo->FreeBuffer (
PciIo,
Pages,
HostAddress
);
- ASSERT_EFI_ERROR(Status);
+ ASSERT_EFI_ERROR (Status);
}
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h
index 319110da3..48ae86141 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h
@@ -10,20 +10,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_XHCI_MEM_H_
#define _EFI_XHCI_MEM_H_
-#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
+#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
- UINT8 *Bits; // Bit array to record which unit is allocated
- UINTN BitsLen;
- UINT8 *Buf;
- UINT8 *BufHost;
- UINTN BufLen; // Memory size in bytes
- VOID *Mapping;
- USBHC_MEM_BLOCK *Next;
+ UINT8 *Bits; // Bit array to record which unit is allocated
+ UINTN BitsLen;
+ UINT8 *Buf;
+ UINT8 *BufHost;
+ UINTN BufLen; // Memory size in bytes
+ VOID *Mapping;
+ USBHC_MEM_BLOCK *Next;
};
//
@@ -32,16 +32,16 @@ struct _USBHC_MEM_BLOCK {
// data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
- EFI_PCI_IO_PROTOCOL *PciIo;
- BOOLEAN Check4G;
- UINT32 Which4G;
- USBHC_MEM_BLOCK *Head;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ BOOLEAN Check4G;
+ UINT32 Which4G;
+ USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
//
// Memory allocation unit, must be 2^n, n>4
//
-#define USBHC_MEM_UNIT 64
+#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
@@ -60,8 +60,6 @@ typedef struct _USBHC_MEM_POOL {
} \
} while (0)
-
-
/**
Initialize the memory management pool for the host controller.
@@ -76,7 +74,6 @@ UsbHcInitMemPool (
IN EFI_PCI_IO_PROTOCOL *PciIo
);
-
/**
Release the memory management pool.
@@ -88,10 +85,9 @@ UsbHcInitMemPool (
**/
EFI_STATUS
UsbHcFreeMemPool (
- IN USBHC_MEM_POOL *Pool
+ IN USBHC_MEM_POOL *Pool
);
-
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -104,11 +100,10 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
);
-
/**
Free the allocated memory back to the memory pool.
@@ -119,9 +114,9 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
/**
@@ -136,9 +131,9 @@ UsbHcFreeMem (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
/**
@@ -153,9 +148,9 @@ UsbHcGetPciAddrForHostAddr (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
/**
@@ -198,10 +193,10 @@ UsbHcAllocateAlignedPages (
**/
VOID
UsbHcFreeAlignedPages (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN VOID *HostAddress,
- IN UINTN Pages,
- VOID *Mapping
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN VOID *HostAddress,
+ IN UINTN Pages,
+ VOID *Mapping
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
index a23c770e6..c05431ff3 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
@@ -1,7 +1,7 @@
/** @file
The XHCI controller driver.
-Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2011 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -13,46 +13,46 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// to the UEFI protocol's port state (change).
//
USB_PORT_STATE_MAP mUsbPortStateMap[] = {
- {XHC_PORTSC_CCS, USB_PORT_STAT_CONNECTION},
- {XHC_PORTSC_PED, USB_PORT_STAT_ENABLE},
- {XHC_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},
- {XHC_PORTSC_RESET, USB_PORT_STAT_RESET}
+ { XHC_PORTSC_CCS, USB_PORT_STAT_CONNECTION },
+ { XHC_PORTSC_PED, USB_PORT_STAT_ENABLE },
+ { XHC_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT },
+ { XHC_PORTSC_RESET, USB_PORT_STAT_RESET }
};
USB_PORT_STATE_MAP mUsbPortChangeMap[] = {
- {XHC_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},
- {XHC_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},
- {XHC_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},
- {XHC_PORTSC_PRC, USB_PORT_STAT_C_RESET}
+ { XHC_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION },
+ { XHC_PORTSC_PEC, USB_PORT_STAT_C_ENABLE },
+ { XHC_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT },
+ { XHC_PORTSC_PRC, USB_PORT_STAT_C_RESET }
};
-USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {
- {XHC_PORTSC_CSC, EfiUsbPortConnectChange},
- {XHC_PORTSC_PEC, EfiUsbPortEnableChange},
- {XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange},
- {XHC_PORTSC_PRC, EfiUsbPortResetChange}
+USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {
+ { XHC_PORTSC_CSC, EfiUsbPortConnectChange },
+ { XHC_PORTSC_PEC, EfiUsbPortEnableChange },
+ { XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange },
+ { XHC_PORTSC_PRC, EfiUsbPortResetChange }
};
USB_PORT_STATE_MAP mUsbHubPortStateMap[] = {
- {XHC_HUB_PORTSC_CCS, USB_PORT_STAT_CONNECTION},
- {XHC_HUB_PORTSC_PED, USB_PORT_STAT_ENABLE},
- {XHC_HUB_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},
- {XHC_HUB_PORTSC_RESET, USB_PORT_STAT_RESET}
+ { XHC_HUB_PORTSC_CCS, USB_PORT_STAT_CONNECTION },
+ { XHC_HUB_PORTSC_PED, USB_PORT_STAT_ENABLE },
+ { XHC_HUB_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT },
+ { XHC_HUB_PORTSC_RESET, USB_PORT_STAT_RESET }
};
USB_PORT_STATE_MAP mUsbHubPortChangeMap[] = {
- {XHC_HUB_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},
- {XHC_HUB_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},
- {XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},
- {XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET}
+ { XHC_HUB_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION },
+ { XHC_HUB_PORTSC_PEC, USB_PORT_STAT_C_ENABLE },
+ { XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT },
+ { XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET }
};
-USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {
- {XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange},
- {XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange},
- {XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange},
- {XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange},
- {XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange}
+USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {
+ { XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange },
+ { XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange },
+ { XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange },
+ { XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange },
+ { XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange }
};
EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding = {
@@ -67,7 +67,7 @@ EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding = {
//
// Template for Xhci's Usb2 Host Controller Protocol Instance.
//
-EFI_USB2_HC_PROTOCOL gXhciUsb2HcTemplate = {
+EFI_USB2_HC_PROTOCOL gXhciUsb2HcTemplate = {
XhcGetCapability,
XhcReset,
XhcGetState,
@@ -114,20 +114,19 @@ XhcGetCapability (
return EFI_INVALID_PARAMETER;
}
- OldTpl = gBS->RaiseTPL (XHC_TPL);
+ OldTpl = gBS->RaiseTPL (XHC_TPL);
Xhc = XHC_FROM_THIS (This);
*MaxSpeed = EFI_USB_SPEED_SUPER;
- *PortNumber = (UINT8) (Xhc->HcSParams1.Data.MaxPorts);
- *Is64BitCapable = (UINT8) Xhc->Support64BitDma;
- DEBUG ((EFI_D_INFO, "XhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));
+ *PortNumber = (UINT8)(Xhc->HcSParams1.Data.MaxPorts);
+ *Is64BitCapable = (UINT8)Xhc->Support64BitDma;
+ DEBUG ((DEBUG_INFO, "XhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));
gBS->RestoreTPL (OldTpl);
return EFI_SUCCESS;
}
-
/**
Provides software reset for the USB host controller.
@@ -168,61 +167,63 @@ XhcReset (
OldTpl = gBS->RaiseTPL (XHC_TPL);
switch (Attributes) {
- case EFI_USB_HC_RESET_GLOBAL:
- //
- // Flow through, same behavior as Host Controller Reset
- //
- case EFI_USB_HC_RESET_HOST_CONTROLLER:
- if ((Xhc->DebugCapSupOffset != 0xFFFFFFFF) && ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&
- ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0)) {
- Status = EFI_SUCCESS;
- goto ON_EXIT;
- }
+ case EFI_USB_HC_RESET_GLOBAL:
//
- // Host Controller must be Halt when Reset it
+ // Flow through, same behavior as Host Controller Reset
//
- if (!XhcIsHalt (Xhc)) {
- Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
-
- if (EFI_ERROR(Status)) {
- Status = EFI_DEVICE_ERROR;
+ case EFI_USB_HC_RESET_HOST_CONTROLLER:
+ if ((Xhc->DebugCapSupOffset != 0xFFFFFFFF) && ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&
+ ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0))
+ {
+ Status = EFI_SUCCESS;
goto ON_EXIT;
}
- }
- Status = XhcResetHC (Xhc, XHC_RESET_TIMEOUT);
- ASSERT (!(XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_CNR)));
+ //
+ // Host Controller must be Halt when Reset it
+ //
+ if (!XhcIsHalt (Xhc)) {
+ Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
- if (EFI_ERROR(Status)) {
- goto ON_EXIT;
- }
- //
- // Clean up the asynchronous transfers, currently only
- // interrupt supports asynchronous operation.
- //
- XhciDelAllAsyncIntTransfers (Xhc);
- XhcFreeSched (Xhc);
+ if (EFI_ERROR (Status)) {
+ Status = EFI_DEVICE_ERROR;
+ goto ON_EXIT;
+ }
+ }
- XhcInitSched (Xhc);
- break;
+ Status = XhcResetHC (Xhc, XHC_RESET_TIMEOUT);
+ ASSERT (!(XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_CNR)));
- case EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG:
- case EFI_USB_HC_RESET_HOST_WITH_DEBUG:
- Status = EFI_UNSUPPORTED;
- break;
+ if (EFI_ERROR (Status)) {
+ goto ON_EXIT;
+ }
- default:
- Status = EFI_INVALID_PARAMETER;
+ //
+ // Clean up the asynchronous transfers, currently only
+ // interrupt supports asynchronous operation.
+ //
+ XhciDelAllAsyncIntTransfers (Xhc);
+ XhcFreeSched (Xhc);
+
+ XhcInitSched (Xhc);
+ break;
+
+ case EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG:
+ case EFI_USB_HC_RESET_HOST_WITH_DEBUG:
+ Status = EFI_UNSUPPORTED;
+ break;
+
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
ON_EXIT:
- DEBUG ((EFI_D_INFO, "XhcReset: status %r\n", Status));
+ DEBUG ((DEBUG_INFO, "XhcReset: status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
}
-
/**
Retrieve the current state of the USB host controller.
@@ -252,7 +253,7 @@ XhcGetState (
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
if (XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
*State = EfiUsbHcStateHalt;
@@ -260,7 +261,7 @@ XhcGetState (
*State = EfiUsbHcStateOperational;
}
- DEBUG ((EFI_D_INFO, "XhcGetState: current state %d\n", *State));
+ DEBUG ((DEBUG_INFO, "XhcGetState: current state %d\n", *State));
gBS->RestoreTPL (OldTpl);
return EFI_SUCCESS;
@@ -285,14 +286,14 @@ XhcSetState (
IN EFI_USB_HC_STATE State
)
{
- USB_XHCI_INSTANCE *Xhc;
- EFI_STATUS Status;
- EFI_USB_HC_STATE CurState;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ EFI_STATUS Status;
+ EFI_USB_HC_STATE CurState;
+ EFI_TPL OldTpl;
Status = XhcGetState (This, &CurState);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
@@ -302,41 +303,41 @@ XhcSetState (
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
switch (State) {
- case EfiUsbHcStateHalt:
- Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
- break;
-
- case EfiUsbHcStateOperational:
- if (XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE)) {
- Status = EFI_DEVICE_ERROR;
+ case EfiUsbHcStateHalt:
+ Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
break;
- }
- //
- // Software must not write a one to this field unless the host controller
- // is in the Halted state. Doing so will yield undefined results.
- // refers to Spec[XHCI1.0-2.3.1]
- //
- if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
- Status = EFI_DEVICE_ERROR;
+ case EfiUsbHcStateOperational:
+ if (XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE)) {
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
+
+ //
+ // Software must not write a one to this field unless the host controller
+ // is in the Halted state. Doing so will yield undefined results.
+ // refers to Spec[XHCI1.0-2.3.1]
+ //
+ if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
+
+ Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
break;
- }
- Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
- break;
+ case EfiUsbHcStateSuspend:
+ Status = EFI_UNSUPPORTED;
+ break;
- case EfiUsbHcStateSuspend:
- Status = EFI_UNSUPPORTED;
- break;
-
- default:
- Status = EFI_INVALID_PARAMETER;
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
- DEBUG ((EFI_D_INFO, "XhcSetState: status %r\n", Status));
+ DEBUG ((DEBUG_INFO, "XhcSetState: status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
@@ -364,15 +365,15 @@ XhcGetRootHubPortStatus (
OUT EFI_USB_PORT_STATUS *PortStatus
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- UINTN Index;
- UINTN MapSize;
- EFI_STATUS Status;
- USB_DEV_ROUTE ParentRouteChart;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ UINTN Index;
+ UINTN MapSize;
+ EFI_STATUS Status;
+ USB_DEV_ROUTE ParentRouteChart;
+ EFI_TPL OldTpl;
if (PortStatus == NULL) {
return EFI_INVALID_PARAMETER;
@@ -380,8 +381,8 @@ XhcGetRootHubPortStatus (
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
- Status = EFI_SUCCESS;
+ Xhc = XHC_FROM_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = Xhc->HcSParams1.Data.MaxPorts;
@@ -390,7 +391,7 @@ XhcGetRootHubPortStatus (
goto ON_EXIT;
}
- Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
+ Offset = (UINT32)(XHC_PORTSC_OFFSET + (0x10 * PortNumber));
PortStatus->PortStatus = 0;
PortStatus->PortChangeStatus = 0;
@@ -398,24 +399,31 @@ XhcGetRootHubPortStatus (
//
// According to XHCI 1.1 spec November 2017,
- // bit 10~13 of the root port status register identifies the speed of the attached device.
+ // Section 7.2 xHCI Support Protocol Capability
//
- switch ((State & XHC_PORTSC_PS) >> 10) {
- case 2:
- PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
- break;
+ PortStatus->PortStatus = XhcCheckUsbPortSpeedUsedPsic (Xhc, ((State & XHC_PORTSC_PS) >> 10));
+ if (PortStatus->PortStatus == 0) {
+ //
+ // According to XHCI 1.1 spec November 2017,
+ // bit 10~13 of the root port status register identifies the speed of the attached device.
+ //
+ switch ((State & XHC_PORTSC_PS) >> 10) {
+ case 2:
+ PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
+ break;
- case 3:
- PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
- break;
+ case 3:
+ PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
+ break;
- case 4:
- case 5:
- PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;
- break;
+ case 4:
+ case 5:
+ PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;
+ break;
- default:
- break;
+ default:
+ break;
+ }
}
//
@@ -425,9 +433,10 @@ XhcGetRootHubPortStatus (
for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {
- PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
+ PortStatus->PortStatus = (UINT16)(PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
}
}
+
//
// Bit5~8 reflects its current link state.
//
@@ -439,7 +448,7 @@ XhcGetRootHubPortStatus (
for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {
- PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
+ PortStatus->PortChangeStatus = (UINT16)(PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
}
}
@@ -463,7 +472,6 @@ ON_EXIT:
return Status;
}
-
/**
Sets a feature for the specified root hub port.
@@ -484,12 +492,12 @@ XhcSetRootHubPortFeature (
IN EFI_USB_PORT_FEATURE PortFeature
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
OldTpl = gBS->RaiseTPL (XHC_TPL);
@@ -503,81 +511,80 @@ XhcSetRootHubPortFeature (
goto ON_EXIT;
}
- Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
+ Offset = (UINT32)(XHC_PORTSC_OFFSET + (0x10 * PortNumber));
State = XhcReadOpReg (Xhc, Offset);
//
// Mask off the port status change bits, these bits are
// write clean bit
//
- State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
+ State &= ~(BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
switch (PortFeature) {
- case EfiUsbPortEnable:
- //
- // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
- // A port may be disabled by software writing a '1' to this flag.
- //
- Status = EFI_SUCCESS;
- break;
+ case EfiUsbPortEnable:
+ //
+ // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
+ // A port may be disabled by software writing a '1' to this flag.
+ //
+ Status = EFI_SUCCESS;
+ break;
- case EfiUsbPortSuspend:
- State |= XHC_PORTSC_LWS;
- XhcWriteOpReg (Xhc, Offset, State);
- State &= ~XHC_PORTSC_PLS;
- State |= (3 << 5) ;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortSuspend:
+ State |= XHC_PORTSC_LWS;
+ XhcWriteOpReg (Xhc, Offset, State);
+ State &= ~XHC_PORTSC_PLS;
+ State |= (3 << 5);
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortReset:
- DEBUG ((EFI_D_INFO, "XhcUsbPortReset!\n"));
- //
- // Make sure Host Controller not halt before reset it
- //
- if (XhcIsHalt (Xhc)) {
- Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
+ case EfiUsbPortReset:
+ DEBUG ((DEBUG_INFO, "XhcUsbPortReset!\n"));
+ //
+ // Make sure Host Controller not halt before reset it
+ //
+ if (XhcIsHalt (Xhc)) {
+ Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_INFO, "XhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
- break;
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "XhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
+ break;
+ }
}
- }
- //
- // 4.3.1 Resetting a Root Hub Port
- // 1) Write the PORTSC register with the Port Reset (PR) bit set to '1'.
- //
- State |= XHC_PORTSC_RESET;
- XhcWriteOpReg (Xhc, Offset, State);
- XhcWaitOpRegBit(Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);
- break;
+ //
+ // 4.3.1 Resetting a Root Hub Port
+ // 1) Write the PORTSC register with the Port Reset (PR) bit set to '1'.
+ //
+ State |= XHC_PORTSC_RESET;
+ XhcWriteOpReg (Xhc, Offset, State);
+ XhcWaitOpRegBit (Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);
+ break;
- case EfiUsbPortPower:
- //
- // Not supported, ignore the operation
- //
- Status = EFI_SUCCESS;
- break;
+ case EfiUsbPortPower:
+ //
+ // Not supported, ignore the operation
+ //
+ Status = EFI_SUCCESS;
+ break;
- case EfiUsbPortOwner:
- //
- // XHCI root hub port don't has the owner bit, ignore the operation
- //
- Status = EFI_SUCCESS;
- break;
+ case EfiUsbPortOwner:
+ //
+ // XHCI root hub port don't has the owner bit, ignore the operation
+ //
+ Status = EFI_SUCCESS;
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
ON_EXIT:
- DEBUG ((EFI_D_INFO, "XhcSetRootHubPortFeature: status %r\n", Status));
+ DEBUG ((DEBUG_INFO, "XhcSetRootHubPortFeature: status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
}
-
/**
Clears a feature for the specified root hub port.
@@ -601,17 +608,17 @@ XhcClearRootHubPortFeature (
IN EFI_USB_PORT_FEATURE PortFeature
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
- Status = EFI_SUCCESS;
+ Xhc = XHC_FROM_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = (Xhc->HcSParams1.Data.MaxPorts);
@@ -627,86 +634,86 @@ XhcClearRootHubPortFeature (
// write clean bit
//
State = XhcReadOpReg (Xhc, Offset);
- State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
+ State &= ~(BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
switch (PortFeature) {
- case EfiUsbPortEnable:
- //
- // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
- // A port may be disabled by software writing a '1' to this flag.
- //
- State |= XHC_PORTSC_PED;
- State &= ~XHC_PORTSC_RESET;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortEnable:
+ //
+ // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
+ // A port may be disabled by software writing a '1' to this flag.
+ //
+ State |= XHC_PORTSC_PED;
+ State &= ~XHC_PORTSC_RESET;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortSuspend:
- State |= XHC_PORTSC_LWS;
- XhcWriteOpReg (Xhc, Offset, State);
- State &= ~XHC_PORTSC_PLS;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortSuspend:
+ State |= XHC_PORTSC_LWS;
+ XhcWriteOpReg (Xhc, Offset, State);
+ State &= ~XHC_PORTSC_PLS;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortReset:
- //
- // PORTSC_RESET BIT(4) bit is RW1S attribute, which means Write-1-to-set status:
- // Register bits indicate status when read, a clear bit may be set by
- // writing a '1'. Writing a '0' to RW1S bits has no effect.
- //
- break;
+ case EfiUsbPortReset:
+ //
+ // PORTSC_RESET BIT(4) bit is RW1S attribute, which means Write-1-to-set status:
+ // Register bits indicate status when read, a clear bit may be set by
+ // writing a '1'. Writing a '0' to RW1S bits has no effect.
+ //
+ break;
- case EfiUsbPortOwner:
- //
- // XHCI root hub port don't has the owner bit, ignore the operation
- //
- break;
+ case EfiUsbPortOwner:
+ //
+ // XHCI root hub port don't has the owner bit, ignore the operation
+ //
+ break;
- case EfiUsbPortConnectChange:
- //
- // Clear connect status change
- //
- State |= XHC_PORTSC_CSC;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortConnectChange:
+ //
+ // Clear connect status change
+ //
+ State |= XHC_PORTSC_CSC;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortEnableChange:
- //
- // Clear enable status change
- //
- State |= XHC_PORTSC_PEC;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortEnableChange:
+ //
+ // Clear enable status change
+ //
+ State |= XHC_PORTSC_PEC;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortOverCurrentChange:
- //
- // Clear PortOverCurrent change
- //
- State |= XHC_PORTSC_OCC;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortOverCurrentChange:
+ //
+ // Clear PortOverCurrent change
+ //
+ State |= XHC_PORTSC_OCC;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortResetChange:
- //
- // Clear Port Reset change
- //
- State |= XHC_PORTSC_PRC;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortResetChange:
+ //
+ // Clear Port Reset change
+ //
+ State |= XHC_PORTSC_PRC;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortPower:
- case EfiUsbPortSuspendChange:
- //
- // Not supported or not related operation
- //
- break;
+ case EfiUsbPortPower:
+ case EfiUsbPortSuspendChange:
+ //
+ // Not supported or not related operation
+ //
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
- break;
+ default:
+ Status = EFI_INVALID_PARAMETER;
+ break;
}
ON_EXIT:
- DEBUG ((EFI_D_INFO, "XhcClearRootHubPortFeature: status %r\n", Status));
+ DEBUG ((DEBUG_INFO, "XhcClearRootHubPortFeature: status %r\n", Status));
gBS->RestoreTPL (OldTpl);
return Status;
@@ -737,22 +744,22 @@ ON_EXIT:
**/
EFI_STATUS
XhcTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 DeviceAddress,
- IN UINT8 EndPointAddress,
- IN UINT8 DeviceSpeed,
- IN UINTN MaximumPacketLength,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN OUT VOID *Data,
- IN OUT UINTN *DataLength,
- IN UINTN Timeout,
- OUT UINT32 *TransferResult
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 DeviceAddress,
+ IN UINT8 EndPointAddress,
+ IN UINT8 DeviceSpeed,
+ IN UINTN MaximumPacketLength,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN OUT VOID *Data,
+ IN OUT UINTN *DataLength,
+ IN UINTN Timeout,
+ OUT UINT32 *TransferResult
)
{
- EFI_STATUS Status;
- EFI_STATUS RecoveryStatus;
- URB *Urb;
+ EFI_STATUS Status;
+ EFI_STATUS RecoveryStatus;
+ URB *Urb;
ASSERT ((Type == XHC_CTRL_TRANSFER) || (Type == XHC_BULK_TRANSFER) || (Type == XHC_INT_TRANSFER_SYNC));
Urb = XhcCreateUrb (
@@ -780,7 +787,7 @@ XhcTransfer (
//
// The transfer timed out. Abort the transfer by dequeueing of the TD.
//
- RecoveryStatus = XhcDequeueTrbFromEndpoint(Xhc, Urb);
+ RecoveryStatus = XhcDequeueTrbFromEndpoint (Xhc, Urb);
if (RecoveryStatus == EFI_ALREADY_STARTED) {
//
// The URB is finished just before stopping endpoint.
@@ -789,8 +796,8 @@ XhcTransfer (
ASSERT (Urb->Result == EFI_USB_NOERROR);
Status = EFI_SUCCESS;
DEBUG ((DEBUG_ERROR, "XhcTransfer[Type=%d]: pending URB is finished, Length = %d.\n", Type, Urb->Completed));
- } else if (EFI_ERROR(RecoveryStatus)) {
- DEBUG((DEBUG_ERROR, "XhcTransfer[Type=%d]: XhcDequeueTrbFromEndpoint failed!\n", Type));
+ } else if (EFI_ERROR (RecoveryStatus)) {
+ DEBUG ((DEBUG_ERROR, "XhcTransfer[Type=%d]: XhcDequeueTrbFromEndpoint failed!\n", Type));
}
}
@@ -799,8 +806,8 @@ XhcTransfer (
if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE)) {
ASSERT (Status == EFI_DEVICE_ERROR);
- RecoveryStatus = XhcRecoverHaltedEndpoint(Xhc, Urb);
- if (EFI_ERROR(RecoveryStatus)) {
+ RecoveryStatus = XhcRecoverHaltedEndpoint (Xhc, Urb);
+ if (EFI_ERROR (RecoveryStatus)) {
DEBUG ((DEBUG_ERROR, "XhcTransfer[Type=%d]: XhcRecoverHaltedEndpoint failed!\n", Type));
}
}
@@ -876,24 +883,28 @@ XhcControlTransfer (
if ((TransferDirection != EfiUsbDataIn) &&
(TransferDirection != EfiUsbDataOut) &&
- (TransferDirection != EfiUsbNoData)) {
+ (TransferDirection != EfiUsbNoData))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection == EfiUsbNoData) &&
- ((Data != NULL) || (*DataLength != 0))) {
+ ((Data != NULL) || (*DataLength != 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection != EfiUsbNoData) &&
- ((Data == NULL) || (*DataLength == 0))) {
+ ((Data == NULL) || (*DataLength == 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&
(MaximumPacketLength != 32) && (MaximumPacketLength != 64) &&
(MaximumPacketLength != 512)
- ) {
+ )
+ {
return EFI_INVALID_PARAMETER;
}
@@ -907,14 +918,14 @@ XhcControlTransfer (
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
Status = EFI_DEVICE_ERROR;
*TransferResult = EFI_USB_ERR_SYSTEM;
Len = 0;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
- DEBUG ((EFI_D_ERROR, "XhcControlTransfer: HC halted at entrance\n"));
+ DEBUG ((DEBUG_ERROR, "XhcControlTransfer: HC halted at entrance\n"));
goto ON_EXIT;
}
@@ -931,7 +942,8 @@ XhcControlTransfer (
// According to XHCI 1.0 spec, the Set_Address request is replaced by XHCI's Address_Device cmd.
//
if ((Request->Request == USB_REQ_SET_ADDRESS) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)))
+ {
//
// Reset the BusDevAddr field of all disabled entries in UsbDevContext array firstly.
// This way is used to clean the history to avoid using wrong device address by XhcAsyncInterruptTransfer().
@@ -939,7 +951,8 @@ XhcControlTransfer (
for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId == 0) &&
- (Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8)Request->Value)) {
+ (Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8)Request->Value))
+ {
Xhc->UsbDevContext[Index + 1].BusDevAddr = 0;
}
}
@@ -948,6 +961,7 @@ XhcControlTransfer (
Status = EFI_DEVICE_ERROR;
goto ON_EXIT;
}
+
//
// The actual device address has been assigned by XHCI during initializing the device slot.
// So we just need establish the mapping relationship between the device address requested from UsbBus
@@ -955,7 +969,7 @@ XhcControlTransfer (
// can find out the actual device address by it.
//
Xhc->UsbDevContext[SlotId].BusDevAddr = (UINT8)Request->Value;
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
goto ON_EXIT;
}
@@ -966,22 +980,22 @@ XhcControlTransfer (
// endpoint is bidirectional. XhcCreateUrb expects this
// combination of Ep addr and its direction.
//
- Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
- Status = XhcTransfer (
- Xhc,
- DeviceAddress,
- Endpoint,
- DeviceSpeed,
- MaximumPacketLength,
- XHC_CTRL_TRANSFER,
- Request,
- Data,
- DataLength,
- Timeout,
- TransferResult
- );
+ Endpoint = (UINT8)(0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
+ Status = XhcTransfer (
+ Xhc,
+ DeviceAddress,
+ Endpoint,
+ DeviceSpeed,
+ MaximumPacketLength,
+ XHC_CTRL_TRANSFER,
+ Request,
+ Data,
+ DataLength,
+ Timeout,
+ TransferResult
+ );
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto ON_EXIT;
}
@@ -992,28 +1006,30 @@ XhcControlTransfer (
//
if ((Request->Request == USB_REQ_GET_DESCRIPTOR) &&
((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)) ||
- ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE))))) {
+ ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE)))))
+ {
DescriptorType = (UINT8)(Request->Value >> 8);
if ((DescriptorType == USB_DESC_TYPE_DEVICE) && ((*DataLength == sizeof (EFI_USB_DEVICE_DESCRIPTOR)) || ((DeviceSpeed == EFI_USB_SPEED_FULL) && (*DataLength == 8)))) {
- ASSERT (Data != NULL);
+ ASSERT (Data != NULL);
+ //
+ // Store a copy of device scriptor as hub device need this info to configure endpoint.
+ //
+ CopyMem (&Xhc->UsbDevContext[SlotId].DevDesc, Data, *DataLength);
+ if (Xhc->UsbDevContext[SlotId].DevDesc.BcdUSB >= 0x0300) {
//
- // Store a copy of device scriptor as hub device need this info to configure endpoint.
+ // If it's a usb3.0 device, then its max packet size is a 2^n.
//
- CopyMem(&Xhc->UsbDevContext[SlotId].DevDesc, Data, *DataLength);
- if (Xhc->UsbDevContext[SlotId].DevDesc.BcdUSB >= 0x0300) {
- //
- // If it's a usb3.0 device, then its max packet size is a 2^n.
- //
- MaxPacket0 = 1 << Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
- } else {
- MaxPacket0 = Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
- }
- Xhc->UsbDevContext[SlotId].ConfDesc = AllocateZeroPool(Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIPTOR *));
- if (Xhc->HcCParams.Data.Csz == 0) {
- Status = XhcEvaluateContext (Xhc, SlotId, MaxPacket0);
- } else {
- Status = XhcEvaluateContext64 (Xhc, SlotId, MaxPacket0);
- }
+ MaxPacket0 = 1 << Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
+ } else {
+ MaxPacket0 = Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
+ }
+
+ Xhc->UsbDevContext[SlotId].ConfDesc = AllocateZeroPool (Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIPTOR *));
+ if (Xhc->HcCParams.Data.Csz == 0) {
+ Status = XhcEvaluateContext (Xhc, SlotId, MaxPacket0);
+ } else {
+ Status = XhcEvaluateContext64 (Xhc, SlotId, MaxPacket0);
+ }
} else if (DescriptorType == USB_DESC_TYPE_CONFIG) {
ASSERT (Data != NULL);
if (*DataLength == ((UINT16 *)Data)[1]) {
@@ -1022,15 +1038,16 @@ XhcControlTransfer (
//
Index = (UINT8)Request->Value;
ASSERT (Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations);
- Xhc->UsbDevContext[SlotId].ConfDesc[Index] = AllocateZeroPool(*DataLength);
- CopyMem(Xhc->UsbDevContext[SlotId].ConfDesc[Index], Data, *DataLength);
+ Xhc->UsbDevContext[SlotId].ConfDesc[Index] = AllocateZeroPool (*DataLength);
+ CopyMem (Xhc->UsbDevContext[SlotId].ConfDesc[Index], Data, *DataLength);
//
// Default to use AlternateSetting 0 for all interfaces.
//
- Xhc->UsbDevContext[SlotId].ActiveAlternateSetting = AllocateZeroPool(Xhc->UsbDevContext[SlotId].ConfDesc[Index]->NumInterfaces * sizeof (UINT8));
+ Xhc->UsbDevContext[SlotId].ActiveAlternateSetting = AllocateZeroPool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]->NumInterfaces * sizeof (UINT8));
}
} else if (((DescriptorType == USB_DESC_TYPE_HUB) ||
- (DescriptorType == USB_DESC_TYPE_HUB_SUPER_SPEED)) && (*DataLength > 2)) {
+ (DescriptorType == USB_DESC_TYPE_HUB_SUPER_SPEED)) && (*DataLength > 2))
+ {
ASSERT (Data != NULL);
HubDesc = (EFI_USB_HUB_DESCRIPTOR *)Data;
ASSERT (HubDesc->NumPorts <= 15);
@@ -1043,7 +1060,7 @@ XhcControlTransfer (
// Don't support multi-TT feature for super speed hub now.
//
MTT = 0;
- DEBUG ((EFI_D_ERROR, "XHCI: Don't support multi-TT feature for Hub now. (force to disable MTT)\n"));
+ DEBUG ((DEBUG_ERROR, "XHCI: Don't support multi-TT feature for Hub now. (force to disable MTT)\n"));
} else {
MTT = 0;
}
@@ -1055,7 +1072,8 @@ XhcControlTransfer (
}
}
} else if ((Request->Request == USB_REQ_SET_CONFIG) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)))
+ {
//
// Hook Set_Config request from UsbBus as we need configure device endpoint.
//
@@ -1066,17 +1084,19 @@ XhcControlTransfer (
} else {
Status = XhcSetConfigCmd64 (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
}
+
break;
}
}
} else if ((Request->Request == USB_REQ_SET_INTERFACE) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_INTERFACE))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_INTERFACE)))
+ {
//
// Hook Set_Interface request from UsbBus as we need configure interface setting.
// Request->Value indicates AlterlateSetting to set
// Request->Index indicates Interface to set
//
- if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] != (UINT8) Request->Value) {
+ if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8)Request->Index] != (UINT8)Request->Value) {
if (Xhc->HcCParams.Data.Csz == 0) {
Status = XhcSetInterface (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Xhc->UsbDevContext[SlotId].ActiveConfiguration - 1], Request);
} else {
@@ -1084,7 +1104,8 @@ XhcControlTransfer (
}
}
} else if ((Request->Request == USB_REQ_GET_STATUS) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER)))
+ {
ASSERT (Data != NULL);
//
// Hook Get_Status request from UsbBus to keep track of the port status change.
@@ -1117,14 +1138,14 @@ XhcControlTransfer (
MapSize = sizeof (mUsbHubPortStateMap) / sizeof (USB_PORT_STATE_MAP);
for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbHubPortStateMap[Index].HwState)) {
- PortStatus.PortStatus = (UINT16) (PortStatus.PortStatus | mUsbHubPortStateMap[Index].UefiState);
+ PortStatus.PortStatus = (UINT16)(PortStatus.PortStatus | mUsbHubPortStateMap[Index].UefiState);
}
}
MapSize = sizeof (mUsbHubPortChangeMap) / sizeof (USB_PORT_STATE_MAP);
for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbHubPortChangeMap[Index].HwState)) {
- PortStatus.PortChangeStatus = (UINT16) (PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);
+ PortStatus.PortChangeStatus = (UINT16)(PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);
}
}
@@ -1133,11 +1154,11 @@ XhcControlTransfer (
for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbHubClearPortChangeMap[Index].HwState)) {
ZeroMem (&ClearPortRequest, sizeof (EFI_USB_DEVICE_REQUEST));
- ClearPortRequest.RequestType = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);
- ClearPortRequest.Request = (UINT8) USB_REQ_CLEAR_FEATURE;
- ClearPortRequest.Value = mUsbHubClearPortChangeMap[Index].Selector;
- ClearPortRequest.Index = Request->Index;
- ClearPortRequest.Length = 0;
+ ClearPortRequest.RequestType = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);
+ ClearPortRequest.Request = (UINT8)USB_REQ_CLEAR_FEATURE;
+ ClearPortRequest.Value = mUsbHubClearPortChangeMap[Index].Selector;
+ ClearPortRequest.Index = Request->Index;
+ ClearPortRequest.Length = 0;
XhcControlTransfer (
This,
@@ -1157,12 +1178,12 @@ XhcControlTransfer (
XhcPollPortStatusChange (Xhc, Xhc->UsbDevContext[SlotId].RouteString, (UINT8)Request->Index, &PortStatus);
- *(UINT32 *)Data = *(UINT32*)&PortStatus;
+ *(UINT32 *)Data = *(UINT32 *)&PortStatus;
}
ON_EXIT:
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
gBS->RestoreTPL (OldTpl);
@@ -1170,7 +1191,6 @@ ON_EXIT:
return Status;
}
-
/**
Submits bulk transfer to a bulk endpoint of a USB device.
@@ -1218,16 +1238,17 @@ XhcBulkTransfer (
OUT UINT32 *TransferResult
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT8 SlotId;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT8 SlotId;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
//
// Validate the parameters
//
if ((DataLength == NULL) || (*DataLength == 0) ||
- (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {
+ (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -1238,19 +1259,20 @@ XhcBulkTransfer (
if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512)) ||
- ((EFI_USB_SPEED_SUPER == DeviceSpeed) && (MaximumPacketLength > 1024))) {
+ ((EFI_USB_SPEED_SUPER == DeviceSpeed) && (MaximumPacketLength > 1024)))
+ {
return EFI_INVALID_PARAMETER;
}
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
*TransferResult = EFI_USB_ERR_SYSTEM;
Status = EFI_DEVICE_ERROR;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
- DEBUG ((EFI_D_ERROR, "XhcBulkTransfer: HC is halted\n"));
+ DEBUG ((DEBUG_ERROR, "XhcBulkTransfer: HC is halted\n"));
goto ON_EXIT;
}
@@ -1281,9 +1303,10 @@ XhcBulkTransfer (
);
ON_EXIT:
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
+
gBS->RestoreTPL (OldTpl);
return Status;
@@ -1335,12 +1358,12 @@ XhcAsyncInterruptTransfer (
IN VOID *Context OPTIONAL
)
{
- USB_XHCI_INSTANCE *Xhc;
- URB *Urb;
- EFI_STATUS Status;
- UINT8 SlotId;
- UINT8 Index;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ URB *Urb;
+ EFI_STATUS Status;
+ UINT8 SlotId;
+ UINT8 Index;
+ EFI_TPL OldTpl;
//
// Validate parameters
@@ -1365,7 +1388,7 @@ XhcAsyncInterruptTransfer (
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
//
// Delete Async interrupt transfer request.
@@ -1386,14 +1409,14 @@ XhcAsyncInterruptTransfer (
}
Status = XhciDelAsyncIntTransfer (Xhc, DeviceAddress, EndPointAddress);
- DEBUG ((EFI_D_INFO, "XhcAsyncInterruptTransfer: remove old transfer for addr %d, Status = %r\n", DeviceAddress, Status));
+ DEBUG ((DEBUG_INFO, "XhcAsyncInterruptTransfer: remove old transfer for addr %d, Status = %r\n", DeviceAddress, Status));
goto ON_EXIT;
}
Status = EFI_SUCCESS;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
- DEBUG ((EFI_D_ERROR, "XhcAsyncInterruptTransfer: HC is halt\n"));
+ DEBUG ((DEBUG_ERROR, "XhcAsyncInterruptTransfer: HC is halt\n"));
Status = EFI_DEVICE_ERROR;
goto ON_EXIT;
}
@@ -1433,7 +1456,6 @@ ON_EXIT:
return Status;
}
-
/**
Submits synchronous interrupt transfer to an interrupt endpoint
of a USB device.
@@ -1477,16 +1499,17 @@ XhcSyncInterruptTransfer (
OUT UINT32 *TransferResult
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT8 SlotId;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT8 SlotId;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
//
// Validates parameters
//
if ((DataLength == NULL) || (*DataLength == 0) ||
- (Data == NULL) || (TransferResult == NULL)) {
+ (Data == NULL) || (TransferResult == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -1496,19 +1519,20 @@ XhcSyncInterruptTransfer (
if (((DeviceSpeed == EFI_USB_SPEED_LOW) && (MaximumPacketLength != 8)) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
- ((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 3072))) {
+ ((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 3072)))
+ {
return EFI_INVALID_PARAMETER;
}
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
*TransferResult = EFI_USB_ERR_SYSTEM;
Status = EFI_DEVICE_ERROR;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
- DEBUG ((EFI_D_ERROR, "EhcSyncInterruptTransfer: HC is halt\n"));
+ DEBUG ((DEBUG_ERROR, "EhcSyncInterruptTransfer: HC is halt\n"));
goto ON_EXIT;
}
@@ -1535,15 +1559,15 @@ XhcSyncInterruptTransfer (
);
ON_EXIT:
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcSyncInterruptTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcSyncInterruptTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
+
gBS->RestoreTPL (OldTpl);
return Status;
}
-
/**
Submits isochronous transfer to a target USB device.
@@ -1583,7 +1607,6 @@ XhcIsochronousTransfer (
return EFI_UNSUPPORTED;
}
-
/**
Submits Async isochronous transfer to a target USB device.
@@ -1639,8 +1662,8 @@ XhcAsyncIsochronousTransfer (
EFI_STATUS
EFIAPI
XhcDriverEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
return EfiLibInstallDriverBindingComponentName2 (
@@ -1653,7 +1676,6 @@ XhcDriverEntryPoint (
);
}
-
/**
Test to see if this driver supports ControllerHandle. Any
ControllerHandle that has Usb2HcProtocol installed will
@@ -1670,14 +1692,14 @@ XhcDriverEntryPoint (
EFI_STATUS
EFIAPI
XhcDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- USB_CLASSC UsbClassCReg;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ USB_CLASSC UsbClassCReg;
//
// Test whether there is PCI IO Protocol attached on the controller handle.
@@ -1685,13 +1707,13 @@ XhcDriverBindingSupported (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
@@ -1703,7 +1725,7 @@ XhcDriverBindingSupported (
&UsbClassCReg
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
Status = EFI_UNSUPPORTED;
goto ON_EXIT;
}
@@ -1713,7 +1735,8 @@ XhcDriverBindingSupported (
//
if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) ||
(UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB) ||
- (UsbClassCReg.ProgInterface != PCI_IF_XHCI)) {
+ (UsbClassCReg.ProgInterface != PCI_IF_XHCI))
+ {
Status = EFI_UNSUPPORTED;
}
@@ -1739,20 +1762,20 @@ ON_EXIT:
otherwise NULL.
**/
-USB_XHCI_INSTANCE*
+USB_XHCI_INSTANCE *
XhcCreateUsbHc (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
IN UINT64 OriginalPciAttributes
)
{
- USB_XHCI_INSTANCE *Xhc;
- EFI_STATUS Status;
- UINT32 PageSize;
- UINT16 ExtCapReg;
- UINT8 ReleaseNumber;
+ USB_XHCI_INSTANCE *Xhc;
+ EFI_STATUS Status;
+ UINT32 PageSize;
+ UINT16 ExtCapReg;
+ UINT8 ReleaseNumber;
- Xhc = AllocateZeroPool(sizeof (USB_XHCI_INSTANCE));
+ Xhc = AllocateZeroPool (sizeof (USB_XHCI_INSTANCE));
if (Xhc == NULL) {
return NULL;
@@ -1765,7 +1788,7 @@ XhcCreateUsbHc (
Xhc->PciIo = PciIo;
Xhc->DevicePath = DevicePath;
Xhc->OriginalPciAttributes = OriginalPciAttributes;
- CopyMem(&Xhc->Usb2Hc, &gXhciUsb2HcTemplate, sizeof (EFI_USB2_HC_PROTOCOL));
+ CopyMem (&Xhc->Usb2Hc, &gXhciUsb2HcTemplate, sizeof (EFI_USB2_HC_PROTOCOL));
Status = PciIo->Pci.Read (
PciIo,
@@ -1775,7 +1798,7 @@ XhcCreateUsbHc (
&ReleaseNumber
);
- if (!EFI_ERROR(Status)) {
+ if (!EFI_ERROR (Status)) {
Xhc->Usb2Hc.MajorRevision = (ReleaseNumber & 0xF0) >> 4;
Xhc->Usb2Hc.MinorRevision = (ReleaseNumber & 0x0F);
}
@@ -1797,22 +1820,32 @@ XhcCreateUsbHc (
// This xHC supports a page size of 2^(n+12) if bit n is Set. For example,
// if bit 0 is Set, the xHC supports 4k byte page sizes.
//
- PageSize = XhcReadOpReg(Xhc, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;
- Xhc->PageSize = 1 << (HighBitSet32(PageSize) + 12);
+ PageSize = XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET);
+ if ((PageSize & (~XHC_PAGESIZE_MASK)) != 0) {
+ DEBUG ((DEBUG_ERROR, "XhcCreateUsb3Hc: Reserved bits are not 0 for PageSize\n"));
+ goto ON_ERROR;
+ }
- ExtCapReg = (UINT16) (Xhc->HcCParams.Data.ExtCapReg);
- Xhc->ExtCapRegBase = ExtCapReg << 2;
- Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
+ PageSize &= XHC_PAGESIZE_MASK;
+ Xhc->PageSize = 1 << (HighBitSet32 (PageSize) + 12);
+
+ ExtCapReg = (UINT16)(Xhc->HcCParams.Data.ExtCapReg);
+ Xhc->ExtCapRegBase = ExtCapReg << 2;
+ Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
Xhc->DebugCapSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG);
+ Xhc->Usb2SupOffset = XhcGetSupportedProtocolCapabilityAddr (Xhc, XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB2);
+ Xhc->Usb3SupOffset = XhcGetSupportedProtocolCapabilityAddr (Xhc, XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB3);
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams2 0x%x\n", Xhc->HcSParams2));
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcCParams 0x%x\n", Xhc->HcCParams));
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset));
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcSParams2 0x%x\n", Xhc->HcSParams2));
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcCParams 0x%x\n", Xhc->HcCParams));
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset));
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Usb2SupOffset 0x%x\n", Xhc->Usb2SupOffset));
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Usb3SupOffset 0x%x\n", Xhc->Usb3SupOffset));
//
// Create AsyncRequest Polling Timer
@@ -1825,14 +1858,14 @@ XhcCreateUsbHc (
&Xhc->PollTimer
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto ON_ERROR;
}
return Xhc;
ON_ERROR:
- FreePool(Xhc);
+ FreePool (Xhc);
return NULL;
}
@@ -1854,7 +1887,7 @@ XhcExitBootService (
USB_XHCI_INSTANCE *Xhc;
EFI_PCI_IO_PROTOCOL *PciIo;
- Xhc = (USB_XHCI_INSTANCE*) Context;
+ Xhc = (USB_XHCI_INSTANCE *)Context;
PciIo = Xhc->PciIo;
//
@@ -1874,11 +1907,11 @@ XhcExitBootService (
// Restore original PCI attributes
//
PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationSet,
- Xhc->OriginalPciAttributes,
- NULL
- );
+ PciIo,
+ EfiPciIoAttributeOperationSet,
+ Xhc->OriginalPciAttributes,
+ NULL
+ );
}
/**
@@ -1897,17 +1930,17 @@ XhcExitBootService (
EFI_STATUS
EFIAPI
XhcDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Supports;
- UINT64 OriginalPciAttributes;
- BOOLEAN PciAttributesSaved;
- USB_XHCI_INSTANCE *Xhc;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Supports;
+ UINT64 OriginalPciAttributes;
+ BOOLEAN PciAttributesSaved;
+ USB_XHCI_INSTANCE *Xhc;
EFI_DEVICE_PATH_PROTOCOL *HcDevicePath;
//
@@ -1916,13 +1949,13 @@ XhcDriverBindingStart (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -1930,14 +1963,14 @@ XhcDriverBindingStart (
// Open Device Path Protocol for on USB host controller
//
HcDevicePath = NULL;
- Status = gBS->OpenProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- (VOID **) &HcDevicePath,
- This->DriverBindingHandle,
- Controller,
- EFI_OPEN_PROTOCOL_GET_PROTOCOL
- );
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ (VOID **)&HcDevicePath,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL
+ );
PciAttributesSaved = FALSE;
//
@@ -1950,9 +1983,10 @@ XhcDriverBindingStart (
&OriginalPciAttributes
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto CLOSE_PCIIO;
}
+
PciAttributesSaved = TRUE;
Status = PciIo->Attributes (
@@ -1961,18 +1995,18 @@ XhcDriverBindingStart (
0,
&Supports
);
- if (!EFI_ERROR(Status)) {
+ if (!EFI_ERROR (Status)) {
Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
- Status = PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationEnable,
- Supports,
- NULL
- );
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationEnable,
+ Supports,
+ NULL
+ );
}
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to enable controller\n"));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to enable controller\n"));
goto CLOSE_PCIIO;
}
@@ -1982,7 +2016,7 @@ XhcDriverBindingStart (
Xhc = XhcCreateUsbHc (PciIo, HcDevicePath, OriginalPciAttributes);
if (Xhc == NULL) {
- DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to create USB2_HC\n"));
+ DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to create USB2_HC\n"));
return EFI_OUT_OF_RESOURCES;
}
@@ -1997,12 +2031,16 @@ XhcDriverBindingStart (
EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,
NULL
);
- if (!EFI_ERROR(Status)) {
+ if (!EFI_ERROR (Status)) {
Xhc->Support64BitDma = TRUE;
} else {
- DEBUG ((EFI_D_WARN,
+ DEBUG ((
+ DEBUG_WARN,
"%a: failed to enable 64-bit DMA on 64-bit capable controller @ %p (%r)\n",
- __FUNCTION__, Controller, Status));
+ __FUNCTION__,
+ Controller,
+ Status
+ ));
}
}
@@ -2025,14 +2063,14 @@ XhcDriverBindingStart (
//
// Start the Host Controller
//
- XhcRunHC(Xhc, XHC_GENERIC_TIMEOUT);
+ XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
//
// Start the asynchronous interrupt monitor
//
Status = gBS->SetTimer (Xhc->PollTimer, TimerPeriodic, XHC_ASYNC_TIMER_INTERVAL);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to start async interrupt monitor\n"));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to start async interrupt monitor\n"));
XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
goto FREE_POOL;
}
@@ -2048,7 +2086,7 @@ XhcDriverBindingStart (
&gEfiEventExitBootServicesGuid,
&Xhc->ExitBootServiceEvent
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto FREE_POOL;
}
@@ -2077,18 +2115,18 @@ XhcDriverBindingStart (
EFI_NATIVE_INTERFACE,
&Xhc->Usb2Hc
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to install USB2_HC Protocol\n"));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to install USB2_HC Protocol\n"));
goto FREE_POOL;
}
- DEBUG ((EFI_D_INFO, "XhcDriverBindingStart: XHCI started for controller @ %x\n", Controller));
+ DEBUG ((DEBUG_INFO, "XhcDriverBindingStart: XHCI started for controller @ %x\n", Controller));
return EFI_SUCCESS;
FREE_POOL:
gBS->CloseEvent (Xhc->PollTimer);
XhcFreeSched (Xhc);
- FreePool(Xhc);
+ FreePool (Xhc);
CLOSE_PCIIO:
if (PciAttributesSaved) {
@@ -2096,11 +2134,11 @@ CLOSE_PCIIO:
// Restore original PCI attributes
//
PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationSet,
- OriginalPciAttributes,
- NULL
- );
+ PciIo,
+ EfiPciIoAttributeOperationSet,
+ OriginalPciAttributes,
+ NULL
+ );
}
gBS->CloseProtocol (
@@ -2113,7 +2151,6 @@ CLOSE_PCIIO:
return Status;
}
-
/**
Stop this driver on ControllerHandle. Support stopping any child handles
created by this driver.
@@ -2130,10 +2167,10 @@ CLOSE_PCIIO:
EFI_STATUS
EFIAPI
XhcDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
@@ -2150,13 +2187,13 @@ XhcDriverBindingStop (
Status = gBS->OpenProtocol (
Controller,
&gEfiUsb2HcProtocolGuid,
- (VOID **) &Usb2Hc,
+ (VOID **)&Usb2Hc,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -2166,7 +2203,7 @@ XhcDriverBindingStop (
Usb2Hc
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -2185,9 +2222,11 @@ XhcDriverBindingStop (
//
for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled ||
- (Xhc->UsbDevContext[Index + 1].SlotId == 0)) {
+ (Xhc->UsbDevContext[Index + 1].SlotId == 0))
+ {
continue;
}
+
if (Xhc->HcCParams.Data.Csz == 0) {
XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
} else {
@@ -2229,8 +2268,7 @@ XhcDriverBindingStop (
Controller
);
- FreePool(Xhc);
+ FreePool (Xhc);
return EFI_SUCCESS;
}
-
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
index 72b4e084f..ca223bd20 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
@@ -3,6 +3,7 @@
Provides some data structure definitions used by the XHCI host controller driver.
Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) Microsoft Corporation.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -28,8 +29,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
-typedef struct _USB_XHCI_INSTANCE USB_XHCI_INSTANCE;
-typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
+typedef struct _USB_XHCI_INSTANCE USB_XHCI_INSTANCE;
+typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
#include "XhciReg.h"
#include "XhciSched.h"
@@ -39,70 +40,62 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
//
// The unit is microsecond, setting it as 1us.
//
-#define XHC_1_MICROSECOND (1)
+#define XHC_1_MICROSECOND (1)
//
// The unit is microsecond, setting it as 1ms.
//
-#define XHC_1_MILLISECOND (1000)
+#define XHC_1_MILLISECOND (1000)
//
// XHC generic timeout experience values.
// The unit is millisecond, setting it as 10s.
//
-#define XHC_GENERIC_TIMEOUT (10 * 1000)
+#define XHC_GENERIC_TIMEOUT (10 * 1000)
//
// XHC reset timeout experience values.
// The unit is millisecond, setting it as 1s.
//
-#define XHC_RESET_TIMEOUT (1000)
+#define XHC_RESET_TIMEOUT (1000)
//
// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.
// The unit is microsecond, setting it as 10ms.
//
-#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
+#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
//
// XHC async transfer timer interval, set by experience.
// The unit is 100us, takes 1ms as interval.
//
-#define XHC_ASYNC_TIMER_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
+#define XHC_ASYNC_TIMER_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
//
// XHC raises TPL to TPL_NOTIFY to serialize all its operations
// to protect shared data structures.
//
-#define XHC_TPL TPL_NOTIFY
+#define XHC_TPL TPL_NOTIFY
-#define CMD_RING_TRB_NUMBER 0x100
-#define TR_RING_TRB_NUMBER 0x100
-#define ERST_NUMBER 0x01
-#define EVENT_RING_TRB_NUMBER 0x200
+#define CMD_RING_TRB_NUMBER 0x100
+#define TR_RING_TRB_NUMBER 0x100
+#define ERST_NUMBER 0x01
+#define EVENT_RING_TRB_NUMBER 0x200
-#define CMD_INTER 0
-#define CTRL_INTER 1
-#define BULK_INTER 2
-#define INT_INTER 3
-#define INT_INTER_ASYNC 4
+#define CMD_INTER 0
+#define CTRL_INTER 1
+#define BULK_INTER 2
+#define INT_INTER 3
+#define INT_INTER_ASYNC 4
-//
-// Iterate through the double linked list. This is delete-safe.
-// Don't touch NextEntry
-//
-#define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \
- for (Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\
- Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)
+#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
-#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
-
-#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
-#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
-#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
+#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
+#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
+#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define XHC_REG_BIT_IS_SET(Xhc, Offset, Bit) \
(XHC_BIT_IS_SET(XhcReadOpReg ((Xhc), (Offset)), (Bit)))
-#define XHCI_IS_DATAIN(EndpointAddr) XHC_BIT_IS_SET((EndpointAddr), 0x80)
+#define XHCI_IS_DATAIN(EndpointAddr) XHC_BIT_IS_SET((EndpointAddr), 0x80)
-#define XHCI_INSTANCE_SIG SIGNATURE_32 ('x', 'h', 'c', 'i')
-#define XHC_FROM_THIS(a) CR(a, USB_XHCI_INSTANCE, Usb2Hc, XHCI_INSTANCE_SIG)
+#define XHCI_INSTANCE_SIG SIGNATURE_32 ('x', 'h', 'c', 'i')
+#define XHC_FROM_THIS(a) CR(a, USB_XHCI_INSTANCE, Usb2Hc, XHCI_INSTANCE_SIG)
#define USB_DESC_TYPE_HUB 0x29
#define USB_DESC_TYPE_HUB_SUPER_SPEED 0x2a
@@ -120,19 +113,19 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
//
#pragma pack(1)
typedef struct {
- UINT8 ProgInterface;
- UINT8 SubClassCode;
- UINT8 BaseCode;
+ UINT8 ProgInterface;
+ UINT8 SubClassCode;
+ UINT8 BaseCode;
} USB_CLASSC;
typedef struct {
- UINT8 Length;
- UINT8 DescType;
- UINT8 NumPorts;
- UINT16 HubCharacter;
- UINT8 PwrOn2PwrGood;
- UINT8 HubContrCurrent;
- UINT8 Filler[16];
+ UINT8 Length;
+ UINT8 DescType;
+ UINT8 NumPorts;
+ UINT16 HubCharacter;
+ UINT8 PwrOn2PwrGood;
+ UINT8 HubContrCurrent;
+ UINT8 Filler[16];
} EFI_USB_HUB_DESCRIPTOR;
#pragma pack()
@@ -140,23 +133,23 @@ struct _USB_DEV_CONTEXT {
//
// Whether this entry in UsbDevContext array is used or not.
//
- BOOLEAN Enabled;
+ BOOLEAN Enabled;
//
// The slot id assigned to the new device through XHCI's Enable_Slot cmd.
//
- UINT8 SlotId;
+ UINT8 SlotId;
//
// The route string presented an attached usb device.
//
- USB_DEV_ROUTE RouteString;
+ USB_DEV_ROUTE RouteString;
//
// The route string of parent device if it exists. Otherwise it's zero.
//
- USB_DEV_ROUTE ParentRouteString;
+ USB_DEV_ROUTE ParentRouteString;
//
// The actual device address assigned by XHCI through Address_Device command.
//
- UINT8 XhciDevAddr;
+ UINT8 XhciDevAddr;
//
// The requested device address from UsbBus driver through Set_Address standard usb request.
// As XHCI spec replaces this request with Address_Device command, we have to record the
@@ -165,23 +158,23 @@ struct _USB_DEV_CONTEXT {
// through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual
// device address and access the actual device.
//
- UINT8 BusDevAddr;
+ UINT8 BusDevAddr;
//
// The pointer to the input device context.
//
- VOID *InputContext;
+ VOID *InputContext;
//
// The pointer to the output device context.
//
- VOID *OutputContext;
+ VOID *OutputContext;
//
// The transfer queue for every endpoint.
//
- VOID *EndpointTransferRing[31];
+ VOID *EndpointTransferRing[31];
//
// The device descriptor which is stored to support XHCI's Evaluate_Context cmd.
//
- EFI_USB_DEVICE_DESCRIPTOR DevDesc;
+ EFI_USB_DEVICE_DESCRIPTOR DevDesc;
//
// As a usb device may include multiple configuration descriptors, we dynamically allocate an array
// to store them.
@@ -189,81 +182,82 @@ struct _USB_DEV_CONTEXT {
// such as Interface descriptor, Endpoint descriptor, and so on.
// These information is used to support XHCI's Config_Endpoint cmd.
//
- EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
+ EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
//
// A device has an active Configuration.
//
- UINT8 ActiveConfiguration;
+ UINT8 ActiveConfiguration;
//
// Every interface has an active AlternateSetting.
//
- UINT8 *ActiveAlternateSetting;
+ UINT8 *ActiveAlternateSetting;
};
struct _USB_XHCI_INSTANCE {
- UINT32 Signature;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 OriginalPciAttributes;
- USBHC_MEM_POOL *MemPool;
+ UINT32 Signature;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 OriginalPciAttributes;
+ USBHC_MEM_POOL *MemPool;
- EFI_USB2_HC_PROTOCOL Usb2Hc;
+ EFI_USB2_HC_PROTOCOL Usb2Hc;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
//
// ExitBootServicesEvent is used to set OS semaphore and
// stop the XHC DMA operation after exit boot service.
//
- EFI_EVENT ExitBootServiceEvent;
- EFI_EVENT PollTimer;
- LIST_ENTRY AsyncIntTransfers;
+ EFI_EVENT ExitBootServiceEvent;
+ EFI_EVENT PollTimer;
+ LIST_ENTRY AsyncIntTransfers;
- UINT8 CapLength; ///< Capability Register Length
- XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
- XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
- XHC_HCCPARAMS HcCParams; ///< Capability Parameters
- UINT32 DBOff; ///< Doorbell Offset
- UINT32 RTSOff; ///< Runtime Register Space Offset
- UINT16 MaxInterrupt;
- UINT32 PageSize;
- UINT64 *ScratchBuf;
- VOID *ScratchMap;
- UINT32 MaxScratchpadBufs;
- UINT64 *ScratchEntry;
- UINTN *ScratchEntryMap;
- UINT32 ExtCapRegBase;
- UINT32 UsbLegSupOffset;
- UINT32 DebugCapSupOffset;
- UINT64 *DCBAA;
- VOID *DCBAAMap;
- UINT32 MaxSlotsEn;
- URB *PendingUrb;
+ UINT8 CapLength; ///< Capability Register Length
+ XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
+ XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
+ XHC_HCCPARAMS HcCParams; ///< Capability Parameters
+ UINT32 DBOff; ///< Doorbell Offset
+ UINT32 RTSOff; ///< Runtime Register Space Offset
+ UINT16 MaxInterrupt;
+ UINT32 PageSize;
+ UINT64 *ScratchBuf;
+ VOID *ScratchMap;
+ UINT32 MaxScratchpadBufs;
+ UINT64 *ScratchEntry;
+ UINTN *ScratchEntryMap;
+ UINT32 ExtCapRegBase;
+ UINT32 UsbLegSupOffset;
+ UINT32 DebugCapSupOffset;
+ UINT32 Usb2SupOffset;
+ UINT32 Usb3SupOffset;
+ UINT64 *DCBAA;
+ VOID *DCBAAMap;
+ UINT32 MaxSlotsEn;
+ URB *PendingUrb;
//
// Cmd Transfer Ring
//
- TRANSFER_RING CmdRing;
+ TRANSFER_RING CmdRing;
//
// EventRing
//
- EVENT_RING EventRing;
+ EVENT_RING EventRing;
//
// Misc
//
- EFI_UNICODE_STRING_TABLE *ControllerNameTable;
+ EFI_UNICODE_STRING_TABLE *ControllerNameTable;
//
// Store device contexts managed by XHCI instance
// The array supports up to 255 devices, entry 0 is reserved and should not be used.
//
- USB_DEV_CONTEXT UsbDevContext[256];
+ USB_DEV_CONTEXT UsbDevContext[256];
- BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
+ BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
};
-
-extern EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding;
-extern EFI_COMPONENT_NAME_PROTOCOL gXhciComponentName;
-extern EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2;
+extern EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL gXhciComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2;
/**
Test to see if this driver supports ControllerHandle. Any
@@ -281,9 +275,9 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2;
EFI_STATUS
EFIAPI
XhcDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -302,9 +296,9 @@ XhcDriverBindingSupported (
EFI_STATUS
EFIAPI
XhcDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -323,10 +317,10 @@ XhcDriverBindingStart (
EFI_STATUS
EFIAPI
XhcDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
);
/**
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
index bdffc3470..2b4a4b244 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
@@ -21,24 +21,24 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
UINT8
XhcReadCapReg8 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT8 Data;
- EFI_STATUS Status;
+ UINT8 Data;
+ EFI_STATUS Status;
Status = Xhc->PciIo->Mem.Read (
Xhc->PciIo,
EfiPciIoWidthUint8,
XHC_BAR_INDEX,
- (UINT64) Offset,
+ (UINT64)Offset,
1,
&Data
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
Data = 0xFF;
}
@@ -57,24 +57,24 @@ XhcReadCapReg8 (
**/
UINT32
XhcReadCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
Status = Xhc->PciIo->Mem.Read (
Xhc->PciIo,
EfiPciIoWidthUint32,
XHC_BAR_INDEX,
- (UINT64) Offset,
+ (UINT64)Offset,
1,
&Data
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@@ -93,12 +93,12 @@ XhcReadCapReg (
**/
UINT32
XhcReadOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
ASSERT (Xhc->CapLength != 0);
@@ -111,8 +111,8 @@ XhcReadOpReg (
&Data
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@@ -129,12 +129,12 @@ XhcReadOpReg (
**/
VOID
XhcWriteOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->CapLength != 0);
@@ -147,15 +147,11 @@ XhcWriteOpReg (
&Data
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
-
-
-
-
/**
Write the data to the XHCI door bell register.
@@ -166,12 +162,12 @@ XhcWriteOpReg (
**/
VOID
XhcWriteDoorBellReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->DBOff != 0);
@@ -184,8 +180,8 @@ XhcWriteDoorBellReg (
&Data
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
@@ -200,12 +196,12 @@ XhcWriteDoorBellReg (
**/
UINT32
XhcReadRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
ASSERT (Xhc->RTSOff != 0);
@@ -218,8 +214,8 @@ XhcReadRuntimeReg (
&Data
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcReadRuntimeReg: Pci Io Read error - %r at %d\n", Status, Offset));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcReadRuntimeReg: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@@ -236,12 +232,12 @@ XhcReadRuntimeReg (
**/
VOID
XhcWriteRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->RTSOff != 0);
@@ -254,8 +250,8 @@ XhcWriteRuntimeReg (
&Data
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcWriteRuntimeReg: Pci Io Write error: %r at %d\n", Status, Offset));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcWriteRuntimeReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
@@ -270,12 +266,12 @@ XhcWriteRuntimeReg (
**/
UINT32
XhcReadExtCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
ASSERT (Xhc->ExtCapRegBase != 0);
@@ -288,8 +284,8 @@ XhcReadExtCapReg (
&Data
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcReadExtCapReg: Pci Io Read error - %r at %d\n", Status, Offset));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcReadExtCapReg: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFF;
}
@@ -306,12 +302,12 @@ XhcReadExtCapReg (
**/
VOID
XhcWriteExtCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->ExtCapRegBase != 0);
@@ -324,12 +320,11 @@ XhcWriteExtCapReg (
&Data
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcWriteExtCapReg: Pci Io Write error: %r at %d\n", Status, Offset));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcWriteExtCapReg: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
-
/**
Set one bit of the runtime register while keeping other bits.
@@ -340,12 +335,12 @@ XhcWriteExtCapReg (
**/
VOID
XhcSetRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadRuntimeReg (Xhc, Offset);
Data |= Bit;
@@ -362,12 +357,12 @@ XhcSetRuntimeRegBit (
**/
VOID
XhcClearRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadRuntimeReg (Xhc, Offset);
Data &= ~Bit;
@@ -384,19 +379,18 @@ XhcClearRuntimeRegBit (
**/
VOID
XhcSetOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadOpReg (Xhc, Offset);
Data |= Bit;
XhcWriteOpReg (Xhc, Offset, Data);
}
-
/**
Clear one bit of the operational register while keeping other bits.
@@ -407,12 +401,12 @@ XhcSetOpRegBit (
**/
VOID
XhcClearOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadOpReg (Xhc, Offset);
Data &= ~Bit;
@@ -423,39 +417,74 @@ XhcClearOpRegBit (
Wait the operation register's bit as specified by Bit
to become set (or clear).
- @param Xhc The XHCI Instance.
- @param Offset The offset of the operation register.
- @param Bit The bit of the register to wait for.
- @param WaitToSet Wait the bit to set or clear.
- @param Timeout The time to wait before abort (in millisecond, ms).
+ @param Xhc The XHCI Instance.
+ @param Offset The offset of the operation register.
+ @param Bit The bit of the register to wait for.
+ @param WaitToSet Wait the bit to set or clear.
+ @param Timeout The time to wait before abort (in millisecond, ms).
- @retval EFI_SUCCESS The bit successfully changed by host controller.
- @retval EFI_TIMEOUT The time out occurred.
+ @retval EFI_SUCCESS The bit successfully changed by host controller.
+ @retval EFI_TIMEOUT The time out occurred.
+ @retval EFI_OUT_OF_RESOURCES Memory for the timer event could not be allocated.
**/
EFI_STATUS
XhcWaitOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit,
- IN BOOLEAN WaitToSet,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit,
+ IN BOOLEAN WaitToSet,
+ IN UINT32 Timeout
)
{
- UINT32 Index;
- UINT64 Loop;
+ EFI_STATUS Status;
+ EFI_EVENT TimeoutEvent;
- Loop = Timeout * XHC_1_MILLISECOND;
+ TimeoutEvent = NULL;
- for (Index = 0; Index < Loop; Index++) {
+ if (Timeout == 0) {
+ return EFI_TIMEOUT;
+ }
+
+ Status = gBS->CreateEvent (
+ EVT_TIMER,
+ TPL_CALLBACK,
+ NULL,
+ NULL,
+ &TimeoutEvent
+ );
+
+ if (EFI_ERROR (Status)) {
+ goto DONE;
+ }
+
+ Status = gBS->SetTimer (
+ TimeoutEvent,
+ TimerRelative,
+ EFI_TIMER_PERIOD_MILLISECONDS (Timeout)
+ );
+
+ if (EFI_ERROR (Status)) {
+ goto DONE;
+ }
+
+ do {
if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {
- return EFI_SUCCESS;
+ Status = EFI_SUCCESS;
+ goto DONE;
}
gBS->Stall (XHC_1_MICROSECOND);
+ } while (EFI_ERROR (gBS->CheckEvent (TimeoutEvent)));
+
+ Status = EFI_TIMEOUT;
+
+DONE:
+ if (TimeoutEvent != NULL) {
+ gBS->CloseEvent (TimeoutEvent);
}
- return EFI_TIMEOUT;
+ return Status;
}
/**
@@ -466,16 +495,16 @@ XhcWaitOpRegBit (
**/
VOID
XhcSetBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- UINT32 Buffer;
+ UINT32 Buffer;
if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
return;
}
- DEBUG ((EFI_D_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
+ DEBUG ((DEBUG_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
Buffer = ((Buffer & (~USBLEGSP_OS_SEMAPHORE)) | USBLEGSP_BIOS_SEMAPHORE);
@@ -490,16 +519,16 @@ XhcSetBiosOwnership (
**/
VOID
XhcClearBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- UINT32 Buffer;
+ UINT32 Buffer;
if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
return;
}
- DEBUG ((EFI_D_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
+ DEBUG ((DEBUG_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
Buffer = ((Buffer & (~USBLEGSP_BIOS_SEMAPHORE)) | USBLEGSP_OS_SEMAPHORE);
@@ -517,13 +546,13 @@ XhcClearBiosOwnership (
**/
UINT32
XhcGetCapabilityAddr (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 CapId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 CapId
)
{
- UINT32 ExtCapOffset;
- UINT8 NextExtCapReg;
- UINT32 Data;
+ UINT32 ExtCapOffset;
+ UINT8 NextExtCapReg;
+ UINT32 Data;
ExtCapOffset = 0;
@@ -535,6 +564,7 @@ XhcGetCapabilityAddr (
if ((Data & 0xFF) == CapId) {
return ExtCapOffset;
}
+
//
// If not, then traverse all of the ext capability registers till finding out it.
//
@@ -545,6 +575,184 @@ XhcGetCapabilityAddr (
return 0xFFFFFFFF;
}
+/**
+ Calculate the offset of the xHCI Supported Protocol Capability.
+
+ @param Xhc The XHCI Instance.
+ @param MajorVersion The USB Major Version in xHCI Support Protocol Capability Field
+
+ @return The offset of xHCI Supported Protocol capability register.
+
+**/
+UINT32
+XhcGetSupportedProtocolCapabilityAddr (
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 MajorVersion
+ )
+{
+ UINT32 ExtCapOffset;
+ UINT8 NextExtCapReg;
+ UINT32 Data;
+ UINT32 NameString;
+ XHC_SUPPORTED_PROTOCOL_DW0 UsbSupportDw0;
+
+ if (Xhc == NULL) {
+ return 0;
+ }
+
+ ExtCapOffset = 0;
+
+ do {
+ //
+ // Check if the extended capability register's capability id is USB Legacy Support.
+ //
+ Data = XhcReadExtCapReg (Xhc, ExtCapOffset);
+ UsbSupportDw0.Dword = Data;
+ if ((Data & 0xFF) == XHC_CAP_USB_SUPPORTED_PROTOCOL) {
+ if (UsbSupportDw0.Data.RevMajor == MajorVersion) {
+ NameString = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_NAME_STRING_OFFSET);
+ if (NameString == XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE) {
+ //
+ // Ensure Name String field is xHCI supported protocols in xHCI Supported Protocol Capability Offset 04h
+ //
+ return ExtCapOffset;
+ }
+ }
+ }
+
+ //
+ // If not, then traverse all of the ext capability registers till finding out it.
+ //
+ NextExtCapReg = (UINT8)((Data >> 8) & 0xFF);
+ ExtCapOffset += (NextExtCapReg << 2);
+ } while (NextExtCapReg != 0);
+
+ return 0xFFFFFFFF;
+}
+
+/**
+ Find PortSpeed value match Protocol Speed ID Value (PSIV).
+
+ @param Xhc The XHCI Instance.
+ @param ExtCapOffset The USB Major Version in xHCI Support Protocol Capability Field
+ @param PortSpeed The Port Speed Field in USB PortSc register
+
+ @return The Protocol Speed ID (PSI) from xHCI Supported Protocol capability register.
+
+**/
+UINT32
+XhciPsivGetPsid (
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 ExtCapOffset,
+ IN UINT8 PortSpeed
+ )
+{
+ XHC_SUPPORTED_PROTOCOL_DW2 PortId;
+ XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID Reg;
+ UINT32 Count;
+
+ if ((Xhc == NULL) || (ExtCapOffset == 0xFFFFFFFF)) {
+ return 0;
+ }
+
+ //
+ // According to XHCI 1.1 spec November 2017,
+ // Section 7.2 xHCI Supported Protocol Capability
+ // 1. Get the PSIC(Protocol Speed ID Count) value.
+ // 2. The PSID register boundary should be Base address + PSIC * 0x04
+ //
+ PortId.Dword = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_DW2_OFFSET);
+
+ for (Count = 0; Count < PortId.Data.Psic; Count++) {
+ Reg.Dword = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_PSI_OFFSET + (Count << 2));
+ if (Reg.Data.Psiv == PortSpeed) {
+ return Reg.Dword;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ Find PortSpeed value match case in XHCI Supported Protocol Capability
+
+ @param Xhc The XHCI Instance.
+ @param PortSpeed The Port Speed Field in USB PortSc register
+
+ @return The USB Port Speed.
+
+**/
+UINT16
+XhcCheckUsbPortSpeedUsedPsic (
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 PortSpeed
+ )
+{
+ XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID SpField;
+ UINT16 UsbSpeedIdMap;
+
+ if (Xhc == NULL) {
+ return 0;
+ }
+
+ SpField.Dword = 0;
+ UsbSpeedIdMap = 0;
+
+ //
+ // Check xHCI Supported Protocol Capability, find the PSIV field to match
+ // PortSpeed definition when the Major Revision is 03h.
+ //
+ if (Xhc->Usb3SupOffset != 0xFFFFFFFF) {
+ SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb3SupOffset, PortSpeed);
+ if (SpField.Dword != 0) {
+ //
+ // Found the corresponding PORTSC value in PSIV field of USB3 offset.
+ //
+ UsbSpeedIdMap = USB_PORT_STAT_SUPER_SPEED;
+ }
+ }
+
+ //
+ // Check xHCI Supported Protocol Capability, find the PSIV field to match
+ // PortSpeed definition when the Major Revision is 02h.
+ //
+ if ((UsbSpeedIdMap == 0) && (Xhc->Usb2SupOffset != 0xFFFFFFFF)) {
+ SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb2SupOffset, PortSpeed);
+ if (SpField.Dword != 0) {
+ //
+ // Found the corresponding PORTSC value in PSIV field of USB2 offset.
+ //
+ if (SpField.Data.Psie == 2) {
+ //
+ // According to XHCI 1.1 spec November 2017,
+ // Section 7.2.1 the Protocol Speed ID Exponent (PSIE) field definition,
+ // PSIE value shall be applied to Protocol Speed ID Mantissa when calculating, value 2 shall represent bit rate in Mb/s
+ //
+ if (SpField.Data.Psim == XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM) {
+ //
+ // PSIM shows as default High-speed protocol, apply to High-speed mapping
+ //
+ UsbSpeedIdMap = USB_PORT_STAT_HIGH_SPEED;
+ }
+ } else if (SpField.Data.Psie == 1) {
+ //
+ // According to XHCI 1.1 spec November 2017,
+ // Section 7.2.1 the Protocol Speed ID Exponent (PSIE) field definition,
+ // PSIE value shall be applied to Protocol Speed ID Mantissa when calculating, value 1 shall represent bit rate in Kb/s
+ //
+ if (SpField.Data.Psim == XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM) {
+ //
+ // PSIM shows as default Low-speed protocol, apply to Low-speed mapping
+ //
+ UsbSpeedIdMap = USB_PORT_STAT_LOW_SPEED;
+ }
+ }
+ }
+ }
+
+ return UsbSpeedIdMap;
+}
+
/**
Whether the XHCI host controller is halted.
@@ -556,13 +764,12 @@ XhcGetCapabilityAddr (
**/
BOOLEAN
XhcIsHalt (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);
}
-
/**
Whether system error occurred.
@@ -574,7 +781,7 @@ XhcIsHalt (
**/
BOOLEAN
XhcIsSysError (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);
@@ -594,11 +801,11 @@ XhcSetHsee (
IN USB_XHCI_INSTANCE *Xhc
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT16 XhciCmd;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT16 XhciCmd;
- PciIo = Xhc->PciIo;
+ PciIo = Xhc->PciIo;
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
@@ -606,7 +813,7 @@ XhcSetHsee (
sizeof (XhciCmd) / sizeof (UINT16),
&XhciCmd
);
- if (!EFI_ERROR(Status)) {
+ if (!EFI_ERROR (Status)) {
if ((XhciCmd & EFI_PCI_COMMAND_SERR) != 0) {
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE);
}
@@ -625,28 +832,29 @@ XhcSetHsee (
**/
EFI_STATUS
XhcResetHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = EFI_SUCCESS;
- DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));
+ DEBUG ((DEBUG_INFO, "XhcResetHC!\n"));
//
// Host can only be reset when it is halt. If not so, halt it
//
if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
Status = XhcHaltHC (Xhc, Timeout);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
}
if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||
- ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {
+ ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0))
+ {
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
//
// Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.
@@ -656,7 +864,7 @@ XhcResetHC (
gBS->Stall (XHC_1_MILLISECOND);
Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
- if (!EFI_ERROR(Status)) {
+ if (!EFI_ERROR (Status)) {
//
// The USBCMD HSEE Bit will be reset to default 0 by USBCMD HCRST.
// Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.
@@ -668,7 +876,6 @@ XhcResetHC (
return Status;
}
-
/**
Halt the XHCI host controller.
@@ -681,18 +888,17 @@ XhcResetHC (
**/
EFI_STATUS
XhcHaltHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);
return Status;
}
-
/**
Set the XHCI host controller to run.
@@ -705,14 +911,13 @@ XhcHaltHC (
**/
EFI_STATUS
XhcRunHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);
return Status;
}
-
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
index cc5c1bf09..5fe2ba4f0 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
@@ -10,187 +10,246 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_XHCI_REG_H_
#define _EFI_XHCI_REG_H_
-#define PCI_IF_XHCI 0x30
+#define PCI_IF_XHCI 0x30
//
// PCI Configuration Registers
//
-#define XHC_BAR_INDEX 0x00
+#define XHC_BAR_INDEX 0x00
-#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
-#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
+#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
+#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
-#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset
+#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset
-#define USB_HUB_CLASS_CODE 0x09
-#define USB_HUB_SUBCLASS_CODE 0x00
+#define USB_HUB_CLASS_CODE 0x09
+#define USB_HUB_SUBCLASS_CODE 0x00
-#define XHC_CAP_USB_LEGACY 0x01
-#define XHC_CAP_USB_DEBUG 0x0A
+#define XHC_CAP_USB_LEGACY 0x01
+#define XHC_CAP_USB_DEBUG 0x0A
+#define XHC_CAP_USB_SUPPORTED_PROTOCOL 0x02
-//============================================//
+// ============================================//
// XHCI register offset //
-//============================================//
+// ============================================//
//
// Capability registers offset
//
-#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
-#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
-#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
-#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
-#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
-#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
-#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
-#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
+#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
+#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
+#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
+#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
+#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
+#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
+#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
+#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
//
// Operational registers offset
//
-#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
-#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
-#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
-#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
-#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
-#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
-#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
-#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
+#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
+#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
+#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
+#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
+#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
+#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
+#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
+#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
//
// Runtime registers offset
//
-#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
-#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
-#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
-#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
-#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
-#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
+#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
+#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
+#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
+#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
+#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
+#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
//
// Debug registers offset
//
-#define XHC_DC_DCCTRL 0x20
+#define XHC_DC_DCCTRL 0x20
-#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
-#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
+#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
+#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
+
+//
+// xHCI Supported Protocol Capability
+//
+#define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB2 0x02
+#define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB3 0x03
+#define XHC_SUPPORTED_PROTOCOL_NAME_STRING_OFFSET 0x04
+#define XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE 0x20425355
+#define XHC_SUPPORTED_PROTOCOL_DW2_OFFSET 0x08
+#define XHC_SUPPORTED_PROTOCOL_PSI_OFFSET 0x10
+#define XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM 480
+#define XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM 1500
#pragma pack (1)
typedef struct {
- UINT8 MaxSlots; // Number of Device Slots
- UINT16 MaxIntrs:11; // Number of Interrupters
- UINT16 Rsvd:5;
- UINT8 MaxPorts; // Number of Ports
+ UINT8 MaxSlots; // Number of Device Slots
+ UINT16 MaxIntrs : 11; // Number of Interrupters
+ UINT16 Rsvd : 5;
+ UINT8 MaxPorts; // Number of Ports
} HCSPARAMS1;
//
// Structural Parameters 1 Register Bitmap Definition
//
typedef union {
- UINT32 Dword;
- HCSPARAMS1 Data;
+ UINT32 Dword;
+ HCSPARAMS1 Data;
} XHC_HCSPARAMS1;
typedef struct {
- UINT32 Ist:4; // Isochronous Scheduling Threshold
- UINT32 Erst:4; // Event Ring Segment Table Max
- UINT32 Rsvd:13;
- UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi
- UINT32 Spr:1; // Scratchpad Restore
- UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo
+ UINT32 Ist : 4; // Isochronous Scheduling Threshold
+ UINT32 Erst : 4; // Event Ring Segment Table Max
+ UINT32 Rsvd : 13;
+ UINT32 ScratchBufHi : 5; // Max Scratchpad Buffers Hi
+ UINT32 Spr : 1; // Scratchpad Restore
+ UINT32 ScratchBufLo : 5; // Max Scratchpad Buffers Lo
} HCSPARAMS2;
//
// Structural Parameters 2 Register Bitmap Definition
//
typedef union {
- UINT32 Dword;
- HCSPARAMS2 Data;
+ UINT32 Dword;
+ HCSPARAMS2 Data;
} XHC_HCSPARAMS2;
typedef struct {
- UINT16 Ac64:1; // 64-bit Addressing Capability
- UINT16 Bnc:1; // BW Negotiation Capability
- UINT16 Csz:1; // Context Size
- UINT16 Ppc:1; // Port Power Control
- UINT16 Pind:1; // Port Indicators
- UINT16 Lhrc:1; // Light HC Reset Capability
- UINT16 Ltc:1; // Latency Tolerance Messaging Capability
- UINT16 Nss:1; // No Secondary SID Support
- UINT16 Pae:1; // Parse All Event Data
- UINT16 Rsvd:3;
- UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size
- UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
+ UINT16 Ac64 : 1; // 64-bit Addressing Capability
+ UINT16 Bnc : 1; // BW Negotiation Capability
+ UINT16 Csz : 1; // Context Size
+ UINT16 Ppc : 1; // Port Power Control
+ UINT16 Pind : 1; // Port Indicators
+ UINT16 Lhrc : 1; // Light HC Reset Capability
+ UINT16 Ltc : 1; // Latency Tolerance Messaging Capability
+ UINT16 Nss : 1; // No Secondary SID Support
+ UINT16 Pae : 1; // Parse All Event Data
+ UINT16 Rsvd : 3;
+ UINT16 MaxPsaSize : 4; // Maximum Primary Stream Array Size
+ UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
} HCCPARAMS;
//
// Capability Parameters Register Bitmap Definition
//
typedef union {
- UINT32 Dword;
- HCCPARAMS Data;
+ UINT32 Dword;
+ HCCPARAMS Data;
} XHC_HCCPARAMS;
+//
+// xHCI Supported Protocol Cabability
+//
+typedef struct {
+ UINT8 CapId;
+ UINT8 NextExtCapReg;
+ UINT8 RevMinor;
+ UINT8 RevMajor;
+} SUPPORTED_PROTOCOL_DW0;
+
+typedef union {
+ UINT32 Dword;
+ SUPPORTED_PROTOCOL_DW0 Data;
+} XHC_SUPPORTED_PROTOCOL_DW0;
+
+typedef struct {
+ UINT32 NameString;
+} XHC_SUPPORTED_PROTOCOL_DW1;
+
+typedef struct {
+ UINT8 CompPortOffset;
+ UINT8 CompPortCount;
+ UINT16 ProtocolDef : 12;
+ UINT16 Psic : 4;
+} SUPPORTED_PROTOCOL_DW2;
+
+typedef union {
+ UINT32 Dword;
+ SUPPORTED_PROTOCOL_DW2 Data;
+} XHC_SUPPORTED_PROTOCOL_DW2;
+
+typedef struct {
+ UINT16 Psiv : 4;
+ UINT16 Psie : 2;
+ UINT16 Plt : 2;
+ UINT16 Pfd : 1;
+ UINT16 RsvdP : 5;
+ UINT16 Lp : 2;
+ UINT16 Psim;
+} SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID;
+
+typedef union {
+ UINT32 Dword;
+ SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID Data;
+} XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID;
+
#pragma pack ()
//
// Register Bit Definition
//
-#define XHC_USBCMD_RUN BIT0 // Run/Stop
-#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
-#define XHC_USBCMD_INTE BIT2 // Interrupter Enable
-#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
+#define XHC_USBCMD_RUN BIT0 // Run/Stop
+#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
+#define XHC_USBCMD_INTE BIT2 // Interrupter Enable
+#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
-#define XHC_USBSTS_HALT BIT0 // Host Controller Halted
-#define XHC_USBSTS_HSE BIT2 // Host System Error
-#define XHC_USBSTS_EINT BIT3 // Event Interrupt
-#define XHC_USBSTS_PCD BIT4 // Port Change Detect
-#define XHC_USBSTS_SSS BIT8 // Save State Status
-#define XHC_USBSTS_RSS BIT9 // Restore State Status
-#define XHC_USBSTS_SRE BIT10 // Save/Restore Error
-#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
-#define XHC_USBSTS_HCE BIT12 // Host Controller Error
+#define XHC_USBSTS_HALT BIT0 // Host Controller Halted
+#define XHC_USBSTS_HSE BIT2 // Host System Error
+#define XHC_USBSTS_EINT BIT3 // Event Interrupt
+#define XHC_USBSTS_PCD BIT4 // Port Change Detect
+#define XHC_USBSTS_SSS BIT8 // Save State Status
+#define XHC_USBSTS_RSS BIT9 // Restore State Status
+#define XHC_USBSTS_SRE BIT10 // Save/Restore Error
+#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
+#define XHC_USBSTS_HCE BIT12 // Host Controller Error
-#define XHC_PAGESIZE_MASK 0xFFFF // Page Size
+#define XHC_PAGESIZE_MASK 0xFFFF // Page Size
-#define XHC_CRCR_RCS BIT0 // Ring Cycle State
-#define XHC_CRCR_CS BIT1 // Command Stop
-#define XHC_CRCR_CA BIT2 // Command Abort
-#define XHC_CRCR_CRR BIT3 // Command Ring Running
+#define XHC_CRCR_RCS BIT0 // Ring Cycle State
+#define XHC_CRCR_CS BIT1 // Command Stop
+#define XHC_CRCR_CA BIT2 // Command Abort
+#define XHC_CRCR_CRR BIT3 // Command Ring Running
-#define XHC_CONFIG_MASK 0xFF // Command Ring Running
+#define XHC_CONFIG_MASK 0xFF // Command Ring Running
-#define XHC_PORTSC_CCS BIT0 // Current Connect Status
-#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
-#define XHC_PORTSC_OCA BIT3 // Over-current Active
-#define XHC_PORTSC_RESET BIT4 // Port Reset
-#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
-#define XHC_PORTSC_PP BIT9 // Port Power
-#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
-#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
-#define XHC_PORTSC_CSC BIT17 // Connect Status Change
-#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
-#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
-#define XHC_PORTSC_OCC BIT20 // Over-Current Change
-#define XHC_PORTSC_PRC BIT21 // Port Reset Change
-#define XHC_PORTSC_PLC BIT22 // Port Link State Change
-#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
-#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
+#define XHC_PORTSC_CCS BIT0 // Current Connect Status
+#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
+#define XHC_PORTSC_OCA BIT3 // Over-current Active
+#define XHC_PORTSC_RESET BIT4 // Port Reset
+#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
+#define XHC_PORTSC_PP BIT9 // Port Power
+#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
+#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
+#define XHC_PORTSC_CSC BIT17 // Connect Status Change
+#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
+#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
+#define XHC_PORTSC_OCC BIT20 // Over-Current Change
+#define XHC_PORTSC_PRC BIT21 // Port Reset Change
+#define XHC_PORTSC_PLC BIT22 // Port Link State Change
+#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
+#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
-#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
-#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
-#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
-#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
-#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
-#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
-#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
-#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
-#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
-#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
-#define XHC_IMAN_IP BIT0 // Interrupt Pending
-#define XHC_IMAN_IE BIT1 // Interrupt Enable
+#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
+#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
+#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
+#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
+#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
+#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
+#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
+#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
+#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
+#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
+#define XHC_IMAN_IP BIT0 // Interrupt Pending
+#define XHC_IMAN_IE BIT1 // Interrupt Enable
-#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
-#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
+#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
+#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
//
// Hub Class Feature Selector for Clear Port Feature Request
@@ -198,8 +257,8 @@ typedef union {
// For more details, Please refer to USB 3.0 Spec Table 10-7.
//
typedef enum {
- Usb3PortBHPortReset = 28,
- Usb3PortBHPortResetChange = 29
+ Usb3PortBHPortReset = 28,
+ Usb3PortBHPortResetChange = 29
} XHC_PORT_FEATURE;
//
@@ -207,16 +266,16 @@ typedef enum {
// UEFI's port states.
//
typedef struct {
- UINT32 HwState;
- UINT16 UefiState;
+ UINT32 HwState;
+ UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
// Structure to map the hardware port states to feature selector for clear port feature request.
//
typedef struct {
- UINT32 HwState;
- UINT16 Selector;
+ UINT32 HwState;
+ UINT16 Selector;
} USB_CLEAR_PORT_MAP;
/**
@@ -231,8 +290,8 @@ typedef struct {
**/
UINT8
XhcReadCapReg8 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -247,8 +306,8 @@ XhcReadCapReg8 (
**/
UINT32
XhcReadCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -263,8 +322,8 @@ XhcReadCapReg (
**/
UINT32
XhcReadOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -277,12 +336,11 @@ XhcReadOpReg (
**/
VOID
XhcWriteOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
-
/**
Read XHCI runtime register.
@@ -294,8 +352,8 @@ XhcWriteOpReg (
**/
UINT32
XhcReadRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -308,12 +366,11 @@ XhcReadRuntimeReg (
**/
VOID
XhcWriteRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
-
/**
Write the data to the XHCI door bell register.
@@ -324,9 +381,9 @@ XhcWriteRuntimeReg (
**/
VOID
XhcWriteDoorBellReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
/**
@@ -339,9 +396,9 @@ XhcWriteDoorBellReg (
**/
VOID
XhcSetOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -354,9 +411,9 @@ XhcSetOpRegBit (
**/
VOID
XhcClearOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -375,11 +432,11 @@ XhcClearOpRegBit (
**/
EFI_STATUS
XhcWaitOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit,
- IN BOOLEAN WaitToSet,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit,
+ IN BOOLEAN WaitToSet,
+ IN UINT32 Timeout
);
/**
@@ -393,8 +450,8 @@ XhcWaitOpRegBit (
**/
UINT32
XhcReadRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -407,9 +464,9 @@ XhcReadRuntimeReg (
**/
VOID
XhcWriteRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
/**
@@ -422,9 +479,9 @@ XhcWriteRuntimeReg (
**/
VOID
XhcSetRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -437,9 +494,9 @@ XhcSetRuntimeRegBit (
**/
VOID
XhcClearRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -453,8 +510,8 @@ XhcClearRuntimeRegBit (
**/
UINT32
XhcReadExtCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -468,7 +525,7 @@ XhcReadExtCapReg (
**/
BOOLEAN
XhcIsHalt (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -482,7 +539,7 @@ XhcIsHalt (
**/
BOOLEAN
XhcIsSysError (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -497,8 +554,8 @@ XhcIsSysError (
**/
EFI_STATUS
XhcResetHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
);
/**
@@ -513,8 +570,8 @@ XhcResetHC (
**/
EFI_STATUS
XhcHaltHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
);
/**
@@ -529,8 +586,8 @@ XhcHaltHC (
**/
EFI_STATUS
XhcRunHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
);
/**
@@ -544,8 +601,38 @@ XhcRunHC (
**/
UINT32
XhcGetCapabilityAddr (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 CapId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 CapId
+ );
+
+/**
+ Calculate the offset of the xHCI Supported Protocol Capability.
+
+ @param Xhc The XHCI Instance.
+ @param MajorVersion The USB Major Version in xHCI Support Protocol Capability Field
+
+ @return The offset of xHCI Supported Protocol capability register.
+
+**/
+UINT32
+XhcGetSupportedProtocolCapabilityAddr (
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 MajorVersion
+ );
+
+/**
+ Find SpeedField value match with Port Speed ID value.
+
+ @param Xhc The XHCI Instance.
+ @param Speed The Port Speed filed in USB PortSc register
+
+ @return The USB Port Speed.
+
+**/
+UINT16
+XhcCheckUsbPortSpeedUsedPsic (
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 Speed
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index e4f3d4c2d..c2906e06f 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -2,7 +2,8 @@
XHCI transfer scheduling routines.
-Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2011 - 2020, Intel Corporation. All rights reserved.
+Copyright (c) Microsoft Corporation.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -18,26 +19,26 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return Created URB or NULL.
**/
-URB*
+URB *
XhcCreateCmdTrb (
IN USB_XHCI_INSTANCE *Xhc,
IN TRB_TEMPLATE *CmdTrb
)
{
- URB *Urb;
+ URB *Urb;
- Urb = AllocateZeroPool(sizeof (URB));
+ Urb = AllocateZeroPool (sizeof (URB));
if (Urb == NULL) {
return NULL;
}
- Urb->Signature = XHC_URB_SIG;
+ Urb->Signature = XHC_URB_SIG;
- Urb->Ring = &Xhc->CmdRing;
+ Urb->Ring = &Xhc->CmdRing;
XhcSyncTrsRing (Xhc, Urb->Ring);
- Urb->TrbNum = 1;
- Urb->TrbStart = Urb->Ring->RingEnqueue;
- CopyMem(Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));
+ Urb->TrbNum = 1;
+ Urb->TrbStart = Urb->Ring->RingEnqueue;
+ CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));
Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;
Urb->TrbEnd = Urb->TrbStart;
@@ -62,14 +63,14 @@ XhcCreateCmdTrb (
EFI_STATUS
EFIAPI
XhcCmdTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN TRB_TEMPLATE *CmdTrb,
- IN UINTN Timeout,
- OUT TRB_TEMPLATE **EvtTrb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN TRB_TEMPLATE *CmdTrb,
+ IN UINTN Timeout,
+ OUT TRB_TEMPLATE **EvtTrb
)
{
- EFI_STATUS Status;
- URB *Urb;
+ EFI_STATUS Status;
+ URB *Urb;
//
// Validate the parameters
@@ -81,7 +82,7 @@ XhcCmdTransfer (
Status = EFI_DEVICE_ERROR;
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
- DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: HC is halted\n"));
+ DEBUG ((DEBUG_ERROR, "XhcCmdTransfer: HC is halted\n"));
goto ON_EXIT;
}
@@ -91,7 +92,7 @@ XhcCmdTransfer (
Urb = XhcCreateCmdTrb (Xhc, CmdTrb);
if (Urb == NULL) {
- DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: failed to create URB\n"));
+ DEBUG ((DEBUG_ERROR, "XhcCmdTransfer: failed to create URB\n"));
Status = EFI_OUT_OF_RESOURCES;
goto ON_EXIT;
}
@@ -127,26 +128,26 @@ ON_EXIT:
@return Created URB or NULL
**/
-URB*
+URB *
XhcCreateUrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
)
{
- USB_ENDPOINT *Ep;
- EFI_STATUS Status;
- URB *Urb;
+ USB_ENDPOINT *Ep;
+ EFI_STATUS Status;
+ URB *Urb;
- Urb = AllocateZeroPool(sizeof (URB));
+ Urb = AllocateZeroPool (sizeof (URB));
if (Urb == NULL) {
return NULL;
}
@@ -169,10 +170,10 @@ XhcCreateUrb (
Urb->Context = Context;
Status = XhcCreateTransferTrb (Xhc, Urb);
- ASSERT_EFI_ERROR(Status);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status));
- FreePool(Urb);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status));
+ FreePool (Urb);
Urb = NULL;
}
@@ -188,8 +189,8 @@ XhcCreateUrb (
**/
VOID
XhcFreeUrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
if ((Xhc == NULL) || (Urb == NULL)) {
@@ -200,7 +201,7 @@ XhcFreeUrb (
Xhc->PciIo->Unmap (Xhc->PciIo, Urb->DataMap);
}
- FreePool(Urb);
+ FreePool (Urb);
}
/**
@@ -214,23 +215,23 @@ XhcFreeUrb (
**/
EFI_STATUS
XhcCreateTransferTrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- VOID *OutputContext;
- TRANSFER_RING *EPRing;
- UINT8 EPType;
- UINT8 SlotId;
- UINT8 Dci;
- TRB *TrbStart;
- UINTN TotalLen;
- UINTN Len;
- UINTN TrbNum;
- EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *Map;
- EFI_STATUS Status;
+ VOID *OutputContext;
+ TRANSFER_RING *EPRing;
+ UINT8 EPType;
+ UINT8 SlotId;
+ UINT8 Dci;
+ TRB *TrbStart;
+ UINTN TotalLen;
+ UINTN Len;
+ UINTN TrbNum;
+ EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *Map;
+ EFI_STATUS Status;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
@@ -243,37 +244,37 @@ XhcCreateTransferTrb (
Urb->Completed = 0;
Urb->Result = EFI_USB_NOERROR;
- Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
+ Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
- EPRing = (TRANSFER_RING *)(UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
- Urb->Ring = EPRing;
+ EPRing = (TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
+ Urb->Ring = EPRing;
OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
if (Xhc->HcCParams.Data.Csz == 0) {
- EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
+ EPType = (UINT8)((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
} else {
- EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
+ EPType = (UINT8)((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
}
//
// No need to remap.
//
if ((Urb->Data != NULL) && (Urb->DataMap == NULL)) {
- if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
+ if (((UINT8)(Urb->Ep.Direction)) == EfiUsbDataIn) {
MapOp = EfiPciIoOperationBusMasterWrite;
} else {
MapOp = EfiPciIoOperationBusMasterRead;
}
- Len = Urb->DataLen;
- Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
+ Len = Urb->DataLen;
+ Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
- if (EFI_ERROR(Status) || (Len != Urb->DataLen)) {
- DEBUG ((EFI_D_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
+ if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
+ DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
return EFI_OUT_OF_RESOURCES;
}
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
- Urb->DataMap = Map;
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
+ Urb->DataMap = Map;
}
//
@@ -286,7 +287,7 @@ XhcCreateTransferTrb (
//
// For control transfer, create SETUP_STAGE_TRB first.
//
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;
TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;
TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;
@@ -297,13 +298,19 @@ XhcCreateTransferTrb (
TrbStart->TrbCtrSetup.IOC = 1;
TrbStart->TrbCtrSetup.IDT = 1;
TrbStart->TrbCtrSetup.Type = TRB_TYPE_SETUP_STAGE;
- if (Urb->Ep.Direction == EfiUsbDataIn) {
- TrbStart->TrbCtrSetup.TRT = 3;
- } else if (Urb->Ep.Direction == EfiUsbDataOut) {
- TrbStart->TrbCtrSetup.TRT = 2;
+ if (Urb->DataLen > 0) {
+ if (Urb->Ep.Direction == EfiUsbDataIn) {
+ TrbStart->TrbCtrSetup.TRT = 3;
+ } else if (Urb->Ep.Direction == EfiUsbDataOut) {
+ TrbStart->TrbCtrSetup.TRT = 2;
+ } else {
+ DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Direction sholud be IN or OUT when Data exists!\n"));
+ ASSERT (FALSE);
+ }
} else {
TrbStart->TrbCtrSetup.TRT = 0;
}
+
//
// Update the cycle bit
//
@@ -315,10 +322,10 @@ XhcCreateTransferTrb (
//
if (Urb->DataLen > 0) {
XhcSyncTrsRing (Xhc, EPRing);
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
- TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->DataPhy);
- TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->DataPhy);
- TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT (Urb->DataPhy);
+ TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT (Urb->DataPhy);
+ TrbStart->TrbCtrData.Length = (UINT32)Urb->DataLen;
TrbStart->TrbCtrData.TDSize = 0;
TrbStart->TrbCtrData.IntTarget = 0;
TrbStart->TrbCtrData.ISP = 1;
@@ -333,18 +340,20 @@ XhcCreateTransferTrb (
} else {
TrbStart->TrbCtrData.DIR = 0;
}
+
//
// Update the cycle bit
//
TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;
Urb->TrbNum++;
}
+
//
// For control transfer, create STATUS_STAGE_TRB.
// Get the pointer to next TRB for status stage use
//
XhcSyncTrsRing (Xhc, EPRing);
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrStatus.IntTarget = 0;
TrbStart->TrbCtrStatus.IOC = 1;
TrbStart->TrbCtrStatus.CH = 0;
@@ -356,6 +365,7 @@ XhcCreateTransferTrb (
} else {
TrbStart->TrbCtrStatus.DIR = 0;
}
+
//
// Update the cycle bit
//
@@ -381,10 +391,11 @@ XhcCreateTransferTrb (
} else {
Len = 0x10000;
}
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.Length = (UINT32) Len;
+
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.Length = (UINT32)Len;
TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1;
@@ -416,10 +427,11 @@ XhcCreateTransferTrb (
} else {
Len = 0x10000;
}
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.Length = (UINT32) Len;
+
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.Length = (UINT32)Len;
TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1;
@@ -440,7 +452,7 @@ XhcCreateTransferTrb (
break;
default:
- DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));
+ DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n", EPType));
ASSERT (FALSE);
break;
}
@@ -448,7 +460,6 @@ XhcCreateTransferTrb (
return EFI_SUCCESS;
}
-
/**
Initialize the XHCI host controller for schedule.
@@ -457,7 +468,7 @@ XhcCreateTransferTrb (
**/
VOID
XhcInitSched (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
VOID *Dcbaa;
@@ -494,8 +505,8 @@ XhcInitSched (
// The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
// Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
//
- Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);
- Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Entries);
+ Entries = (Xhc->MaxSlotsEn + 1) * sizeof (UINT64);
+ Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Entries);
ASSERT (Dcbaa != NULL);
ZeroMem (Dcbaa, Entries);
@@ -511,27 +522,27 @@ XhcInitSched (
//
// Allocate the buffer to record the Mapping for each scratch buffer in order to Unmap them
//
- ScratchEntryMap = AllocateZeroPool(sizeof (UINTN) * MaxScratchpadBufs);
+ ScratchEntryMap = AllocateZeroPool (sizeof (UINTN) * MaxScratchpadBufs);
ASSERT (ScratchEntryMap != NULL);
Xhc->ScratchEntryMap = ScratchEntryMap;
//
// Allocate the buffer to record the host address for each entry
//
- ScratchEntry = AllocateZeroPool(sizeof (UINT64) * MaxScratchpadBufs);
+ ScratchEntry = AllocateZeroPool (sizeof (UINT64) * MaxScratchpadBufs);
ASSERT (ScratchEntry != NULL);
Xhc->ScratchEntry = ScratchEntry;
ScratchPhy = 0;
- Status = UsbHcAllocateAlignedPages (
- Xhc->PciIo,
- EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
- Xhc->PageSize,
- (VOID **) &ScratchBuf,
- &ScratchPhy,
- &Xhc->ScratchMap
- );
- ASSERT_EFI_ERROR(Status);
+ Status = UsbHcAllocateAlignedPages (
+ Xhc->PciIo,
+ EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
+ Xhc->PageSize,
+ (VOID **)&ScratchBuf,
+ &ScratchPhy,
+ &Xhc->ScratchMap
+ );
+ ASSERT_EFI_ERROR (Status);
ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));
Xhc->ScratchBuf = ScratchBuf;
@@ -541,26 +552,27 @@ XhcInitSched (
//
for (Index = 0; Index < MaxScratchpadBufs; Index++) {
ScratchEntryPhy = 0;
- Status = UsbHcAllocateAlignedPages (
- Xhc->PciIo,
- EFI_SIZE_TO_PAGES (Xhc->PageSize),
- Xhc->PageSize,
- (VOID **) &ScratchEntry[Index],
- &ScratchEntryPhy,
- (VOID **) &ScratchEntryMap[Index]
- );
- ASSERT_EFI_ERROR(Status);
+ Status = UsbHcAllocateAlignedPages (
+ Xhc->PciIo,
+ EFI_SIZE_TO_PAGES (Xhc->PageSize),
+ Xhc->PageSize,
+ (VOID **)&ScratchEntry[Index],
+ &ScratchEntryPhy,
+ (VOID **)&ScratchEntryMap[Index]
+ );
+ ASSERT_EFI_ERROR (Status);
ZeroMem ((VOID *)(UINTN)ScratchEntry[Index], Xhc->PageSize);
//
// Fill with the PCI device address
//
*ScratchBuf++ = ScratchEntryPhy;
}
+
//
// The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
// Device Context Base Address Array points to the Scratchpad Buffer Array.
//
- *(UINT64 *)Dcbaa = (UINT64)(UINTN) ScratchPhy;
+ *(UINT64 *)Dcbaa = (UINT64)(UINTN)ScratchPhy;
}
//
@@ -573,10 +585,10 @@ XhcInitSched (
// So divide it to two 32-bytes width register access.
//
DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries);
- XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(DcbaaPhy));
+ XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy));
XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));
- DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
+ DEBUG ((DEBUG_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
//
// Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
@@ -590,15 +602,15 @@ XhcInitSched (
// Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
// So we set RCS as inverted PCS init value to let Command Ring empty
//
- CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
- CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN) CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
+ CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
+ CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN)CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
ASSERT ((CmdRingPhy & 0x3F) == 0);
CmdRingPhy |= XHC_CRCR_RCS;
//
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access.
//
- XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRingPhy));
+ XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT (CmdRingPhy));
XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));
//
@@ -615,9 +627,13 @@ XhcInitSched (
// Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
//
CreateEventRing (Xhc, &Xhc->EventRing);
- DEBUG ((DEBUG_INFO, "XhcInitSched: Created CMD ring [%p~%p) EVENT ring [%p~%p)\n",
- Xhc->CmdRing.RingSeg0, (UINTN)Xhc->CmdRing.RingSeg0 + sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,
- Xhc->EventRing.EventRingSeg0, (UINTN)Xhc->EventRing.EventRingSeg0 + sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER
+ DEBUG ((
+ DEBUG_INFO,
+ "XhcInitSched: Created CMD ring [%p~%p) EVENT ring [%p~%p)\n",
+ Xhc->CmdRing.RingSeg0,
+ (UINTN)Xhc->CmdRing.RingSeg0 + sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,
+ Xhc->EventRing.EventRingSeg0,
+ (UINTN)Xhc->EventRing.EventRingSeg0 + sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER
));
}
@@ -638,39 +654,40 @@ XhcInitSched (
EFI_STATUS
EFIAPI
XhcRecoverHaltedEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- UINT8 Dci;
- UINT8 SlotId;
+ EFI_STATUS Status;
+ UINT8 Dci;
+ UINT8 SlotId;
Status = EFI_SUCCESS;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
+
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
- DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));
+ DEBUG ((DEBUG_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));
//
// 1) Send Reset endpoint command to transit from halt to stop state
//
- Status = XhcResetEndpoint(Xhc, SlotId, Dci);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
+ Status = XhcResetEndpoint (Xhc, SlotId, Dci);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
goto Done;
}
//
// 2)Set dequeue pointer
//
- Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
+ Status = XhcSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
}
@@ -700,37 +717,38 @@ Done:
EFI_STATUS
EFIAPI
XhcDequeueTrbFromEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- UINT8 Dci;
- UINT8 SlotId;
+ EFI_STATUS Status;
+ UINT8 Dci;
+ UINT8 SlotId;
Status = EFI_SUCCESS;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
+
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
- DEBUG ((EFI_D_INFO, "Stop Slot = %x,Dci = %x\n", SlotId, Dci));
+ DEBUG ((DEBUG_INFO, "Stop Slot = %x,Dci = %x\n", SlotId, Dci));
//
// 1) Send Stop endpoint command to stop xHC from executing of the TDs on the endpoint
//
- Status = XhcStopEndpoint(Xhc, SlotId, Dci, Urb);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
+ Status = XhcStopEndpoint (Xhc, SlotId, Dci, Urb);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
goto Done;
}
//
// 2)Set dequeue pointer
//
- if (Urb->Finished && Urb->Result == EFI_USB_NOERROR) {
+ if (Urb->Finished && (Urb->Result == EFI_USB_NOERROR)) {
//
// Return Already Started to indicate the pending URB is finished.
// This fixes BULK data loss when transfer is detected as timeout
@@ -739,8 +757,8 @@ XhcDequeueTrbFromEndpoint (
Status = EFI_ALREADY_STARTED;
DEBUG ((DEBUG_INFO, "XhcDequeueTrbFromEndpoint: Pending URB is finished: Length Actual/Expect = %d/%d!\n", Urb->Completed, Urb->DataLen));
} else {
- Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
- if (EFI_ERROR(Status)) {
+ Status = XhcSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
}
@@ -764,8 +782,8 @@ Done:
**/
VOID
CreateEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- OUT EVENT_RING *EventRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ OUT EVENT_RING *EventRing
)
{
VOID *Buf;
@@ -777,15 +795,15 @@ CreateEventRing (
ASSERT (EventRing != NULL);
Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;
- Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, Size);
EventRing->EventRingSeg0 = Buf;
EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
- EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
- EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
+ EventRing->EventRingDequeue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;
+ EventRing->EventRingEnqueue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;
DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
@@ -796,12 +814,12 @@ CreateEventRing (
EventRing->EventRingCCS = 1;
Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;
- Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, Size);
- ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
+ ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *)Buf;
EventRing->ERSTBase = ERSTBase;
ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);
ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);
@@ -826,12 +844,12 @@ CreateEventRing (
XhcWriteRuntimeReg (
Xhc,
XHC_ERDP_OFFSET,
- XHC_LOW_32BIT((UINT64)(UINTN)DequeuePhy)
+ XHC_LOW_32BIT ((UINT64)(UINTN)DequeuePhy)
);
XhcWriteRuntimeReg (
Xhc,
XHC_ERDP_OFFSET + 4,
- XHC_HIGH_32BIT((UINT64)(UINTN)DequeuePhy)
+ XHC_HIGH_32BIT ((UINT64)(UINTN)DequeuePhy)
);
//
// Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)
@@ -842,12 +860,12 @@ CreateEventRing (
XhcWriteRuntimeReg (
Xhc,
XHC_ERSTBA_OFFSET,
- XHC_LOW_32BIT((UINT64)(UINTN)ERSTPhy)
+ XHC_LOW_32BIT ((UINT64)(UINTN)ERSTPhy)
);
XhcWriteRuntimeReg (
Xhc,
XHC_ERSTBA_OFFSET + 4,
- XHC_HIGH_32BIT((UINT64)(UINTN)ERSTPhy)
+ XHC_HIGH_32BIT ((UINT64)(UINTN)ERSTPhy)
);
//
// Need set IMAN IE bit to enble the ring interrupt
@@ -865,9 +883,9 @@ CreateEventRing (
**/
VOID
CreateTransferRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINTN TrbNum,
- OUT TRANSFER_RING *TransferRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINTN TrbNum,
+ OUT TRANSFER_RING *TransferRing
)
{
VOID *Buf;
@@ -876,28 +894,28 @@ CreateTransferRing (
Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);
- TransferRing->RingSeg0 = Buf;
- TransferRing->TrbNumber = TrbNum;
- TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
- TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
- TransferRing->RingPCS = 1;
+ TransferRing->RingSeg0 = Buf;
+ TransferRing->TrbNumber = TrbNum;
+ TransferRing->RingEnqueue = (TRB_TEMPLATE *)TransferRing->RingSeg0;
+ TransferRing->RingDequeue = (TRB_TEMPLATE *)TransferRing->RingSeg0;
+ TransferRing->RingPCS = 1;
//
// 4.9.2 Transfer Ring Management
// To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
// point to the first TRB in the ring.
//
- EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
+ EndTrb = (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
EndTrb->Type = TRB_TYPE_LINK;
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);
EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);
//
// Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
//
- EndTrb->TC = 1;
+ EndTrb->TC = 1;
//
// Set Cycle bit as other TRB PCS init value
//
@@ -914,11 +932,11 @@ CreateTransferRing (
EFI_STATUS
EFIAPI
XhcFreeEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN EVENT_RING *EventRing
-)
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN EVENT_RING *EventRing
+ )
{
- if(EventRing->EventRingSeg0 == NULL) {
+ if (EventRing->EventRingSeg0 == NULL) {
return EFI_SUCCESS;
}
@@ -942,11 +960,11 @@ XhcFreeEventRing (
**/
VOID
XhcFreeSched (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- UINT32 Index;
- UINT64 *ScratchEntry;
+ UINT32 Index;
+ UINT64 *ScratchEntry;
if (Xhc->ScratchBuf != NULL) {
ScratchEntry = Xhc->ScratchEntry;
@@ -954,14 +972,15 @@ XhcFreeSched (
//
// Free Scratchpad Buffers
//
- UsbHcFreeAlignedPages (Xhc->PciIo, (VOID*)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]);
+ UsbHcFreeAlignedPages (Xhc->PciIo, (VOID *)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *)Xhc->ScratchEntryMap[Index]);
}
+
//
// Free Scratchpad Buffer Array
//
UsbHcFreeAlignedPages (Xhc->PciIo, Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)), Xhc->ScratchMap);
- FreePool(Xhc->ScratchEntryMap);
- FreePool(Xhc->ScratchEntry);
+ FreePool (Xhc->ScratchEntryMap);
+ FreePool (Xhc->ScratchEntry);
}
if (Xhc->CmdRing.RingSeg0 != NULL) {
@@ -969,10 +988,10 @@ XhcFreeSched (
Xhc->CmdRing.RingSeg0 = NULL;
}
- XhcFreeEventRing (Xhc,&Xhc->EventRing);
+ XhcFreeEventRing (Xhc, &Xhc->EventRing);
if (Xhc->DCBAA != NULL) {
- UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof(UINT64));
+ UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof (UINT64));
Xhc->DCBAA = NULL;
}
@@ -998,30 +1017,31 @@ XhcFreeSched (
**/
BOOLEAN
IsTransferRingTrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN TRB_TEMPLATE *Trb,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN TRB_TEMPLATE *Trb,
+ IN URB *Urb
)
{
- LINK_TRB *LinkTrb;
- TRB_TEMPLATE *CheckedTrb;
- UINTN Index;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ LINK_TRB *LinkTrb;
+ TRB_TEMPLATE *CheckedTrb;
+ UINTN Index;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
CheckedTrb = Urb->TrbStart;
for (Index = 0; Index < Urb->TrbNum; Index++) {
if (Trb == CheckedTrb) {
return TRUE;
}
+
CheckedTrb++;
//
// If the checked TRB is the link TRB at the end of the transfer ring,
// recircle it to the head of the ring.
//
if (CheckedTrb->Type == TRB_TYPE_LINK) {
- LinkTrb = (LINK_TRB *) CheckedTrb;
- PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64) LinkTrb->PtrHi, 32));
- CheckedTrb = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
+ LinkTrb = (LINK_TRB *)CheckedTrb;
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64)LinkTrb->PtrHi, 32));
+ CheckedTrb = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));
ASSERT (CheckedTrb == Urb->Ring->RingSeg0);
}
}
@@ -1042,16 +1062,16 @@ IsTransferRingTrb (
**/
BOOLEAN
IsAsyncIntTrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN TRB_TEMPLATE *Trb,
- OUT URB **Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN TRB_TEMPLATE *Trb,
+ OUT URB **Urb
)
{
- LIST_ENTRY *Entry;
- LIST_ENTRY *Next;
- URB *CheckedUrb;
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *Next;
+ URB *CheckedUrb;
- EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
+ BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
if (IsTransferRingTrb (Xhc, Trb, CheckedUrb)) {
*Urb = CheckedUrb;
@@ -1062,7 +1082,6 @@ IsAsyncIntTrb (
return FALSE;
}
-
/**
Check the URB's execution result and update the URB's
result accordingly.
@@ -1075,21 +1094,21 @@ IsAsyncIntTrb (
**/
BOOLEAN
XhcCheckUrbResult (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EVT_TRB_TRANSFER *EvtTrb;
- TRB_TEMPLATE *TRBPtr;
- UINTN Index;
- UINT8 TRBType;
- EFI_STATUS Status;
- URB *AsyncUrb;
- URB *CheckedUrb;
- UINT64 XhcDequeue;
- UINT32 High;
- UINT32 Low;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EVT_TRB_TRANSFER *EvtTrb;
+ TRB_TEMPLATE *TRBPtr;
+ UINTN Index;
+ UINT8 TRBType;
+ EFI_STATUS Status;
+ URB *AsyncUrb;
+ URB *CheckedUrb;
+ UINT64 XhcDequeue;
+ UINT32 High;
+ UINT32 Low;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT ((Xhc != NULL) && (Urb != NULL));
@@ -1130,8 +1149,8 @@ XhcCheckUrbResult (
//
// Need convert pci device address to host address
//
- PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
- TRBPtr = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64)EvtTrb->TRBPtrHi, 32));
+ TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));
//
// Update the status of URB including the pending URB, the URB that is currently checked,
@@ -1139,7 +1158,7 @@ XhcCheckUrbResult (
// This way is used to avoid that those completed async transfer events don't get
// handled in time and are flushed by newer coming events.
//
- if (Xhc->PendingUrb != NULL && IsTransferRingTrb (Xhc, TRBPtr, Xhc->PendingUrb)) {
+ if ((Xhc->PendingUrb != NULL) && IsTransferRingTrb (Xhc, TRBPtr, Xhc->PendingUrb)) {
CheckedUrb = Xhc->PendingUrb;
} else if (IsTransferRingTrb (Xhc, TRBPtr, Urb)) {
CheckedUrb = Urb;
@@ -1153,25 +1172,25 @@ XhcCheckUrbResult (
case TRB_COMPLETION_STALL_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_STALL;
CheckedUrb->Finished = TRUE;
- DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_BABBLE_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_BABBLE;
CheckedUrb->Finished = TRUE;
- DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_DATA_BUFFER_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_BUFFER;
CheckedUrb->Finished = TRUE;
- DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_USB_TRANSACTION_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Finished = TRUE;
- DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_STOPPED:
@@ -1187,20 +1206,21 @@ XhcCheckUrbResult (
case TRB_COMPLETION_SHORT_PACKET:
case TRB_COMPLETION_SUCCESS:
if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {
- DEBUG ((EFI_D_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));
+ DEBUG ((DEBUG_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));
}
- TRBType = (UINT8) (TRBPtr->Type);
+ TRBType = (UINT8)(TRBPtr->Type);
if ((TRBType == TRB_TYPE_DATA_STAGE) ||
(TRBType == TRB_TYPE_NORMAL) ||
- (TRBType == TRB_TYPE_ISOCH)) {
- CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);
+ (TRBType == TRB_TYPE_ISOCH))
+ {
+ CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL *)TRBPtr)->Length - EvtTrb->Length);
}
break;
default:
- DEBUG ((EFI_D_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n", EvtTrb->Completecode));
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Finished = TRUE;
goto EXIT;
@@ -1231,9 +1251,9 @@ EXIT:
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access.
//
- Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
- High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
- XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);
+ Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
+ High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
+ XhcDequeue = (UINT64)(LShiftU64 ((UINT64)High, 32) | Low);
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));
@@ -1249,34 +1269,39 @@ EXIT:
return Urb->Finished;
}
-
/**
Execute the transfer by polling the URB. This is a synchronous operation.
- @param Xhc The XHCI Instance.
- @param CmdTransfer The executed URB is for cmd transfer or not.
- @param Urb The URB to execute.
- @param Timeout The time to wait before abort, in millisecond.
+ @param Xhc The XHCI Instance.
+ @param CmdTransfer The executed URB is for cmd transfer or not.
+ @param Urb The URB to execute.
+ @param Timeout The time to wait before abort, in millisecond.
- @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
- @return EFI_TIMEOUT The transfer failed due to time out.
- @return EFI_SUCCESS The transfer finished OK.
+ @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
+ @return EFI_TIMEOUT The transfer failed due to time out.
+ @return EFI_SUCCESS The transfer finished OK.
+ @retval EFI_OUT_OF_RESOURCES Memory for the timer event could not be allocated.
**/
EFI_STATUS
XhcExecTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN BOOLEAN CmdTransfer,
- IN URB *Urb,
- IN UINTN Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN BOOLEAN CmdTransfer,
+ IN URB *Urb,
+ IN UINTN Timeout
)
{
- EFI_STATUS Status;
- UINTN Index;
- UINT64 Loop;
- UINT8 SlotId;
- UINT8 Dci;
- BOOLEAN Finished;
+ EFI_STATUS Status;
+ UINT8 SlotId;
+ UINT8 Dci;
+ BOOLEAN Finished;
+ EFI_EVENT TimeoutEvent;
+ BOOLEAN IndefiniteTimeout;
+
+ Status = EFI_SUCCESS;
+ Finished = FALSE;
+ TimeoutEvent = NULL;
+ IndefiniteTimeout = FALSE;
if (CmdTransfer) {
SlotId = 0;
@@ -1286,31 +1311,62 @@ XhcExecTransfer (
if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
- Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
+
+ Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
}
- Status = EFI_SUCCESS;
- Loop = Timeout * XHC_1_MILLISECOND;
if (Timeout == 0) {
- Loop = 0xFFFFFFFF;
+ IndefiniteTimeout = TRUE;
+ goto RINGDOORBELL;
}
+ Status = gBS->CreateEvent (
+ EVT_TIMER,
+ TPL_CALLBACK,
+ NULL,
+ NULL,
+ &TimeoutEvent
+ );
+
+ if (EFI_ERROR (Status)) {
+ goto DONE;
+ }
+
+ Status = gBS->SetTimer (
+ TimeoutEvent,
+ TimerRelative,
+ EFI_TIMER_PERIOD_MILLISECONDS (Timeout)
+ );
+
+ if (EFI_ERROR (Status)) {
+ goto DONE;
+ }
+
+RINGDOORBELL:
XhcRingDoorBell (Xhc, SlotId, Dci);
- for (Index = 0; Index < Loop; Index++) {
+ do {
Finished = XhcCheckUrbResult (Xhc, Urb);
if (Finished) {
break;
}
- gBS->Stall (XHC_1_MICROSECOND);
- }
- if (Index == Loop) {
+ gBS->Stall (XHC_1_MICROSECOND);
+ } while (IndefiniteTimeout || EFI_ERROR (gBS->CheckEvent (TimeoutEvent)));
+
+DONE:
+ if (EFI_ERROR (Status)) {
+ Urb->Result = EFI_USB_ERR_NOTEXECUTE;
+ } else if (!Finished) {
Urb->Result = EFI_USB_ERR_TIMEOUT;
Status = EFI_TIMEOUT;
} else if (Urb->Result != EFI_USB_NOERROR) {
- Status = EFI_DEVICE_ERROR;
+ Status = EFI_DEVICE_ERROR;
+ }
+
+ if (TimeoutEvent != NULL) {
+ gBS->CloseEvent (TimeoutEvent);
}
return Status;
@@ -1330,9 +1386,9 @@ XhcExecTransfer (
**/
EFI_STATUS
XhciDelAsyncIntTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpNum
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpNum
)
{
LIST_ENTRY *Entry;
@@ -1346,22 +1402,23 @@ XhciDelAsyncIntTransfer (
Urb = NULL;
- EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
+ BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
if ((Urb->Ep.BusAddr == BusAddr) &&
(Urb->Ep.EpAddr == EpNum) &&
- (Urb->Ep.Direction == Direction)) {
+ (Urb->Ep.Direction == Direction))
+ {
//
// Device doesn't finish the IntTransfer until real data comes
// So the TRB should be removed as well.
//
Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));
}
RemoveEntryList (&Urb->UrbList);
- FreePool(Urb->Data);
+ FreePool (Urb->Data);
XhcFreeUrb (Xhc, Urb);
return EFI_SUCCESS;
}
@@ -1378,15 +1435,15 @@ XhciDelAsyncIntTransfer (
**/
VOID
XhciDelAllAsyncIntTransfers (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- LIST_ENTRY *Entry;
- LIST_ENTRY *Next;
- URB *Urb;
- EFI_STATUS Status;
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *Next;
+ URB *Urb;
+ EFI_STATUS Status;
- EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
+ BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
//
@@ -1394,12 +1451,12 @@ XhciDelAllAsyncIntTransfers (
// So the TRB should be removed as well.
//
Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));
}
RemoveEntryList (&Urb->UrbList);
- FreePool(Urb->Data);
+ FreePool (Urb->Data);
XhcFreeUrb (Xhc, Urb);
}
}
@@ -1422,20 +1479,20 @@ XhciDelAllAsyncIntTransfers (
**/
URB *
XhciInsertAsyncIntTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
)
{
- VOID *Data;
- URB *Urb;
+ VOID *Data;
+ URB *Urb;
- Data = AllocateZeroPool(DataLen);
+ Data = AllocateZeroPool (DataLen);
if (Data == NULL) {
DEBUG ((DEBUG_ERROR, "%a: failed to allocate buffer\n", __FUNCTION__));
return NULL;
@@ -1456,7 +1513,7 @@ XhciInsertAsyncIntTransfer (
);
if (Urb == NULL) {
DEBUG ((DEBUG_ERROR, "%a: failed to create URB\n", __FUNCTION__));
- FreePool(Data);
+ FreePool (Data);
return NULL;
}
@@ -1478,19 +1535,20 @@ XhciInsertAsyncIntTransfer (
**/
VOID
XhcUpdateAsyncRequest (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
if (Urb->Result == EFI_USB_NOERROR) {
Status = XhcCreateTransferTrb (Xhc, Urb);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return;
}
+
Status = RingIntTransferDoorBell (Xhc, Urb);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return;
}
}
@@ -1509,16 +1567,16 @@ XhcUpdateAsyncRequest (
**/
EFI_STATUS
XhcFlushAsyncIntMap (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINTN Len;
- VOID *Map;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINTN Len;
+ VOID *Map;
PciIo = Xhc->PciIo;
Len = Urb->DataLen;
@@ -1531,7 +1589,7 @@ XhcFlushAsyncIntMap (
if (Urb->DataMap != NULL) {
Status = PciIo->Unmap (PciIo, Urb->DataMap);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto ON_ERROR;
}
}
@@ -1539,12 +1597,12 @@ XhcFlushAsyncIntMap (
Urb->DataMap = NULL;
Status = PciIo->Map (PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
- if (EFI_ERROR(Status) || (Len != Urb->DataLen)) {
+ if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
goto ON_ERROR;
}
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
- Urb->DataMap = Map;
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
+ Urb->DataMap = Map;
return EFI_SUCCESS;
ON_ERROR:
@@ -1561,24 +1619,24 @@ ON_ERROR:
VOID
EFIAPI
XhcMonitorAsyncRequests (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- USB_XHCI_INSTANCE *Xhc;
- LIST_ENTRY *Entry;
- LIST_ENTRY *Next;
- UINT8 *ProcBuf;
- URB *Urb;
- UINT8 SlotId;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *Next;
+ UINT8 *ProcBuf;
+ URB *Urb;
+ UINT8 SlotId;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = (USB_XHCI_INSTANCE*) Context;
+ Xhc = (USB_XHCI_INSTANCE *)Context;
- EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
+ BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
//
@@ -1604,8 +1662,8 @@ XhcMonitorAsyncRequests (
// bridge to system memory.
//
Status = XhcFlushAsyncIntMap (Xhc, Urb);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
}
//
@@ -1619,7 +1677,7 @@ XhcMonitorAsyncRequests (
// Make sure the data received from HW is no more than expected.
//
if (Urb->Completed <= Urb->DataLen) {
- ProcBuf = AllocateZeroPool(Urb->Completed);
+ ProcBuf = AllocateZeroPool (Urb->Completed);
}
if (ProcBuf == NULL) {
@@ -1627,7 +1685,7 @@ XhcMonitorAsyncRequests (
continue;
}
- CopyMem(ProcBuf, Urb->Data, Urb->Completed);
+ CopyMem (ProcBuf, Urb->Data, Urb->Completed);
}
//
@@ -1646,12 +1704,12 @@ XhcMonitorAsyncRequests (
// his callback. Some drivers may has a lower TPL restriction.
//
gBS->RestoreTPL (OldTpl);
- (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
+ (Urb->Callback)(ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
OldTpl = gBS->RaiseTPL (XHC_TPL);
}
if (ProcBuf != NULL) {
- gBS->FreePool(ProcBuf);
+ gBS->FreePool (ProcBuf);
}
XhcUpdateAsyncRequest (Xhc, Urb);
@@ -1674,18 +1732,20 @@ XhcMonitorAsyncRequests (
EFI_STATUS
EFIAPI
XhcPollPortStatusChange (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT8 Port,
- IN EFI_USB_PORT_STATUS *PortState
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT8 Port,
+ IN EFI_USB_PORT_STATUS *PortState
)
{
- EFI_STATUS Status;
- UINT8 Speed;
- UINT8 SlotId;
- USB_DEV_ROUTE RouteChart;
+ EFI_STATUS Status;
+ UINT8 Speed;
+ UINT8 SlotId;
+ UINT8 Retries;
+ USB_DEV_ROUTE RouteChart;
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
+ Retries = XHC_INIT_DEVICE_SLOT_RETRIES;
if ((PortState->PortChangeStatus & (USB_PORT_STAT_C_CONNECTION | USB_PORT_STAT_C_ENABLE | USB_PORT_STAT_C_OVERCURRENT | USB_PORT_STAT_C_RESET)) == 0) {
return EFI_SUCCESS;
@@ -1696,13 +1756,14 @@ XhcPollPortStatusChange (
RouteChart.Route.RootPortNum = Port + 1;
RouteChart.Route.TierNum = 1;
} else {
- if(Port < 14) {
+ if (Port < 14) {
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));
} else {
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));
}
- RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
- RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
+
+ RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
+ RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
}
SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
@@ -1715,7 +1776,8 @@ XhcPollPortStatusChange (
}
if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&
- ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {
+ ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0))
+ {
//
// Has a device attached, Identify device speed after port is enabled.
//
@@ -1727,23 +1789,34 @@ XhcPollPortStatusChange (
} else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {
Speed = EFI_USB_SPEED_SUPER;
}
- //
- // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
- //
- SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
- if ((SlotId == 0) && ((PortState->PortChangeStatus & USB_PORT_STAT_C_RESET) != 0)) {
- if (Xhc->HcCParams.Data.Csz == 0) {
- Status = XhcInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);
- } else {
- Status = XhcInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);
+
+ do {
+ //
+ // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
+ //
+ SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
+ if ((SlotId == 0) && ((PortState->PortChangeStatus & USB_PORT_STAT_C_RESET) != 0)) {
+ if (Xhc->HcCParams.Data.Csz == 0) {
+ Status = XhcInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);
+ } else {
+ Status = XhcInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);
+ }
}
- }
+
+ //
+ // According to the xHCI specification (section 4.6.5), "a USB Transaction
+ // Error Completion Code for an Address Device Command may be due to a Stall
+ // response from a device. Software should issue a Disable Slot Command for
+ // the Device Slot then an Enable Slot Command to recover from this error."
+ // Therefore, retry the device slot initialization if it fails due to a
+ // device error.
+ //
+ } while ((Status == EFI_DEVICE_ERROR) && (Retries-- != 0));
}
return Status;
}
-
/**
Calculate the device context index by endpoint address and direction.
@@ -1755,19 +1828,20 @@ XhcPollPortStatusChange (
**/
UINT8
XhcEndpointToDci (
- IN UINT8 EpAddr,
- IN UINT8 Direction
+ IN UINT8 EpAddr,
+ IN UINT8 Direction
)
{
- UINT8 Index;
+ UINT8 Index;
if (EpAddr == 0) {
return 1;
} else {
- Index = (UINT8) (2 * EpAddr);
+ Index = (UINT8)(2 * EpAddr);
if (Direction == EfiUsbDataIn) {
Index += 1;
}
+
return Index;
}
}
@@ -1793,7 +1867,8 @@ XhcBusDevAddrToSlotId (
for (Index = 0; Index < 255; Index++) {
if (Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
- (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {
+ (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr))
+ {
break;
}
}
@@ -1826,7 +1901,8 @@ XhcRouteStringToSlotId (
for (Index = 0; Index < 255; Index++) {
if (Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
- (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword))
+ {
break;
}
}
@@ -1850,12 +1926,12 @@ XhcRouteStringToSlotId (
EFI_STATUS
EFIAPI
XhcSyncEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN EVENT_RING *EvtRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN EVENT_RING *EvtRing
)
{
- UINTN Index;
- TRB_TEMPLATE *EvtTrb1;
+ UINTN Index;
+ TRB_TEMPLATE *EvtTrb1;
ASSERT (EvtRing != NULL);
@@ -1872,8 +1948,8 @@ XhcSyncEventRing (
EvtTrb1++;
- if ((UINTN)EvtTrb1 >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
- EvtTrb1 = EvtRing->EventRingSeg0;
+ if ((UINTN)EvtTrb1 >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
+ EvtTrb1 = EvtRing->EventRingSeg0;
EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;
}
}
@@ -1899,12 +1975,12 @@ XhcSyncEventRing (
EFI_STATUS
EFIAPI
XhcSyncTrsRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN TRANSFER_RING *TrsRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN TRANSFER_RING *TrsRing
)
{
- UINTN Index;
- TRB_TEMPLATE *TrsTrb;
+ UINTN Index;
+ TRB_TEMPLATE *TrsTrb;
ASSERT (TrsRing != NULL);
//
@@ -1917,18 +1993,19 @@ XhcSyncTrsRing (
if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
break;
}
+
TrsTrb++;
- if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
- ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);
+ if ((UINT8)TrsTrb->Type == TRB_TYPE_LINK) {
+ ASSERT (((LINK_TRB *)TrsTrb)->TC != 0);
//
// set cycle bit in Link TRB as normal
//
- ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
+ ((LINK_TRB *)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
//
// Toggle PCS maintained by software
//
TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
- TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address
+ TrsTrb = (TRB_TEMPLATE *)TrsRing->RingSeg0; // Use host address
}
}
@@ -1965,9 +2042,9 @@ XhcSyncTrsRing (
EFI_STATUS
EFIAPI
XhcCheckNewEvent (
- IN USB_XHCI_INSTANCE *Xhc,
- IN EVENT_RING *EvtRing,
- OUT TRB_TEMPLATE **NewEvtTrb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN EVENT_RING *EvtRing,
+ OUT TRB_TEMPLATE **NewEvtTrb
)
{
ASSERT (EvtRing != NULL);
@@ -1982,7 +2059,7 @@ XhcCheckNewEvent (
//
// If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
//
- if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
+ if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
}
@@ -2002,9 +2079,9 @@ XhcCheckNewEvent (
EFI_STATUS
EFIAPI
XhcRingDoorBell (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
)
{
if (SlotId == 0) {
@@ -2027,12 +2104,12 @@ XhcRingDoorBell (
**/
EFI_STATUS
RingIntTransferDoorBell (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- UINT8 SlotId;
- UINT8 Dci;
+ UINT8 SlotId;
+ UINT8 Dci;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
@@ -2055,11 +2132,11 @@ RingIntTransferDoorBell (
EFI_STATUS
EFIAPI
XhcInitializeDeviceSlot (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
)
{
EFI_STATUS Status;
@@ -2080,17 +2157,18 @@ XhcInitializeDeviceSlot (
CmdTrb.Type = TRB_TYPE_EN_SLOT;
Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
+
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
- DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
+ DEBUG ((DEBUG_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8)EvtTrb->SlotId;
ASSERT (SlotId != 0);
@@ -2106,10 +2184,10 @@ XhcInitializeDeviceSlot (
//
InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));
ASSERT (InputContext != NULL);
- ASSERT (((UINTN) InputContext & 0x3F) == 0);
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);
ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;
//
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
@@ -2130,14 +2208,15 @@ XhcInitializeDeviceSlot (
//
// The device is behind of hub device.
//
- ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);
+ ParentSlotId = XhcRouteStringToSlotId (Xhc, ParentRouteChart);
ASSERT (ParentSlotId != 0);
//
- //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
+ // if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
//
ParentDeviceContext = (DEVICE_CONTEXT *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))
+ {
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
//
// Full/Low device attached to High speed hub port that isolates the high speed signaling
@@ -2164,9 +2243,9 @@ XhcInitializeDeviceSlot (
//
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
//
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
//
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
//
@@ -2179,6 +2258,7 @@ XhcInitializeDeviceSlot (
} else {
InputContext->EP[0].MaxPacketSize = 8;
}
+
//
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
// 1KB, and Bulk and Isoch endpoints 3KB.
@@ -2206,7 +2286,7 @@ XhcInitializeDeviceSlot (
//
OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));
ASSERT (OutputContext != NULL);
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
@@ -2218,7 +2298,7 @@ XhcInitializeDeviceSlot (
//
// Fill DCBAA with PCI device address
//
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;
//
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
@@ -2229,22 +2309,25 @@ XhcInitializeDeviceSlot (
//
gBS->Stall (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1;
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (!EFI_ERROR(Status)) {
- DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;
- DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (!EFI_ERROR (Status)) {
+ DeviceAddress = (UINT8)((DEVICE_CONTEXT *)OutputContext)->Slot.DeviceAddress;
+ DEBUG ((DEBUG_INFO, " Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
+ } else {
+ DEBUG ((DEBUG_ERROR, " Slot %d address not assigned successfully. Status = %r\n", SlotId, Status));
+ XhcDisableSlotCmd (Xhc, SlotId);
}
return Status;
@@ -2265,11 +2348,11 @@ XhcInitializeDeviceSlot (
EFI_STATUS
EFIAPI
XhcInitializeDeviceSlot64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
)
{
EFI_STATUS Status;
@@ -2290,17 +2373,18 @@ XhcInitializeDeviceSlot64 (
CmdTrb.Type = TRB_TYPE_EN_SLOT;
Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
+
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
- DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
+ DEBUG ((DEBUG_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8)EvtTrb->SlotId;
ASSERT (SlotId != 0);
@@ -2316,10 +2400,10 @@ XhcInitializeDeviceSlot64 (
//
InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));
ASSERT (InputContext != NULL);
- ASSERT (((UINTN) InputContext & 0x3F) == 0);
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);
ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;
//
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
@@ -2340,14 +2424,15 @@ XhcInitializeDeviceSlot64 (
//
// The device is behind of hub device.
//
- ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);
+ ParentSlotId = XhcRouteStringToSlotId (Xhc, ParentRouteChart);
ASSERT (ParentSlotId != 0);
//
- //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
+ // if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
//
ParentDeviceContext = (DEVICE_CONTEXT_64 *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))
+ {
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
//
// Full/Low device attached to High speed hub port that isolates the high speed signaling
@@ -2374,9 +2459,9 @@ XhcInitializeDeviceSlot64 (
//
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
//
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
//
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
//
@@ -2389,6 +2474,7 @@ XhcInitializeDeviceSlot64 (
} else {
InputContext->EP[0].MaxPacketSize = 8;
}
+
//
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
// 1KB, and Bulk and Isoch endpoints 3KB.
@@ -2416,7 +2502,7 @@ XhcInitializeDeviceSlot64 (
//
OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));
ASSERT (OutputContext != NULL);
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
@@ -2428,7 +2514,7 @@ XhcInitializeDeviceSlot64 (
//
// Fill DCBAA with PCI device address
//
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;
//
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
@@ -2439,27 +2525,30 @@ XhcInitializeDeviceSlot64 (
//
gBS->Stall (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1;
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (!EFI_ERROR(Status)) {
- DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;
- DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (!EFI_ERROR (Status)) {
+ DeviceAddress = (UINT8)((DEVICE_CONTEXT_64 *)OutputContext)->Slot.DeviceAddress;
+ DEBUG ((DEBUG_INFO, " Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
+ } else {
+ DEBUG ((DEBUG_ERROR, " Slot %d address not assigned successfully. Status = %r\n", SlotId, Status));
+ XhcDisableSlotCmd64 (Xhc, SlotId);
}
+
return Status;
}
-
/**
Disable the specified device slot.
@@ -2472,8 +2561,8 @@ XhcInitializeDeviceSlot64 (
EFI_STATUS
EFIAPI
XhcDisableSlotCmd (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId
)
{
EFI_STATUS Status;
@@ -2489,14 +2578,15 @@ XhcDisableSlotCmd (
for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled ||
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))
+ {
continue;
}
Status = XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
Xhc->UsbDevContext[Index + 1].SlotId = 0;
}
}
@@ -2504,22 +2594,23 @@ XhcDisableSlotCmd (
//
// Construct the disable slot command
//
- DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
+ DEBUG ((DEBUG_INFO, "Disable device slot %d!\n", SlotId));
ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
CmdTrbDisSlot.CycleBit = 1;
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
CmdTrbDisSlot.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
+
//
// Free the slot's device context entry
//
@@ -2534,19 +2625,20 @@ XhcDisableSlotCmd (
if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
- FreePool(Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
+
+ FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
}
}
for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {
- FreePool(Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
+ FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
}
}
if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {
- FreePool(Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);
+ FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);
}
if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
@@ -2556,6 +2648,7 @@ XhcDisableSlotCmd (
if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));
}
+
//
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
@@ -2579,8 +2672,8 @@ XhcDisableSlotCmd (
EFI_STATUS
EFIAPI
XhcDisableSlotCmd64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId
)
{
EFI_STATUS Status;
@@ -2596,14 +2689,15 @@ XhcDisableSlotCmd64 (
for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled ||
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))
+ {
continue;
}
Status = XhcDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
Xhc->UsbDevContext[Index + 1].SlotId = 0;
}
}
@@ -2611,22 +2705,23 @@ XhcDisableSlotCmd64 (
//
// Construct the disable slot command
//
- DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
+ DEBUG ((DEBUG_INFO, "Disable device slot %d!\n", SlotId));
ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
CmdTrbDisSlot.CycleBit = 1;
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
CmdTrbDisSlot.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
+
//
// Free the slot's device context entry
//
@@ -2641,19 +2736,20 @@ XhcDisableSlotCmd64 (
if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
- FreePool(Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
+
+ FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
}
}
for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {
- FreePool(Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
+ FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
}
}
if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {
- FreePool(Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);
+ FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);
}
if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
@@ -2661,8 +2757,9 @@ XhcDisableSlotCmd64 (
}
if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
- UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
+ UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
}
+
//
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
@@ -2689,23 +2786,23 @@ XhcDisableSlotCmd64 (
UINT8
EFIAPI
XhcInitializeEndpointContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN INPUT_CONTEXT *InputContext,
- IN USB_INTERFACE_DESCRIPTOR *IfDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN INPUT_CONTEXT *InputContext,
+ IN USB_INTERFACE_DESCRIPTOR *IfDesc
)
{
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- UINT8 Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINT8 Interval;
- TRANSFER_RING *EndpointTransferRing;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ UINT8 Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINT8 Interval;
+ TRANSFER_RING *EndpointTransferRing;
MaxDci = 0;
@@ -2755,14 +2852,16 @@ XhcInitializeEndpointContext (
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
- DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created BULK ring [%p~%p)\n",
- EpDesc->EndpointAddress,
- EndpointTransferRing->RingSeg0,
- (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
- ));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((
+ DEBUG_INFO,
+ "Endpoint[%x]: Created BULK ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
break;
@@ -2774,6 +2873,7 @@ XhcInitializeEndpointContext (
InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
}
+
//
// Get the bInterval from descriptor and init the the interval field of endpoint context.
// Refer to XHCI 1.1 spec section 6.2.3.6.
@@ -2791,7 +2891,7 @@ XhcInitializeEndpointContext (
//
// Do not support isochronous transfer now.
//
- DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
+ DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
case USB_ENDPOINT_INTERRUPT:
@@ -2802,6 +2902,7 @@ XhcInitializeEndpointContext (
InputContext->EP[Dci-1].CErr = 3;
InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
}
+
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
//
@@ -2813,7 +2914,7 @@ XhcInitializeEndpointContext (
// Calculate through the bInterval field of Endpoint descriptor.
//
ASSERT (Interval != 0);
- InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;
} else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
Interval = EpDesc->Interval;
ASSERT (Interval >= 1 && Interval <= 16);
@@ -2828,24 +2929,27 @@ XhcInitializeEndpointContext (
}
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
- DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created INT ring [%p~%p)\n",
- EpDesc->EndpointAddress,
- EndpointTransferRing->RingSeg0,
- (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
- ));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((
+ DEBUG_INFO,
+ "Endpoint[%x]: Created INT ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
+
break;
case USB_ENDPOINT_CONTROL:
//
// Do not support control transfer now.
//
- DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
+ DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
default:
- DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
+ DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
}
@@ -2855,8 +2959,8 @@ XhcInitializeEndpointContext (
((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
- PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
- PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
+ PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
@@ -2881,23 +2985,23 @@ XhcInitializeEndpointContext (
UINT8
EFIAPI
XhcInitializeEndpointContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN INPUT_CONTEXT_64 *InputContext,
- IN USB_INTERFACE_DESCRIPTOR *IfDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN INPUT_CONTEXT_64 *InputContext,
+ IN USB_INTERFACE_DESCRIPTOR *IfDesc
)
{
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- UINT8 Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINT8 Interval;
- TRANSFER_RING *EndpointTransferRing;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ UINT8 Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINT8 Interval;
+ TRANSFER_RING *EndpointTransferRing;
MaxDci = 0;
@@ -2947,14 +3051,16 @@ XhcInitializeEndpointContext64 (
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
- DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created BULK ring [%p~%p)\n",
- EpDesc->EndpointAddress,
- EndpointTransferRing->RingSeg0,
- (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
- ));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((
+ DEBUG_INFO,
+ "Endpoint64[%x]: Created BULK ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
break;
@@ -2966,6 +3072,7 @@ XhcInitializeEndpointContext64 (
InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
}
+
//
// Get the bInterval from descriptor and init the the interval field of endpoint context.
// Refer to XHCI 1.1 spec section 6.2.3.6.
@@ -2983,7 +3090,7 @@ XhcInitializeEndpointContext64 (
//
// Do not support isochronous transfer now.
//
- DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
+ DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
case USB_ENDPOINT_INTERRUPT:
@@ -2994,6 +3101,7 @@ XhcInitializeEndpointContext64 (
InputContext->EP[Dci-1].CErr = 3;
InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
}
+
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
//
@@ -3005,7 +3113,7 @@ XhcInitializeEndpointContext64 (
// Calculate through the bInterval field of Endpoint descriptor.
//
ASSERT (Interval != 0);
- InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;
} else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
Interval = EpDesc->Interval;
ASSERT (Interval >= 1 && Interval <= 16);
@@ -3020,24 +3128,27 @@ XhcInitializeEndpointContext64 (
}
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
- DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created INT ring [%p~%p)\n",
- EpDesc->EndpointAddress,
- EndpointTransferRing->RingSeg0,
- (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
- ));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((
+ DEBUG_INFO,
+ "Endpoint64[%x]: Created INT ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
+
break;
case USB_ENDPOINT_CONTROL:
//
// Do not support control transfer now.
//
- DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
+ DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
default:
- DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
+ DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
continue;
}
@@ -3047,8 +3158,8 @@ XhcInitializeEndpointContext64 (
((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
- PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
- PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
+ PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
@@ -3072,30 +3183,31 @@ XhcInitializeEndpointContext64 (
EFI_STATUS
EFIAPI
XhcSetConfigCmd (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- UINT8 Index;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ UINT8 Index;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
INPUT_CONTEXT *InputContext;
DEVICE_CONTEXT *OutputContext;
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+
//
// 4.6.6 Configure Endpoint
//
InputContext = Xhc->UsbDevContext[SlotId].InputContext;
OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
- CopyMem(&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));
+ CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));
ASSERT (ConfigDesc != NULL);
@@ -3126,21 +3238,21 @@ XhcSetConfigCmd (
// configure endpoint
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));
+ DEBUG ((DEBUG_INFO, "Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
} else {
Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;
}
@@ -3162,30 +3274,31 @@ XhcSetConfigCmd (
EFI_STATUS
EFIAPI
XhcSetConfigCmd64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- UINT8 Index;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ UINT8 Index;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
INPUT_CONTEXT_64 *InputContext;
DEVICE_CONTEXT_64 *OutputContext;
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+
//
// 4.6.6 Configure Endpoint
//
InputContext = Xhc->UsbDevContext[SlotId].InputContext;
OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
- CopyMem(&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));
+ CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));
ASSERT (ConfigDesc != NULL);
@@ -3216,21 +3329,21 @@ XhcSetConfigCmd64 (
// configure endpoint
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));
+ DEBUG ((DEBUG_INFO, "Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
} else {
Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;
}
@@ -3253,17 +3366,17 @@ XhcSetConfigCmd64 (
EFI_STATUS
EFIAPI
XhcStopEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *PendingUrb OPTIONAL
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *PendingUrb OPTIONAL
)
{
- EFI_STATUS Status;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
+ EFI_STATUS Status;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
- DEBUG ((EFI_D_INFO, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
+ DEBUG ((DEBUG_INFO, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
//
// When XhcCheckUrbResult waits for the Stop_Endpoint completion, it also checks
@@ -3296,14 +3409,14 @@ XhcStopEndpoint (
CmdTrbStopED.Type = TRB_TYPE_STOP_ENDPOINT;
CmdTrbStopED.EDID = Dci;
CmdTrbStopED.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbStopED,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbStopED,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
}
Xhc->PendingUrb = NULL;
@@ -3325,16 +3438,16 @@ XhcStopEndpoint (
EFI_STATUS
EFIAPI
XhcResetEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
)
{
EFI_STATUS Status;
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
CMD_TRB_RESET_ENDPOINT CmdTrbResetED;
- DEBUG ((EFI_D_INFO, "XhcResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
+ DEBUG ((DEBUG_INFO, "XhcResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
//
// Send stop endpoint command to transit Endpoint from running to stop state
@@ -3344,14 +3457,14 @@ XhcResetEndpoint (
CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;
CmdTrbResetED.EDID = Dci;
CmdTrbResetED.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbResetED,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
}
return Status;
@@ -3373,10 +3486,10 @@ XhcResetEndpoint (
EFI_STATUS
EFIAPI
XhcSetTrDequeuePointer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *Urb
)
{
EFI_STATUS Status;
@@ -3384,27 +3497,27 @@ XhcSetTrDequeuePointer (
CMD_SET_TR_DEQ_POINTER CmdSetTRDeq;
EFI_PHYSICAL_ADDRESS PhyAddr;
- DEBUG ((EFI_D_INFO, "XhcSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));
+ DEBUG ((DEBUG_INFO, "XhcSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));
//
// Send stop endpoint command to transit Endpoint from running to stop state
//
ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdSetTRDeq.CycleBit = 1;
CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;
CmdSetTRDeq.Endpoint = Dci;
CmdSetTRDeq.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdSetTRDeq,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
}
return Status;
@@ -3425,26 +3538,26 @@ XhcSetTrDequeuePointer (
EFI_STATUS
EFIAPI
XhcSetInterface (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
- IN EFI_USB_DEVICE_REQUEST *Request
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
+ IN EFI_USB_DEVICE_REQUEST *Request
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDescActive;
- USB_INTERFACE_DESCRIPTOR *IfDescSet;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- UINT8 Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *RingSeg;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDescActive;
+ USB_INTERFACE_DESCRIPTOR *IfDescSet;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ UINT8 Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *RingSeg;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
INPUT_CONTEXT *InputContext;
@@ -3466,25 +3579,25 @@ XhcSetInterface (
// So the default Drop Context and Add Context flags can be '0' to cover 1).
//
ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
- CopyMem(&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));
+ CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));
ASSERT (ConfigDesc != NULL);
MaxDci = 0;
IfDescActive = NULL;
- IfDescSet = NULL;
+ IfDescSet = NULL;
IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
- while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {
+ while ((UINTN)IfDesc < ((UINTN)ConfigDesc + ConfigDesc->TotalLength)) {
if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {
- if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {
+ if (IfDesc->InterfaceNumber == (UINT8)Request->Index) {
if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {
//
// Find out the active interface descriptor.
//
IfDescActive = IfDesc;
- } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {
+ } else if (IfDesc->AlternateSetting == (UINT8)Request->Value) {
//
// Find out the interface descriptor to set.
//
@@ -3492,6 +3605,7 @@ XhcSetInterface (
}
}
}
+
IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
@@ -3510,8 +3624,8 @@ XhcSetInterface (
//
if ((IfDescActive != NULL) && (IfDescSet != NULL)) {
- NumEp = IfDescActive->NumEndpoints;
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);
+ NumEp = IfDescActive->NumEndpoints;
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDescActive + 1);
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
@@ -3522,22 +3636,24 @@ XhcSetInterface (
continue;
}
- EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
- Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
Dci = XhcEndpointToDci (EpAddr, Direction);
ASSERT (Dci < 32);
if (Dci > MaxDci) {
MaxDci = Dci;
}
+
//
// XHCI 4.3.6 - Setting Alternate Interfaces
// 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
//
Status = XhcStopEndpoint (Xhc, SlotId, Dci, NULL);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
+
//
// XHCI 4.3.6 - Setting Alternate Interfaces
// 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
@@ -3547,7 +3663,8 @@ XhcSetInterface (
if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
- FreePool(Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
+
+ FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;
}
@@ -3586,26 +3703,26 @@ XhcSetInterface (
// 5) Issue and successfully complete a Configure Endpoint Command.
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- DEBUG ((EFI_D_INFO, "SetInterface: Configure Endpoint\n"));
+ DEBUG ((DEBUG_INFO, "SetInterface: Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "SetInterface: Config Endpoint Failed, Status = %r\n", Status));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "SetInterface: Config Endpoint Failed, Status = %r\n", Status));
} else {
//
// Update the active AlternateSetting.
//
- Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;
+ Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8)Request->Index] = (UINT8)Request->Value;
}
}
@@ -3627,26 +3744,26 @@ XhcSetInterface (
EFI_STATUS
EFIAPI
XhcSetInterface64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
- IN EFI_USB_DEVICE_REQUEST *Request
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
+ IN EFI_USB_DEVICE_REQUEST *Request
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDescActive;
- USB_INTERFACE_DESCRIPTOR *IfDescSet;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- UINT8 Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *RingSeg;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDescActive;
+ USB_INTERFACE_DESCRIPTOR *IfDescSet;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ UINT8 Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *RingSeg;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
INPUT_CONTEXT_64 *InputContext;
@@ -3668,25 +3785,25 @@ XhcSetInterface64 (
// So the default Drop Context and Add Context flags can be '0' to cover 1).
//
ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
- CopyMem(&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));
+ CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));
ASSERT (ConfigDesc != NULL);
MaxDci = 0;
IfDescActive = NULL;
- IfDescSet = NULL;
+ IfDescSet = NULL;
IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
- while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {
+ while ((UINTN)IfDesc < ((UINTN)ConfigDesc + ConfigDesc->TotalLength)) {
if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {
- if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {
+ if (IfDesc->InterfaceNumber == (UINT8)Request->Index) {
if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {
//
// Find out the active interface descriptor.
//
IfDescActive = IfDesc;
- } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {
+ } else if (IfDesc->AlternateSetting == (UINT8)Request->Value) {
//
// Find out the interface descriptor to set.
//
@@ -3694,6 +3811,7 @@ XhcSetInterface64 (
}
}
}
+
IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
@@ -3712,8 +3830,8 @@ XhcSetInterface64 (
//
if ((IfDescActive != NULL) && (IfDescSet != NULL)) {
- NumEp = IfDescActive->NumEndpoints;
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);
+ NumEp = IfDescActive->NumEndpoints;
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDescActive + 1);
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
@@ -3724,22 +3842,24 @@ XhcSetInterface64 (
continue;
}
- EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
- Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
Dci = XhcEndpointToDci (EpAddr, Direction);
ASSERT (Dci < 32);
if (Dci > MaxDci) {
MaxDci = Dci;
}
+
//
// XHCI 4.3.6 - Setting Alternate Interfaces
// 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
//
Status = XhcStopEndpoint (Xhc, SlotId, Dci, NULL);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
+
//
// XHCI 4.3.6 - Setting Alternate Interfaces
// 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
@@ -3749,7 +3869,8 @@ XhcSetInterface64 (
if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
- FreePool(Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
+
+ FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;
}
@@ -3788,26 +3909,26 @@ XhcSetInterface64 (
// 5) Issue and successfully complete a Configure Endpoint Command.
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- DEBUG ((EFI_D_INFO, "SetInterface64: Configure Endpoint\n"));
+ DEBUG ((DEBUG_INFO, "SetInterface64: Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status));
} else {
//
// Update the active AlternateSetting.
//
- Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;
+ Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8)Request->Index] = (UINT8)Request->Value;
}
}
@@ -3827,9 +3948,9 @@ XhcSetInterface64 (
EFI_STATUS
EFIAPI
XhcEvaluateContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
)
{
EFI_STATUS Status;
@@ -3850,22 +3971,23 @@ XhcEvaluateContext (
InputContext->EP[0].MaxPacketSize = MaxPacketSize;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1;
CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- DEBUG ((EFI_D_INFO, "Evaluate context\n"));
+ DEBUG ((DEBUG_INFO, "Evaluate context\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -3882,9 +4004,9 @@ XhcEvaluateContext (
EFI_STATUS
EFIAPI
XhcEvaluateContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
)
{
EFI_STATUS Status;
@@ -3905,26 +4027,26 @@ XhcEvaluateContext64 (
InputContext->EP[0].MaxPacketSize = MaxPacketSize;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1;
CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- DEBUG ((EFI_D_INFO, "Evaluate context\n"));
+ DEBUG ((DEBUG_INFO, "Evaluate context\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
}
+
return Status;
}
-
/**
Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
@@ -3939,11 +4061,11 @@ XhcEvaluateContext64 (
**/
EFI_STATUS
XhcConfigHubContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
)
{
EFI_STATUS Status;
@@ -3967,29 +4089,30 @@ XhcConfigHubContext (
//
// Copy the slot context from OutputContext to Input context
//
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));
InputContext->Slot.Hub = 1;
InputContext->Slot.PortNum = PortNum;
InputContext->Slot.TTT = TTT;
InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
+ DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));
Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -4007,11 +4130,11 @@ XhcConfigHubContext (
**/
EFI_STATUS
XhcConfigHubContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
)
{
EFI_STATUS Status;
@@ -4035,30 +4158,29 @@ XhcConfigHubContext64 (
//
// Copy the slot context from OutputContext to Input context
//
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));
InputContext->Slot.Hub = 1;
InputContext->Slot.PortNum = PortNum;
InputContext->Slot.TTT = TTT;
InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
+ DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));
Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
}
+
return Status;
}
-
-
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
index 2f1899502..7c85f7993 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
@@ -10,72 +10,73 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_XHCI_SCHED_H_
#define _EFI_XHCI_SCHED_H_
-#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
+#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
+#define XHC_INIT_DEVICE_SLOT_RETRIES 1
//
// Transfer types, used in URB to identify the transfer type
//
-#define XHC_CTRL_TRANSFER 0x01
-#define XHC_BULK_TRANSFER 0x02
-#define XHC_INT_TRANSFER_SYNC 0x04
-#define XHC_INT_TRANSFER_ASYNC 0x08
-#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
+#define XHC_CTRL_TRANSFER 0x01
+#define XHC_BULK_TRANSFER 0x02
+#define XHC_INT_TRANSFER_SYNC 0x04
+#define XHC_INT_TRANSFER_ASYNC 0x08
+#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
//
// 6.4.6 TRB Types
//
-#define TRB_TYPE_NORMAL 1
-#define TRB_TYPE_SETUP_STAGE 2
-#define TRB_TYPE_DATA_STAGE 3
-#define TRB_TYPE_STATUS_STAGE 4
-#define TRB_TYPE_ISOCH 5
-#define TRB_TYPE_LINK 6
-#define TRB_TYPE_EVENT_DATA 7
-#define TRB_TYPE_NO_OP 8
-#define TRB_TYPE_EN_SLOT 9
-#define TRB_TYPE_DIS_SLOT 10
-#define TRB_TYPE_ADDRESS_DEV 11
-#define TRB_TYPE_CON_ENDPOINT 12
-#define TRB_TYPE_EVALU_CONTXT 13
-#define TRB_TYPE_RESET_ENDPOINT 14
-#define TRB_TYPE_STOP_ENDPOINT 15
-#define TRB_TYPE_SET_TR_DEQUE 16
-#define TRB_TYPE_RESET_DEV 17
-#define TRB_TYPE_GET_PORT_BANW 21
-#define TRB_TYPE_FORCE_HEADER 22
-#define TRB_TYPE_NO_OP_COMMAND 23
-#define TRB_TYPE_TRANS_EVENT 32
-#define TRB_TYPE_COMMAND_COMPLT_EVENT 33
-#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
-#define TRB_TYPE_HOST_CONTROLLER_EVENT 37
-#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
-#define TRB_TYPE_MFINDEX_WRAP_EVENT 39
+#define TRB_TYPE_NORMAL 1
+#define TRB_TYPE_SETUP_STAGE 2
+#define TRB_TYPE_DATA_STAGE 3
+#define TRB_TYPE_STATUS_STAGE 4
+#define TRB_TYPE_ISOCH 5
+#define TRB_TYPE_LINK 6
+#define TRB_TYPE_EVENT_DATA 7
+#define TRB_TYPE_NO_OP 8
+#define TRB_TYPE_EN_SLOT 9
+#define TRB_TYPE_DIS_SLOT 10
+#define TRB_TYPE_ADDRESS_DEV 11
+#define TRB_TYPE_CON_ENDPOINT 12
+#define TRB_TYPE_EVALU_CONTXT 13
+#define TRB_TYPE_RESET_ENDPOINT 14
+#define TRB_TYPE_STOP_ENDPOINT 15
+#define TRB_TYPE_SET_TR_DEQUE 16
+#define TRB_TYPE_RESET_DEV 17
+#define TRB_TYPE_GET_PORT_BANW 21
+#define TRB_TYPE_FORCE_HEADER 22
+#define TRB_TYPE_NO_OP_COMMAND 23
+#define TRB_TYPE_TRANS_EVENT 32
+#define TRB_TYPE_COMMAND_COMPLT_EVENT 33
+#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
+#define TRB_TYPE_HOST_CONTROLLER_EVENT 37
+#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
+#define TRB_TYPE_MFINDEX_WRAP_EVENT 39
//
// Endpoint Type (EP Type).
//
-#define ED_NOT_VALID 0
-#define ED_ISOCH_OUT 1
-#define ED_BULK_OUT 2
-#define ED_INTERRUPT_OUT 3
-#define ED_CONTROL_BIDIR 4
-#define ED_ISOCH_IN 5
-#define ED_BULK_IN 6
-#define ED_INTERRUPT_IN 7
+#define ED_NOT_VALID 0
+#define ED_ISOCH_OUT 1
+#define ED_BULK_OUT 2
+#define ED_INTERRUPT_OUT 3
+#define ED_CONTROL_BIDIR 4
+#define ED_ISOCH_IN 5
+#define ED_BULK_IN 6
+#define ED_INTERRUPT_IN 7
//
// 6.4.5 TRB Completion Codes
//
-#define TRB_COMPLETION_INVALID 0
-#define TRB_COMPLETION_SUCCESS 1
-#define TRB_COMPLETION_DATA_BUFFER_ERROR 2
-#define TRB_COMPLETION_BABBLE_ERROR 3
-#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
-#define TRB_COMPLETION_TRB_ERROR 5
-#define TRB_COMPLETION_STALL_ERROR 6
-#define TRB_COMPLETION_SHORT_PACKET 13
-#define TRB_COMPLETION_STOPPED 26
-#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27
+#define TRB_COMPLETION_INVALID 0
+#define TRB_COMPLETION_SUCCESS 1
+#define TRB_COMPLETION_DATA_BUFFER_ERROR 2
+#define TRB_COMPLETION_BABBLE_ERROR 3
+#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
+#define TRB_COMPLETION_TRB_ERROR 5
+#define TRB_COMPLETION_STALL_ERROR 6
+#define TRB_COMPLETION_SHORT_PACKET 13
+#define TRB_COMPLETION_STOPPED 26
+#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27
//
// The topology string used to present usb device location
@@ -84,15 +85,15 @@ typedef struct _USB_DEV_TOPOLOGY {
//
// The tier concatenation of down stream port.
//
- UINT32 RouteString:20;
+ UINT32 RouteString : 20;
//
// The root port number of the chain.
//
- UINT32 RootPortNum:8;
+ UINT32 RootPortNum : 8;
//
// The Tier the device reside.
//
- UINT32 TierNum:4;
+ UINT32 TierNum : 4;
} USB_DEV_TOPOLOGY;
//
@@ -125,33 +126,33 @@ typedef struct _USB_ENDPOINT {
// TRB Template
//
typedef struct _TRB_TEMPLATE {
- UINT32 Parameter1;
+ UINT32 Parameter1;
- UINT32 Parameter2;
+ UINT32 Parameter2;
- UINT32 Status;
+ UINT32 Status;
- UINT32 CycleBit:1;
- UINT32 RsvdZ1:9;
- UINT32 Type:6;
- UINT32 Control:16;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ1 : 9;
+ UINT32 Type : 6;
+ UINT32 Control : 16;
} TRB_TEMPLATE;
typedef struct _TRANSFER_RING {
- VOID *RingSeg0;
- UINTN TrbNumber;
- TRB_TEMPLATE *RingEnqueue;
- TRB_TEMPLATE *RingDequeue;
- UINT32 RingPCS;
+ VOID *RingSeg0;
+ UINTN TrbNumber;
+ TRB_TEMPLATE *RingEnqueue;
+ TRB_TEMPLATE *RingDequeue;
+ UINT32 RingPCS;
} TRANSFER_RING;
typedef struct _EVENT_RING {
- VOID *ERSTBase;
- VOID *EventRingSeg0;
- UINTN TrbNumber;
- TRB_TEMPLATE *EventRingEnqueue;
- TRB_TEMPLATE *EventRingDequeue;
- UINT32 EventRingCCS;
+ VOID *ERSTBase;
+ VOID *EventRingSeg0;
+ UINTN TrbNumber;
+ TRB_TEMPLATE *EventRingEnqueue;
+ TRB_TEMPLATE *EventRingDequeue;
+ UINT32 EventRingCCS;
} EVENT_RING;
//
@@ -159,39 +160,39 @@ typedef struct _EVENT_RING {
// usb requests.
//
typedef struct _URB {
- UINT32 Signature;
- LIST_ENTRY UrbList;
+ UINT32 Signature;
+ LIST_ENTRY UrbList;
//
// Usb Device URB related information
//
- USB_ENDPOINT Ep;
- EFI_USB_DEVICE_REQUEST *Request;
- VOID *Data;
- UINTN DataLen;
- VOID *DataPhy;
- VOID *DataMap;
- EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
- VOID *Context;
+ USB_ENDPOINT Ep;
+ EFI_USB_DEVICE_REQUEST *Request;
+ VOID *Data;
+ UINTN DataLen;
+ VOID *DataPhy;
+ VOID *DataMap;
+ EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
+ VOID *Context;
//
// Execute result
//
- UINT32 Result;
+ UINT32 Result;
//
// completed data length
//
- UINTN Completed;
+ UINTN Completed;
//
// Command/Tranfer Ring info
//
- TRANSFER_RING *Ring;
- TRB_TEMPLATE *TrbStart;
- TRB_TEMPLATE *TrbEnd;
- UINTN TrbNum;
- BOOLEAN StartDone;
- BOOLEAN EndDone;
- BOOLEAN Finished;
+ TRANSFER_RING *Ring;
+ TRB_TEMPLATE *TrbStart;
+ TRB_TEMPLATE *TrbEnd;
+ UINTN TrbNum;
+ BOOLEAN StartDone;
+ BOOLEAN EndDone;
+ BOOLEAN Finished;
- TRB_TEMPLATE *EvtTrb;
+ TRB_TEMPLATE *EvtTrb;
} URB;
//
@@ -202,11 +203,11 @@ typedef struct _URB {
// is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
//
typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
- UINT32 PtrLo;
- UINT32 PtrHi;
- UINT32 RingTrbSize:16;
- UINT32 RsvdZ1:16;
- UINT32 RsvdZ2;
+ UINT32 PtrLo;
+ UINT32 PtrHi;
+ UINT32 RingTrbSize : 16;
+ UINT32 RsvdZ1 : 16;
+ UINT32 RsvdZ2;
} EVENT_RING_SEG_TABLE_ENTRY;
//
@@ -216,25 +217,25 @@ typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
// Rings, and to define the Data stage information for Control Transfer Rings.
//
typedef struct _TRANSFER_TRB_NORMAL {
- UINT32 TRBPtrLo;
+ UINT32 TRBPtrLo;
- UINT32 TRBPtrHi;
+ UINT32 TRBPtrHi;
- UINT32 Length:17;
- UINT32 TDSize:5;
- UINT32 IntTarget:10;
+ UINT32 Length : 17;
+ UINT32 TDSize : 5;
+ UINT32 IntTarget : 10;
- UINT32 CycleBit:1;
- UINT32 ENT:1;
- UINT32 ISP:1;
- UINT32 NS:1;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 IDT:1;
- UINT32 RsvdZ1:2;
- UINT32 BEI:1;
- UINT32 Type:6;
- UINT32 RsvdZ2:16;
+ UINT32 CycleBit : 1;
+ UINT32 ENT : 1;
+ UINT32 ISP : 1;
+ UINT32 NS : 1;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 IDT : 1;
+ UINT32 RsvdZ1 : 2;
+ UINT32 BEI : 1;
+ UINT32 Type : 6;
+ UINT32 RsvdZ2 : 16;
} TRANSFER_TRB_NORMAL;
//
@@ -242,25 +243,25 @@ typedef struct _TRANSFER_TRB_NORMAL {
// A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
//
typedef struct _TRANSFER_TRB_CONTROL_SETUP {
- UINT32 bmRequestType:8;
- UINT32 bRequest:8;
- UINT32 wValue:16;
+ UINT32 bmRequestType : 8;
+ UINT32 bRequest : 8;
+ UINT32 wValue : 16;
- UINT32 wIndex:16;
- UINT32 wLength:16;
+ UINT32 wIndex : 16;
+ UINT32 wLength : 16;
- UINT32 Length:17;
- UINT32 RsvdZ1:5;
- UINT32 IntTarget:10;
+ UINT32 Length : 17;
+ UINT32 RsvdZ1 : 5;
+ UINT32 IntTarget : 10;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:4;
- UINT32 IOC:1;
- UINT32 IDT:1;
- UINT32 RsvdZ3:3;
- UINT32 Type:6;
- UINT32 TRT:2;
- UINT32 RsvdZ4:14;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 4;
+ UINT32 IOC : 1;
+ UINT32 IDT : 1;
+ UINT32 RsvdZ3 : 3;
+ UINT32 Type : 6;
+ UINT32 TRT : 2;
+ UINT32 RsvdZ4 : 14;
} TRANSFER_TRB_CONTROL_SETUP;
//
@@ -268,25 +269,25 @@ typedef struct _TRANSFER_TRB_CONTROL_SETUP {
// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
//
typedef struct _TRANSFER_TRB_CONTROL_DATA {
- UINT32 TRBPtrLo;
+ UINT32 TRBPtrLo;
- UINT32 TRBPtrHi;
+ UINT32 TRBPtrHi;
- UINT32 Length:17;
- UINT32 TDSize:5;
- UINT32 IntTarget:10;
+ UINT32 Length : 17;
+ UINT32 TDSize : 5;
+ UINT32 IntTarget : 10;
- UINT32 CycleBit:1;
- UINT32 ENT:1;
- UINT32 ISP:1;
- UINT32 NS:1;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 IDT:1;
- UINT32 RsvdZ1:3;
- UINT32 Type:6;
- UINT32 DIR:1;
- UINT32 RsvdZ2:15;
+ UINT32 CycleBit : 1;
+ UINT32 ENT : 1;
+ UINT32 ISP : 1;
+ UINT32 NS : 1;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 IDT : 1;
+ UINT32 RsvdZ1 : 3;
+ UINT32 Type : 6;
+ UINT32 DIR : 1;
+ UINT32 RsvdZ2 : 15;
} TRANSFER_TRB_CONTROL_DATA;
//
@@ -294,21 +295,21 @@ typedef struct _TRANSFER_TRB_CONTROL_DATA {
// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
//
typedef struct _TRANSFER_TRB_CONTROL_STATUS {
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
- UINT32 RsvdZ3:22;
- UINT32 IntTarget:10;
+ UINT32 RsvdZ3 : 22;
+ UINT32 IntTarget : 10;
- UINT32 CycleBit:1;
- UINT32 ENT:1;
- UINT32 RsvdZ4:2;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 RsvdZ5:4;
- UINT32 Type:6;
- UINT32 DIR:1;
- UINT32 RsvdZ6:15;
+ UINT32 CycleBit : 1;
+ UINT32 ENT : 1;
+ UINT32 RsvdZ4 : 2;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 RsvdZ5 : 4;
+ UINT32 Type : 6;
+ UINT32 DIR : 1;
+ UINT32 RsvdZ6 : 15;
} TRANSFER_TRB_CONTROL_STATUS;
//
@@ -317,21 +318,21 @@ typedef struct _TRANSFER_TRB_CONTROL_STATUS {
// for more information on the use and operation of Transfer Events.
//
typedef struct _EVT_TRB_TRANSFER {
- UINT32 TRBPtrLo;
+ UINT32 TRBPtrLo;
- UINT32 TRBPtrHi;
+ UINT32 TRBPtrHi;
- UINT32 Length:24;
- UINT32 Completecode:8;
+ UINT32 Length : 24;
+ UINT32 Completecode : 8;
- UINT32 CycleBit:1;
- UINT32 RsvdZ1:1;
- UINT32 ED:1;
- UINT32 RsvdZ2:7;
- UINT32 Type:6;
- UINT32 EndpointId:5;
- UINT32 RsvdZ3:3;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ1 : 1;
+ UINT32 ED : 1;
+ UINT32 RsvdZ2 : 7;
+ UINT32 Type : 6;
+ UINT32 EndpointId : 5;
+ UINT32 RsvdZ3 : 3;
+ UINT32 SlotId : 8;
} EVT_TRB_TRANSFER;
//
@@ -340,26 +341,26 @@ typedef struct _EVT_TRB_TRANSFER {
// Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
//
typedef struct _EVT_TRB_COMMAND_COMPLETION {
- UINT32 TRBPtrLo;
+ UINT32 TRBPtrLo;
- UINT32 TRBPtrHi;
+ UINT32 TRBPtrHi;
- UINT32 RsvdZ2:24;
- UINT32 Completecode:8;
+ UINT32 RsvdZ2 : 24;
+ UINT32 Completecode : 8;
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 VFID:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 VFID : 8;
+ UINT32 SlotId : 8;
} EVT_TRB_COMMAND_COMPLETION;
typedef union _TRB {
- TRB_TEMPLATE TrbTemplate;
- TRANSFER_TRB_NORMAL TrbNormal;
- TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
- TRANSFER_TRB_CONTROL_DATA TrbCtrData;
- TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
+ TRB_TEMPLATE TrbTemplate;
+ TRANSFER_TRB_NORMAL TrbNormal;
+ TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
+ TRANSFER_TRB_CONTROL_DATA TrbCtrData;
+ TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
} TRB;
//
@@ -368,14 +369,14 @@ typedef union _TRB {
// mechanisms offered by the xHCI.
//
typedef struct _CMD_TRB_NO_OP {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 RsvdZ4:16;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 16;
} CMD_TRB_NO_OP;
//
@@ -384,14 +385,14 @@ typedef struct _CMD_TRB_NO_OP {
// selected slot to the host in a Command Completion Event.
//
typedef struct _CMD_TRB_ENABLE_SLOT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 RsvdZ4:16;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 16;
} CMD_TRB_ENABLE_SLOT;
//
@@ -400,15 +401,15 @@ typedef struct _CMD_TRB_ENABLE_SLOT {
// internal xHC resources assigned to the slot.
//
typedef struct _CMD_TRB_DISABLE_SLOT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 RsvdZ4:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_DISABLE_SLOT;
//
@@ -418,18 +419,18 @@ typedef struct _CMD_TRB_DISABLE_SLOT {
// issue a SET_ADDRESS request to the USB device.
//
typedef struct _CMD_TRB_ADDRESS_DEVICE {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1;
+ UINT32 RsvdZ1;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:8;
- UINT32 BSR:1;
- UINT32 Type:6;
- UINT32 RsvdZ3:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 8;
+ UINT32 BSR : 1;
+ UINT32 Type : 6;
+ UINT32 RsvdZ3 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_ADDRESS_DEVICE;
//
@@ -438,18 +439,18 @@ typedef struct _CMD_TRB_ADDRESS_DEVICE {
// endpoints selected by the command.
//
typedef struct _CMD_TRB_CONFIG_ENDPOINT {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1;
+ UINT32 RsvdZ1;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:8;
- UINT32 DC:1;
- UINT32 Type:6;
- UINT32 RsvdZ3:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 8;
+ UINT32 DC : 1;
+ UINT32 Type : 6;
+ UINT32 RsvdZ3 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_CONFIG_ENDPOINT;
//
@@ -459,17 +460,17 @@ typedef struct _CMD_TRB_CONFIG_ENDPOINT {
// shall evaluate any changes
//
typedef struct _CMD_TRB_EVALUATE_CONTEXT {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1;
+ UINT32 RsvdZ1;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:9;
- UINT32 Type:6;
- UINT32 RsvdZ3:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ3 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_EVALUATE_CONTEXT;
//
@@ -477,17 +478,17 @@ typedef struct _CMD_TRB_EVALUATE_CONTEXT {
// The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
//
typedef struct _CMD_TRB_RESET_ENDPOINT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:8;
- UINT32 TSP:1;
- UINT32 Type:6;
- UINT32 EDID:5;
- UINT32 RsvdZ4:3;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 8;
+ UINT32 TSP : 1;
+ UINT32 Type : 6;
+ UINT32 EDID : 5;
+ UINT32 RsvdZ4 : 3;
+ UINT32 SlotId : 8;
} CMD_TRB_RESET_ENDPOINT;
//
@@ -496,17 +497,17 @@ typedef struct _CMD_TRB_RESET_ENDPOINT {
// Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
//
typedef struct _CMD_TRB_STOP_ENDPOINT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 EDID:5;
- UINT32 RsvdZ4:2;
- UINT32 SP:1;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 EDID : 5;
+ UINT32 RsvdZ4 : 2;
+ UINT32 SP : 1;
+ UINT32 SlotId : 8;
} CMD_TRB_STOP_ENDPOINT;
//
@@ -515,19 +516,19 @@ typedef struct _CMD_TRB_STOP_ENDPOINT {
// Pointer and DCS fields of an Endpoint or Stream Context.
//
typedef struct _CMD_SET_TR_DEQ_POINTER {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1:16;
- UINT32 StreamID:16;
+ UINT32 RsvdZ1 : 16;
+ UINT32 StreamID : 16;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:9;
- UINT32 Type:6;
- UINT32 Endpoint:5;
- UINT32 RsvdZ3:3;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 9;
+ UINT32 Type : 6;
+ UINT32 Endpoint : 5;
+ UINT32 RsvdZ3 : 3;
+ UINT32 SlotId : 8;
} CMD_SET_TR_DEQ_POINTER;
//
@@ -535,211 +536,207 @@ typedef struct _CMD_SET_TR_DEQ_POINTER {
// A Link TRB provides support for non-contiguous TRB Rings.
//
typedef struct _LINK_TRB {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1:22;
- UINT32 InterTarget:10;
+ UINT32 RsvdZ1 : 22;
+ UINT32 InterTarget : 10;
- UINT32 CycleBit:1;
- UINT32 TC:1;
- UINT32 RsvdZ2:2;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 RsvdZ3:4;
- UINT32 Type:6;
- UINT32 RsvdZ4:16;
+ UINT32 CycleBit : 1;
+ UINT32 TC : 1;
+ UINT32 RsvdZ2 : 2;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 RsvdZ3 : 4;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 16;
} LINK_TRB;
//
// 6.2.2 Slot Context
//
typedef struct _SLOT_CONTEXT {
- UINT32 RouteString:20;
- UINT32 Speed:4;
- UINT32 RsvdZ1:1;
- UINT32 MTT:1;
- UINT32 Hub:1;
- UINT32 ContextEntries:5;
+ UINT32 RouteString : 20;
+ UINT32 Speed : 4;
+ UINT32 RsvdZ1 : 1;
+ UINT32 MTT : 1;
+ UINT32 Hub : 1;
+ UINT32 ContextEntries : 5;
- UINT32 MaxExitLatency:16;
- UINT32 RootHubPortNum:8;
- UINT32 PortNum:8;
+ UINT32 MaxExitLatency : 16;
+ UINT32 RootHubPortNum : 8;
+ UINT32 PortNum : 8;
- UINT32 TTHubSlotId:8;
- UINT32 TTPortNum:8;
- UINT32 TTT:2;
- UINT32 RsvdZ2:4;
- UINT32 InterTarget:10;
+ UINT32 TTHubSlotId : 8;
+ UINT32 TTPortNum : 8;
+ UINT32 TTT : 2;
+ UINT32 RsvdZ2 : 4;
+ UINT32 InterTarget : 10;
- UINT32 DeviceAddress:8;
- UINT32 RsvdZ3:19;
- UINT32 SlotState:5;
+ UINT32 DeviceAddress : 8;
+ UINT32 RsvdZ3 : 19;
+ UINT32 SlotState : 5;
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
} SLOT_CONTEXT;
typedef struct _SLOT_CONTEXT_64 {
- UINT32 RouteString:20;
- UINT32 Speed:4;
- UINT32 RsvdZ1:1;
- UINT32 MTT:1;
- UINT32 Hub:1;
- UINT32 ContextEntries:5;
+ UINT32 RouteString : 20;
+ UINT32 Speed : 4;
+ UINT32 RsvdZ1 : 1;
+ UINT32 MTT : 1;
+ UINT32 Hub : 1;
+ UINT32 ContextEntries : 5;
- UINT32 MaxExitLatency:16;
- UINT32 RootHubPortNum:8;
- UINT32 PortNum:8;
+ UINT32 MaxExitLatency : 16;
+ UINT32 RootHubPortNum : 8;
+ UINT32 PortNum : 8;
- UINT32 TTHubSlotId:8;
- UINT32 TTPortNum:8;
- UINT32 TTT:2;
- UINT32 RsvdZ2:4;
- UINT32 InterTarget:10;
+ UINT32 TTHubSlotId : 8;
+ UINT32 TTPortNum : 8;
+ UINT32 TTT : 2;
+ UINT32 RsvdZ2 : 4;
+ UINT32 InterTarget : 10;
- UINT32 DeviceAddress:8;
- UINT32 RsvdZ3:19;
- UINT32 SlotState:5;
+ UINT32 DeviceAddress : 8;
+ UINT32 RsvdZ3 : 19;
+ UINT32 SlotState : 5;
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
- UINT32 RsvdZ8;
- UINT32 RsvdZ9;
- UINT32 RsvdZ10;
- UINT32 RsvdZ11;
-
- UINT32 RsvdZ12;
- UINT32 RsvdZ13;
- UINT32 RsvdZ14;
- UINT32 RsvdZ15;
+ UINT32 RsvdZ8;
+ UINT32 RsvdZ9;
+ UINT32 RsvdZ10;
+ UINT32 RsvdZ11;
+ UINT32 RsvdZ12;
+ UINT32 RsvdZ13;
+ UINT32 RsvdZ14;
+ UINT32 RsvdZ15;
} SLOT_CONTEXT_64;
-
//
// 6.2.3 Endpoint Context
//
typedef struct _ENDPOINT_CONTEXT {
- UINT32 EPState:3;
- UINT32 RsvdZ1:5;
- UINT32 Mult:2;
- UINT32 MaxPStreams:5;
- UINT32 LSA:1;
- UINT32 Interval:8;
- UINT32 RsvdZ2:8;
+ UINT32 EPState : 3;
+ UINT32 RsvdZ1 : 5;
+ UINT32 Mult : 2;
+ UINT32 MaxPStreams : 5;
+ UINT32 LSA : 1;
+ UINT32 Interval : 8;
+ UINT32 RsvdZ2 : 8;
- UINT32 RsvdZ3:1;
- UINT32 CErr:2;
- UINT32 EPType:3;
- UINT32 RsvdZ4:1;
- UINT32 HID:1;
- UINT32 MaxBurstSize:8;
- UINT32 MaxPacketSize:16;
+ UINT32 RsvdZ3 : 1;
+ UINT32 CErr : 2;
+ UINT32 EPType : 3;
+ UINT32 RsvdZ4 : 1;
+ UINT32 HID : 1;
+ UINT32 MaxBurstSize : 8;
+ UINT32 MaxPacketSize : 16;
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 AverageTRBLength:16;
- UINT32 MaxESITPayload:16;
+ UINT32 AverageTRBLength : 16;
+ UINT32 MaxESITPayload : 16;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
} ENDPOINT_CONTEXT;
typedef struct _ENDPOINT_CONTEXT_64 {
- UINT32 EPState:3;
- UINT32 RsvdZ1:5;
- UINT32 Mult:2;
- UINT32 MaxPStreams:5;
- UINT32 LSA:1;
- UINT32 Interval:8;
- UINT32 RsvdZ2:8;
+ UINT32 EPState : 3;
+ UINT32 RsvdZ1 : 5;
+ UINT32 Mult : 2;
+ UINT32 MaxPStreams : 5;
+ UINT32 LSA : 1;
+ UINT32 Interval : 8;
+ UINT32 RsvdZ2 : 8;
- UINT32 RsvdZ3:1;
- UINT32 CErr:2;
- UINT32 EPType:3;
- UINT32 RsvdZ4:1;
- UINT32 HID:1;
- UINT32 MaxBurstSize:8;
- UINT32 MaxPacketSize:16;
+ UINT32 RsvdZ3 : 1;
+ UINT32 CErr : 2;
+ UINT32 EPType : 3;
+ UINT32 RsvdZ4 : 1;
+ UINT32 HID : 1;
+ UINT32 MaxBurstSize : 8;
+ UINT32 MaxPacketSize : 16;
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 AverageTRBLength:16;
- UINT32 MaxESITPayload:16;
+ UINT32 AverageTRBLength : 16;
+ UINT32 MaxESITPayload : 16;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
- UINT32 RsvdZ8;
- UINT32 RsvdZ9;
- UINT32 RsvdZ10;
- UINT32 RsvdZ11;
-
- UINT32 RsvdZ12;
- UINT32 RsvdZ13;
- UINT32 RsvdZ14;
- UINT32 RsvdZ15;
+ UINT32 RsvdZ8;
+ UINT32 RsvdZ9;
+ UINT32 RsvdZ10;
+ UINT32 RsvdZ11;
+ UINT32 RsvdZ12;
+ UINT32 RsvdZ13;
+ UINT32 RsvdZ14;
+ UINT32 RsvdZ15;
} ENDPOINT_CONTEXT_64;
-
//
// 6.2.5.1 Input Control Context
//
typedef struct _INPUT_CONTRL_CONTEXT {
- UINT32 Dword1;
- UINT32 Dword2;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
- UINT32 RsvdZ3;
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
+ UINT32 Dword1;
+ UINT32 Dword2;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+ UINT32 RsvdZ3;
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
} INPUT_CONTRL_CONTEXT;
typedef struct _INPUT_CONTRL_CONTEXT_64 {
- UINT32 Dword1;
- UINT32 Dword2;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
- UINT32 RsvdZ3;
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
- UINT32 RsvdZ8;
- UINT32 RsvdZ9;
- UINT32 RsvdZ10;
- UINT32 RsvdZ11;
- UINT32 RsvdZ12;
- UINT32 RsvdZ13;
- UINT32 RsvdZ14;
+ UINT32 Dword1;
+ UINT32 Dword2;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+ UINT32 RsvdZ3;
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
+ UINT32 RsvdZ8;
+ UINT32 RsvdZ9;
+ UINT32 RsvdZ10;
+ UINT32 RsvdZ11;
+ UINT32 RsvdZ12;
+ UINT32 RsvdZ13;
+ UINT32 RsvdZ14;
} INPUT_CONTRL_CONTEXT_64;
//
// 6.2.1 Device Context
//
typedef struct _DEVICE_CONTEXT {
- SLOT_CONTEXT Slot;
- ENDPOINT_CONTEXT EP[31];
+ SLOT_CONTEXT Slot;
+ ENDPOINT_CONTEXT EP[31];
} DEVICE_CONTEXT;
typedef struct _DEVICE_CONTEXT_64 {
- SLOT_CONTEXT_64 Slot;
- ENDPOINT_CONTEXT_64 EP[31];
+ SLOT_CONTEXT_64 Slot;
+ ENDPOINT_CONTEXT_64 EP[31];
} DEVICE_CONTEXT_64;
//
@@ -752,12 +749,11 @@ typedef struct _INPUT_CONTEXT {
} INPUT_CONTEXT;
typedef struct _INPUT_CONTEXT_64 {
- INPUT_CONTRL_CONTEXT_64 InputControlContext;
- SLOT_CONTEXT_64 Slot;
- ENDPOINT_CONTEXT_64 EP[31];
+ INPUT_CONTRL_CONTEXT_64 InputControlContext;
+ SLOT_CONTEXT_64 Slot;
+ ENDPOINT_CONTEXT_64 EP[31];
} INPUT_CONTEXT_64;
-
/**
Initialize the XHCI host controller for schedule.
@@ -766,7 +762,7 @@ typedef struct _INPUT_CONTEXT_64 {
**/
VOID
XhcInitSched (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -777,7 +773,7 @@ XhcInitSched (
**/
VOID
XhcFreeSched (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -791,8 +787,8 @@ XhcFreeSched (
**/
EFI_STATUS
RingIntTransferDoorBell (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
/**
@@ -810,10 +806,10 @@ RingIntTransferDoorBell (
**/
EFI_STATUS
XhcExecTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN BOOLEAN CmdTransfer,
- IN URB *Urb,
- IN UINTN Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN BOOLEAN CmdTransfer,
+ IN URB *Urb,
+ IN UINTN Timeout
);
/**
@@ -830,9 +826,9 @@ XhcExecTransfer (
**/
EFI_STATUS
XhciDelAsyncIntTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpNum
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpNum
);
/**
@@ -843,7 +839,7 @@ XhciDelAsyncIntTransfer (
**/
VOID
XhciDelAllAsyncIntTransfers (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -864,14 +860,14 @@ XhciDelAllAsyncIntTransfers (
**/
URB *
XhciInsertAsyncIntTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
);
/**
@@ -882,7 +878,7 @@ XhciInsertAsyncIntTransfer (
**/
VOID
XhcSetBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -893,7 +889,7 @@ XhcSetBiosOwnership (
**/
VOID
XhcClearBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -923,8 +919,8 @@ XhcRouteStringToSlotId (
**/
UINT8
XhcEndpointToDci (
- IN UINT8 EpAddr,
- IN UINT8 Direction
+ IN UINT8 EpAddr,
+ IN UINT8 Direction
);
/**
@@ -940,9 +936,9 @@ XhcEndpointToDci (
EFI_STATUS
EFIAPI
XhcRingDoorBell (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
);
/**
@@ -955,8 +951,8 @@ XhcRingDoorBell (
VOID
EFIAPI
XhcMonitorAsyncRequests (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
);
/**
@@ -974,10 +970,10 @@ XhcMonitorAsyncRequests (
EFI_STATUS
EFIAPI
XhcPollPortStatusChange (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT8 Port,
- IN EFI_USB_PORT_STATUS *PortState
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT8 Port,
+ IN EFI_USB_PORT_STATUS *PortState
);
/**
@@ -994,14 +990,13 @@ XhcPollPortStatusChange (
**/
EFI_STATUS
XhcConfigHubContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
);
-
/**
Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
@@ -1016,14 +1011,13 @@ XhcConfigHubContext (
**/
EFI_STATUS
XhcConfigHubContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
);
-
/**
Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
@@ -1038,13 +1032,12 @@ XhcConfigHubContext64 (
EFI_STATUS
EFIAPI
XhcSetConfigCmd (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
);
-
/**
Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
@@ -1059,10 +1052,10 @@ XhcSetConfigCmd (
EFI_STATUS
EFIAPI
XhcSetConfigCmd64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
);
/**
@@ -1080,11 +1073,11 @@ XhcSetConfigCmd64 (
EFI_STATUS
EFIAPI
XhcSetInterface (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
- IN EFI_USB_DEVICE_REQUEST *Request
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
+ IN EFI_USB_DEVICE_REQUEST *Request
);
/**
@@ -1102,11 +1095,11 @@ XhcSetInterface (
EFI_STATUS
EFIAPI
XhcSetInterface64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
- IN EFI_USB_DEVICE_REQUEST *Request
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
+ IN EFI_USB_DEVICE_REQUEST *Request
);
/**
@@ -1140,11 +1133,11 @@ XhcBusDevAddrToSlotId (
EFI_STATUS
EFIAPI
XhcInitializeDeviceSlot (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
);
/**
@@ -1162,11 +1155,11 @@ XhcInitializeDeviceSlot (
EFI_STATUS
EFIAPI
XhcInitializeDeviceSlot64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
);
/**
@@ -1182,12 +1175,11 @@ XhcInitializeDeviceSlot64 (
EFI_STATUS
EFIAPI
XhcEvaluateContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
);
-
/**
Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
@@ -1201,12 +1193,11 @@ XhcEvaluateContext (
EFI_STATUS
EFIAPI
XhcEvaluateContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
);
-
/**
Disable the specified device slot.
@@ -1219,11 +1210,10 @@ XhcEvaluateContext64 (
EFI_STATUS
EFIAPI
XhcDisableSlotCmd (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId
);
-
/**
Disable the specified device slot.
@@ -1236,11 +1226,10 @@ XhcDisableSlotCmd (
EFI_STATUS
EFIAPI
XhcDisableSlotCmd64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId
);
-
/**
Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
@@ -1253,8 +1242,8 @@ XhcDisableSlotCmd64 (
EFI_STATUS
EFIAPI
XhcSyncTrsRing (
- IN USB_XHCI_INSTANCE *Xhc,
- TRANSFER_RING *TrsRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ TRANSFER_RING *TrsRing
);
/**
@@ -1269,8 +1258,8 @@ XhcSyncTrsRing (
EFI_STATUS
EFIAPI
XhcSyncEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- EVENT_RING *EvtRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ EVENT_RING *EvtRing
);
/**
@@ -1287,9 +1276,9 @@ XhcSyncEventRing (
EFI_STATUS
EFIAPI
XhcCheckNewEvent (
- IN USB_XHCI_INSTANCE *Xhc,
- IN EVENT_RING *EvtRing,
- OUT TRB_TEMPLATE **NewEvtTrb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN EVENT_RING *EvtRing,
+ OUT TRB_TEMPLATE **NewEvtTrb
);
/**
@@ -1302,9 +1291,9 @@ XhcCheckNewEvent (
**/
VOID
CreateTransferRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINTN TrbNum,
- OUT TRANSFER_RING *TransferRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINTN TrbNum,
+ OUT TRANSFER_RING *TransferRing
);
/**
@@ -1316,8 +1305,8 @@ CreateTransferRing (
**/
VOID
CreateEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- OUT EVENT_RING *EventRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ OUT EVENT_RING *EventRing
);
/**
@@ -1337,8 +1326,8 @@ CreateEventRing (
EFI_STATUS
EFIAPI
XhcRecoverHaltedEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
/**
@@ -1357,8 +1346,8 @@ XhcRecoverHaltedEndpoint (
EFI_STATUS
EFIAPI
XhcDequeueTrbFromEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
/**
@@ -1376,10 +1365,10 @@ XhcDequeueTrbFromEndpoint (
EFI_STATUS
EFIAPI
XhcStopEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *PendingUrb OPTIONAL
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *PendingUrb OPTIONAL
);
/**
@@ -1396,9 +1385,9 @@ XhcStopEndpoint (
EFI_STATUS
EFIAPI
XhcResetEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
);
/**
@@ -1417,10 +1406,10 @@ XhcResetEndpoint (
EFI_STATUS
EFIAPI
XhcSetTrDequeuePointer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *Urb
);
/**
@@ -1441,19 +1430,19 @@ XhcSetTrDequeuePointer (
@return Created URB or NULL
**/
-URB*
+URB *
XhcCreateUrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 DevAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
);
/**
@@ -1465,8 +1454,8 @@ XhcCreateUrb (
**/
VOID
XhcFreeUrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
/**
@@ -1480,8 +1469,8 @@ XhcFreeUrb (
**/
EFI_STATUS
XhcCreateTransferTrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
#endif