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Merge branch 'master' of https://github.com/CloverHackyColor/CloverBootloader

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SergeySlice 2022-02-08 20:01:10 +03:00
commit 294551b969
10 changed files with 4881 additions and 1242 deletions
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2392
CloverPackage/CloverV2/EFI/CLOVER/config-sample.plist
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2
MdePkg/Include/IndustryStandard/Acpi.h
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@ -11,6 +11,6 @@
#ifndef _ACPI_H_
#define _ACPI_H_
#include <IndustryStandard/Acpi63.h>
#include <IndustryStandard/Acpi64.h>
#endif

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MdePkg/Include/IndustryStandard/Acpi64.h Normal file
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13
MdePkg/Include/IndustryStandard/AcpiAml.h
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@ -171,9 +171,14 @@
//
// FieldElement OpCode
//
#define AML_FIELD_RESERVED_OP 0x00
#define AML_FIELD_ACCESS_OP 0x01
#define AML_FIELD_CONNECTION_OP 0x02
#define AML_FIELD_EXT_ACCESS_OP 0x03
#define AML_FIELD_RESERVED_OP 0x00
#define AML_FIELD_ACCESS_OP 0x01
#define AML_FIELD_CONNECTION_OP 0x02
#define AML_FIELD_EXT_ACCESS_OP 0x03
//
// AML Name segment definitions
//
#define AML_NAME_SEG_SIZE 4
#endif

6
MdePkg/Include/IndustryStandard/Pci.h
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@ -1,7 +1,7 @@
/** @file
Support for the latest PCI standard.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -9,9 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _PCI_H_
#define _PCI_H_
#include <IndustryStandard/Pci30.h>
#include <IndustryStandard/PciExpress21.h>
#include <IndustryStandard/PciExpress30.h>
#include <IndustryStandard/PciExpress50.h>
#include <IndustryStandard/PciCodeId.h>
#endif

2
MdePkg/Include/IndustryStandard/Pci22.h
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@ -5,7 +5,7 @@
PCI Local Bus Specification, 2.2
PCI-to-PCI Bridge Architecture Specification, Revision 1.2
PC Card Standard, 8.0
PCI Power Management Interface Specifiction, Revision 1.2
PCI Power Management Interface Specification, Revision 1.2
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>

136
MdePkg/Include/IndustryStandard/PciExpress50.h Normal file
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@ -0,0 +1,136 @@
/** @file
Support for the PCI Express 5.0 standard.
This header file may not define all structures. Please extend as required.
Copyright (c) 2020, American Megatrends International LLC. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _PCIEXPRESS50_H_
#define _PCIEXPRESS50_H_
#include <IndustryStandard/PciExpress40.h>
#pragma pack(1)
/// The Physical Layer PCI Express Extended Capability definitions.
///
/// Based on section 7.7.6 of PCI Express Base Specification 5.0.
///@{
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID 0x002A
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1
// Register offsets from Physical Layer PCI-E Ext Cap Header
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET 0x04
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET 0x08
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET 0x0C
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET 0x10
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET 0x14
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET 0x18
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET 0x1C
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
typedef union {
struct {
UINT32 EqualizationByPassToHighestRateSupport : 1; // bit 0
UINT32 NoEqualizationNeededSupport : 1; // bit 1
UINT32 Reserved1 : 6; // Reserved bit 2:7
UINT32 ModifiedTSUsageMode0Support : 1; // bit 8
UINT32 ModifiedTSUsageMode1Support : 1; // bit 9
UINT32 ModifiedTSUsageMode2Support : 1; // bit 10
UINT32 ModifiedTSReservedUsageModes : 5; // bit 11:15
UINT32 Reserved2 : 16; // Reserved bit 16:31
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES;
typedef union {
struct {
UINT32 EqualizationByPassToHighestRateDisable : 1; // bit 0
UINT32 NoEqualizationNeededDisable : 1; // bit 1
UINT32 Reserved1 : 6; // Reserved bit 2:7
UINT32 ModifiedTSUsageModeSelected : 3; // bit 8:10
UINT32 Reserved2 : 21; // Reserved bit 11:31
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL;
typedef union {
struct {
UINT32 EqualizationComplete : 1; // bit 0
UINT32 EqualizationPhase1Success : 1; // bit 1
UINT32 EqualizationPhase2Success : 1; // bit 2
UINT32 EqualizationPhase3Success : 1; // bit 3
UINT32 LinkEqualizationRequest : 1; // bit 4
UINT32 ModifiedTSRcvd : 1; // bit 5
UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7
UINT32 TransmitterPrecodingOn : 1; // bit 8
UINT32 TransmitterPrecodeRequest : 1; // bit 9
UINT32 NoEqualizationNeededRcvd : 1; // bit 10
UINT32 Reserved : 21; // Reserved bit 11:31
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS;
typedef union {
struct {
UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2
UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15
UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1;
typedef union {
struct {
UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23
UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
UINT32 Reserved : 6; // Reserved bit 26:31
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2;
typedef union {
struct {
UINT32 TransModifiedTSUsageMode : 3; // bit 0:2
UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15
UINT32 TransModifiedTSVendorId : 16; // bit 16:31
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1;
typedef union {
struct {
UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23
UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
UINT32 Reserved : 6; // Reserved bit 26:31
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2;
typedef union {
struct {
UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3
UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7
} Bits;
UINT8 Uint8;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL;
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablities;
PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control;
PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status;
PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifiedTs1Data;
PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifiedTs2Data;
PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModifiedTs1Data;
PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModifiedTs2Data;
PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0;
///@}
#pragma pack()
#endif

118
MdePkg/Include/IndustryStandard/SmBios.h
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@ -809,7 +809,10 @@ typedef enum {
ProcessorUpgradeSocketLGA2066 = 0x39,
ProcessorUpgradeSocketBGA1392 = 0x3A,
ProcessorUpgradeSocketBGA1510 = 0x3B,
ProcessorUpgradeSocketBGA1528 = 0x3C
ProcessorUpgradeSocketBGA1528 = 0x3C,
ProcessorUpgradeSocketLGA4189 = 0x3D,
ProcessorUpgradeSocketLGA1200 = 0x3E,
ProcessorUpgradeSocketLGA4677 = 0x3F
} PROCESSOR_UPGRADE;
///
@ -1391,11 +1394,14 @@ typedef struct {
/// System Slots - Slot Characteristics 2.
///
typedef struct {
UINT8 PmeSignalSupported :1;
UINT8 HotPlugDevicesSupported :1;
UINT8 SmbusSignalSupported :1;
UINT8 BifurcationSupported :1;
UINT8 Reserved :4; ///< Set to 0.
UINT8 PmeSignalSupported : 1;
UINT8 HotPlugDevicesSupported : 1;
UINT8 SmbusSignalSupported : 1;
UINT8 BifurcationSupported : 1;
UINT8 AsyncSurpriseRemoval : 1;
UINT8 FlexbusSlotCxl10Capable : 1;
UINT8 FlexbusSlotCxl20Capable : 1;
UINT8 Reserved : 1; ///< Set to 0.
} MISC_SLOT_CHARACTERISTICS2;
///
@ -1434,9 +1440,15 @@ typedef struct {
//
// Add for smbios 3.2
//
UINT8 DataBusWidth;
UINT8 PeerGroupingCount;
MISC_SLOT_PEER_GROUP PeerGroups[1];
UINT8 DataBusWidth;
UINT8 PeerGroupingCount;
MISC_SLOT_PEER_GROUP PeerGroups[1];
//
// Add for smbios 3.4
//
UINT8 SlotInformation;
UINT8 SlotPhysicalWidth;
UINT16 SlotPitch;
} SMBIOS_TABLE_TYPE9;
///
@ -1629,7 +1641,8 @@ typedef enum {
MemoryArrayLocationPc98C20AddonCard = 0xA0,
MemoryArrayLocationPc98C24AddonCard = 0xA1,
MemoryArrayLocationPc98EAddonCard = 0xA2,
MemoryArrayLocationPc98LocalBusAddonCard = 0xA3
MemoryArrayLocationPc98LocalBusAddonCard = 0xA3,
MemoryArrayLocationCXLAddonCard = 0xA4
} MEMORY_ARRAY_LOCATION;
///
@ -1682,21 +1695,22 @@ typedef struct {
/// Memory Device - Form Factor.
///
typedef enum {
MemoryFormFactorOther = 0x01,
MemoryFormFactorUnknown = 0x02,
MemoryFormFactorSimm = 0x03,
MemoryFormFactorSip = 0x04,
MemoryFormFactorChip = 0x05,
MemoryFormFactorDip = 0x06,
MemoryFormFactorZip = 0x07,
MemoryFormFactorProprietaryCard = 0x08,
MemoryFormFactorDimm = 0x09,
MemoryFormFactorTsop = 0x0A,
MemoryFormFactorRowOfChips = 0x0B,
MemoryFormFactorRimm = 0x0C,
MemoryFormFactorSodimm = 0x0D,
MemoryFormFactorSrimm = 0x0E,
MemoryFormFactorFbDimm = 0x0F
MemoryFormFactorOther = 0x01,
MemoryFormFactorUnknown = 0x02,
MemoryFormFactorSimm = 0x03,
MemoryFormFactorSip = 0x04,
MemoryFormFactorChip = 0x05,
MemoryFormFactorDip = 0x06,
MemoryFormFactorZip = 0x07,
MemoryFormFactorProprietaryCard = 0x08,
MemoryFormFactorDimm = 0x09,
MemoryFormFactorTsop = 0x0A,
MemoryFormFactorRowOfChips = 0x0B,
MemoryFormFactorRimm = 0x0C,
MemoryFormFactorSodimm = 0x0D,
MemoryFormFactorSrimm = 0x0E,
MemoryFormFactorFbDimm = 0x0F,
MemoryFormFactorDie = 0x10
} MEMORY_FORM_FACTOR;
///
@ -1763,13 +1777,17 @@ typedef struct {
/// Memory Device - Memory Technology
///
typedef enum {
MemoryTechnologyOther = 0x01,
MemoryTechnologyUnknown = 0x02,
MemoryTechnologyDram = 0x03,
MemoryTechnologyNvdimmN = 0x04,
MemoryTechnologyNvdimmF = 0x05,
MemoryTechnologyNvdimmP = 0x06,
MemoryTechnologyIntelPersistentMemory = 0x07
MemoryTechnologyOther = 0x01,
MemoryTechnologyUnknown = 0x02,
MemoryTechnologyDram = 0x03,
MemoryTechnologyNvdimmN = 0x04,
MemoryTechnologyNvdimmF = 0x05,
MemoryTechnologyNvdimmP = 0x06,
//
// This definition is updated to represent Intel
// Optane DC Persistent Memory in SMBIOS spec 3.4.0
//
MemoryTechnologyIntelOptanePersistentMemory = 0x07
} MEMORY_DEVICE_TECHNOLOGY;
///
@ -1844,17 +1862,22 @@ typedef struct {
//
// Add for smbios 3.2.0
//
UINT8 MemoryTechnology; ///< The enumeration value from MEMORY_DEVICE_TECHNOLOGY
MEMORY_DEVICE_OPERATING_MODE_CAPABILITY MemoryOperatingModeCapability;
SMBIOS_TABLE_STRING FirwareVersion;
UINT16 ModuleManufacturerID;
UINT16 ModuleProductID;
UINT16 MemorySubsystemControllerManufacturerID;
UINT16 MemorySubsystemControllerProductID;
UINT64 NonVolatileSize;
UINT64 VolatileSize;
UINT64 CacheSize;
UINT64 LogicalSize;
UINT8 MemoryTechnology; ///< The enumeration value from MEMORY_DEVICE_TECHNOLOGY
MEMORY_DEVICE_OPERATING_MODE_CAPABILITY MemoryOperatingModeCapability;
SMBIOS_TABLE_STRING FirmwareVersion;
UINT16 ModuleManufacturerID;
UINT16 ModuleProductID;
UINT16 MemorySubsystemControllerManufacturerID;
UINT16 MemorySubsystemControllerProductID;
UINT64 NonVolatileSize;
UINT64 VolatileSize;
UINT64 CacheSize;
UINT64 LogicalSize;
//
// Add for smbios 3.3.0
//
UINT32 ExtendedSpeed;
UINT32 ExtendedConfiguredMemorySpeed;
} SMBIOS_TABLE_TYPE17;
///
@ -2510,6 +2533,15 @@ typedef struct {
UINT8 DevFuncNum;
} SMBIOS_TABLE_TYPE41;
///
/// Management Controller Host Interface - Protocol Record Data Format.
///
typedef struct {
UINT8 ProtocolType;
UINT8 ProtocolTypeDataLen;
UINT8 ProtocolTypeData[1];
} MC_HOST_INTERFACE_PROTOCOL_RECORD;
///
/// Management Controller Host Interface - Interface Types.
/// 00h - 3Fh: MCTP Host Interfaces

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MdePkg/Include/IndustryStandard/Spdm.h Normal file
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@ -0,0 +1,318 @@
/** @file
Definitions of Security Protocol & Data Model Specification (SPDM)
version 1.0.0 in Distributed Management Task Force (DMTF).
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __SPDM_H__
#define __SPDM_H__
#pragma pack(1)
///
/// SPDM response code
///
#define SPDM_DIGESTS 0x01
#define SPDM_CERTIFICATE 0x02
#define SPDM_CHALLENGE_AUTH 0x03
#define SPDM_VERSION 0x04
#define SPDM_MEASUREMENTS 0x60
#define SPDM_CAPABILITIES 0x61
#define SPDM_SET_CERT_RESPONSE 0x62
#define SPDM_ALGORITHMS 0x63
#define SPDM_ERROR 0x7F
///
/// SPDM request code
///
#define SPDM_GET_DIGESTS 0x81
#define SPDM_GET_CERTIFICATE 0x82
#define SPDM_CHALLENGE 0x83
#define SPDM_GET_VERSION 0x84
#define SPDM_GET_MEASUREMENTS 0xE0
#define SPDM_GET_CAPABILITIES 0xE1
#define SPDM_NEGOTIATE_ALGORITHMS 0xE3
#define SPDM_RESPOND_IF_READY 0xFF
///
/// SPDM message header
///
typedef struct {
UINT8 SPDMVersion;
UINT8 RequestResponseCode;
UINT8 Param1;
UINT8 Param2;
} SPDM_MESSAGE_HEADER;
#define SPDM_MESSAGE_VERSION 0x10
///
/// SPDM GET_VERSION request
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
} SPDM_GET_VERSION_REQUEST;
///
/// SPDM GET_VERSION response
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
UINT8 Reserved;
UINT8 VersionNumberEntryCount;
// SPDM_VERSION_NUMBER VersionNumberEntry[VersionNumberEntryCount];
} SPDM_VERSION_RESPONSE;
///
/// SPDM VERSION structure
///
typedef struct {
UINT16 Alpha : 4;
UINT16 UpdateVersionNumber : 4;
UINT16 MinorVersion : 4;
UINT16 MajorVersion : 4;
} SPDM_VERSION_NUMBER;
///
/// SPDM GET_CAPABILITIES request
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
} SPDM_GET_CAPABILITIES_REQUEST;
///
/// SPDM GET_CAPABILITIES response
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
UINT8 Reserved;
UINT8 CTExponent;
UINT16 Reserved2;
UINT32 Flags;
} SPDM_CAPABILITIES_RESPONSE;
///
/// SPDM GET_CAPABILITIES response Flags
///
#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CACHE_CAP BIT0
#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP BIT1
#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP BIT2
#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP (BIT3 | BIT4)
#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_NO_SIG BIT3
#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG BIT4
#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_FRESH_CAP BIT5
///
/// SPDM NEGOTIATE_ALGORITHMS request
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
UINT16 Length;
UINT8 MeasurementSpecification;
UINT8 Reserved;
UINT32 BaseAsymAlgo;
UINT32 BaseHashAlgo;
UINT8 Reserved2[12];
UINT8 ExtAsymCount;
UINT8 ExtHashCount;
UINT16 Reserved3;
// UINT32 ExtAsym[ExtAsymCount];
// UINT32 ExtHash[ExtHashCount];
} SPDM_NEGOTIATE_ALGORITHMS_REQUEST;
///
/// SPDM NEGOTIATE_ALGORITHMS request BaseAsymAlgo
///
#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048 BIT0
#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048 BIT1
#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072 BIT2
#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072 BIT3
#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 BIT4
#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096 BIT5
#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096 BIT6
#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384 BIT7
#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521 BIT8
///
/// SPDM NEGOTIATE_ALGORITHMS request BaseHashAlgo
///
#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256 BIT0
#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384 BIT1
#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512 BIT2
#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256 BIT3
#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384 BIT4
#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512 BIT5
///
/// SPDM NEGOTIATE_ALGORITHMS response
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
UINT16 Length;
UINT8 MeasurementSpecificationSel;
UINT8 Reserved;
UINT32 MeasurementHashAlgo;
UINT32 BaseAsymSel;
UINT32 BaseHashSel;
UINT8 Reserved2[12];
UINT8 ExtAsymSelCount;
UINT8 ExtHashSelCount;
UINT16 Reserved3;
// UINT32 ExtAsymSel[ExtAsymSelCount];
// UINT32 ExtHashSel[ExtHashSelCount];
} SPDM_ALGORITHMS_RESPONSE;
///
/// SPDM NEGOTIATE_ALGORITHMS response MeasurementHashAlgo
///
#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_RAW_BIT_STREAM_ONLY BIT0
#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_256 BIT1
#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_384 BIT2
#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_512 BIT3
#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256 BIT4
#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_384 BIT5
#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_512 BIT6
///
/// SPDM GET_DIGESTS request
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
} SPDM_GET_DIGESTS_REQUEST;
///
/// SPDM GET_DIGESTS response
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
// UINT8 Digest[DigestSize];
} SPDM_DIGESTS_RESPONSE;
///
/// SPDM GET_DIGESTS request
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
UINT16 Offset;
UINT16 Length;
} SPDM_GET_CERTIFICATE_REQUEST;
///
/// SPDM GET_DIGESTS response
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
UINT16 PortionLength;
UINT16 RemainderLength;
// UINT8 CertChain[CertChainSize];
} SPDM_CERTIFICATE_RESPONSE;
///
/// SPDM CHALLENGE request
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
UINT8 Nonce[32];
} SPDM_CHALLENGE_REQUEST;
///
/// SPDM CHALLENGE response
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
// UINT8 CertChainHash[DigestSize];
// UINT8 Nonce[32];
// UINT8 MeasurementSummaryHash[DigestSize];
// UINT16 OpaqueLength;
// UINT8 OpaqueData[OpaqueLength];
// UINT8 Signature[KeySize];
} SPDM_CHALLENGE_AUTH_RESPONSE;
///
/// SPDM GET_MEASUREMENTS request
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
UINT8 Nonce[32];
} SPDM_GET_MEASUREMENTS_REQUEST;
///
/// SPDM MEASUREMENTS block common header
///
typedef struct {
UINT8 Index;
UINT8 MeasurementSpecification;
UINT16 MeasurementSize;
// UINT8 Measurement[MeasurementSize];
} SPDM_MEASUREMENT_BLOCK_COMMON_HEADER;
#define SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF BIT0
///
/// SPDM MEASUREMENTS block DMTF header
///
typedef struct {
UINT8 DMTFSpecMeasurementValueType;
UINT16 DMTFSpecMeasurementValueSize;
// UINT8 DMTFSpecMeasurementValue[DMTFSpecMeasurementValueSize];
} SPDM_MEASUREMENT_BLOCK_DMTF_HEADER;
///
/// SPDM MEASUREMENTS block MeasurementValueType
///
#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_IMMUTABLE_ROM 0
#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_MUTABLE_FIRMWARE 1
#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_HARDWARE_CONFIGURATION 2
#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_FIRMWARE_CONFIGURATION 3
#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_RAW_BIT_STREAM BIT7
///
/// SPDM GET_MEASUREMENTS response
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
UINT8 NumberOfBlocks;
UINT8 MeasurementRecordLength[3];
// UINT8 MeasurementRecord[MeasurementRecordLength];
// UINT8 Nonce[32];
// UINT16 OpaqueLength;
// UINT8 OpaqueData[OpaqueLength];
// UINT8 Signature[KeySize];
} SPDM_MEASUREMENTS_RESPONSE;
///
/// SPDM ERROR response
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
// Param1 == Error Code
// Param2 == Error Data
// UINT8 ExtendedErrorData[];
} SPDM_ERROR_RESPONSE;
///
/// SPDM error code
///
#define SPDM_ERROR_CODE_INVALID_REQUEST 0x01
#define SPDM_ERROR_CODE_BUSY 0x03
#define SPDM_ERROR_CODE_UNEXPECTED_REQUEST 0x04
#define SPDM_ERROR_CODE_UNSPECIFIED 0x05
#define SPDM_ERROR_CODE_UNSUPPORTED_REQUEST 0x07
#define SPDM_ERROR_CODE_MAJOR_VERSION_MISMATCH 0x41
#define SPDM_ERROR_CODE_RESPONSE_NOT_READY 0x42
#define SPDM_ERROR_CODE_REQUEST_RESYNCH 0x43
///
/// SPDM RESPONSE_IF_READY request
///
typedef struct {
SPDM_MESSAGE_HEADER Header;
// Param1 == RequestCode
// Param2 == Token
} SPDM_RESPONSE_IF_READY_REQUEST;
#pragma pack()
#endif

2
rEFIt_UEFI/Platform/guid.cpp
View File

@ -77,7 +77,7 @@ EFI_PART_TYPE_LEGACY_MBR_GUID {0x024DEE41, 0x33E7, 0x11D3, {0x9D, 0x69, 0x00, 0x
// 1FEDE521-031C-4BC5-8050-F3D6161E2E92
// BD8C1056-9F36-44EC-92A8-A6337F817986 gEfiEdidActiveProtocolGuid
// 26baccba-6f42-11d4-bce7-008081883cc7
// 63FAECF2-E7EE-4CB9-8A0C-11CE5E89E33C protocol at FinalizeBootStruct or DrawBootGraphics
// 63FAECF2-E7EE-4CB9-8A0C-11CE5E89E33C protocol at FinalizeBootStruct APPLE_EG2_INFO_PROTOCOL_GUID
// 03B99B90-ECCF-451D-809E-8341FCB830AC RestartData protocol
// 24B73556-2197-4702-82A8-3E1337DAFBF2 before Firmware password APPLE_SECURE_BOOT_PROTOCOL_GUID
// 24B73556-2197-4702-82A8-3E1337DAFBF3 Apple Trusted Boot enabled configuration