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dont fix ownership for VIA 

Signed-off-by: SergeySlice <sergey.slice@gmail.com>
This commit is contained in:
SergeySlice 2022-10-05 21:04:32 +03:00
parent dd0beb2111
commit 70a37b142c
6 changed files with 24 additions and 21 deletions
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14
CloverPackage/CloverV2/EFI/CLOVER/config-sample.plist
View File

@ -884,20 +884,6 @@
<key>Replace</key>
<data>VGVsZXBob25lcwA=</data>
</dict>
<dict>
<key>Comment</key>
<string>Patch_to_not_load_this_driver</string>
<key>Disabled</key>
<true/>
<key>Find</key>
<string>0x04020000</string>
<key>InfoPlistPatch</key>
<true/>
<key>Name</key>
<string>AppleHDAController</string>
<key>Replace</key>
<string>0x44220000</string>
</dict>
<dict>
<key>Comment</key>
<string>Make all drives to be internal</string>

2
rEFIt_UEFI/Platform/ati.cpp
View File

@ -1184,7 +1184,7 @@ Navi23
0x73E31002 0x73FF1002
Radeon Pro WX
The low to mid-range, single slot, Polaris-based WX 4100 (PCIe x8 electrical), WX 5100, WX 7100 are supported from OS X Sierra;
The low to mid-range, single slot, Polaris-based WX 4100 Buffin (PCIe x8 electrical), WX 5100, WX 7100 are supported from OS X Sierra;
the high-end WX 8200 (Vega 56) and WX 9100 (Vega 64), from High Sierra.
Lexa-based WX 2100, WX 3100 and WX 3200 do NOT work.

2
rEFIt_UEFI/Platform/cpu.cpp
View File

@ -1605,7 +1605,6 @@ MacModel GetDefaultModel()
DefaultType = MacPro51;
break;
case CPU_MODEL_IVY_BRIDGE:
case CPU_MODEL_IVY_BRIDGE_E5:
DefaultType = iMac132;
if ( gConf.GfxPropertiesArray.isCardAtPosIntel(0) ) {
DefaultType = MacMini62;
@ -1646,6 +1645,7 @@ MacModel GetDefaultModel()
break;
}
break;
case CPU_MODEL_IVY_BRIDGE_E5:
case CPU_MODEL_BROADWELL_E5:
DefaultType = MacPro61;
break;

2
rEFIt_UEFI/Platform/cpu.h
View File

@ -41,7 +41,7 @@
#define CPU_MODEL_IVY_BRIDGE 0x3A
#define CPU_MODEL_HASWELL 0x3C /* Haswell DT */
#define CPU_MODEL_HASWELL_U5 0x3D /* Haswell U5 5th generation Broadwell*/
#define CPU_MODEL_IVY_BRIDGE_E5 0x3E /* Ivy Bridge Xeon UN */
#define CPU_MODEL_IVY_BRIDGE_E5 0x3E /* Ivy Bridge Xeon E5-2650v2 */
#define CPU_MODEL_HASWELL_E 0x3F /* Haswell Extreme */
//#define CPU_MODEL_HASWELL_H 0x?? // Haswell H
#define CPU_MODEL_HASWELL_ULT 0x45 /* Haswell ULT */

18
rEFIt_UEFI/Platform/usbfix.cpp
View File

@ -77,6 +77,8 @@ DBG("FixOwnership() -> begin\n");
&HandleArrayCount,
&HandleArray
);
DBG("PCI Io found %lld\n", HandleArrayCount);
if (HandleArrayCount > 50) HandleArrayCount = 50;
if (!EFI_ERROR(Status)) {
for (Index = 0; Index < HandleArrayCount; Index++) {
Status = gBS->HandleProtocol (
@ -118,7 +120,7 @@ DBG("FixOwnership() -> begin\n");
IoWrite16 (PortBase, 0);
}
MsgLog("USB UHCI reset for device %04hX\n", Pci.Hdr.DeviceId);
DBG("USB UHCI reset for device %04hX\n", Pci.Hdr.DeviceId);
break;
/* case PCI_IF_OHCI:
@ -136,16 +138,17 @@ DBG("FixOwnership() -> begin\n");
//
// Found the EHCI, then disable the legacy support
//
DBG("EHCI found devID= %04hX\n", Pci.Hdr.DeviceId);
Value = 0x0002;
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x04, 1, &Value);
DBG("EHCI cmd 2 written\n");
Base = 0;
Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, 0x10, 1, &Base);
if (*((UINT8*)(UINTN)Base) < 0x0C) {
DBG("Config space too small: no legacy implementation\n");
break;
}
DBG("EHCI Base=%08hX\n", Base);
// opaddr = Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0)
opaddr = Base + *((UINT8*)(UINTN)(Base));
// eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8
@ -290,12 +293,20 @@ DBG("FixOwnership() -> begin\n");
//
// Found the XHCI, then disable the legacy support, if present
//
DBG("USB XHCI reset for device %04hX\n", Pci.Hdr.DeviceId);
if (Pci.Hdr.VendorId == 0x1106) {
//ну ее нах эту ВИА
DBG("skip XHCI controller from VIA\n");
break;
}
Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint32, 0 /* BAR0 */, (UINT64) 0x10 /* HCCPARAMS1 */, 1, &HcCapParams);
ExtendCap = EFI_ERROR(Status) ? 0 : ((HcCapParams >> 14) & 0x3FFFC);
MsgLog("ExtendCap=%08hX\n", ExtendCap);
while (ExtendCap) {
Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint32, 0 /* BAR0 */, (UINT64) ExtendCap, 1, &Value);
if (EFI_ERROR(Status))
break;
MsgLog(" Value=%08hX\n", Value);
if ((Value & 0xFF) == 1) {
//
// Do nothing if Bios Ownership clear
@ -341,6 +352,7 @@ DBG("FixOwnership() -> begin\n");
}
}
}
else break;
}
} else {
return Status;

7
rEFIt_UEFI/refit/main.cpp
View File

@ -638,6 +638,7 @@ void debugStartImageWithOC()
OC_STRING_ASSIGN(mOpenCoreConfiguration.Misc.Boot.PickerMode, "Builtin");
OC_STRING_ASSIGN(mOpenCoreConfiguration.Misc.Security.DmgLoading, "Any");
mOpenCoreConfiguration.Uefi.Quirks.IgnoreInvalidFlexRatio = 0;
mOpenCoreConfiguration.Uefi.Quirks.TscSyncTimeout = 0;
OcMain(&mOpenCoreStorage, NULL);
@ -1019,13 +1020,17 @@ void LOADER_ENTRY::StartLoader()
mOpenCoreConfiguration.Booter.Quirks.RebuildAppleMemoryMap = gSettings.Quirks.OcBooterQuirks.RebuildAppleMemoryMap;
mOpenCoreConfiguration.Booter.Quirks.ResizeAppleGpuBars = gSettings.Quirks.OcBooterQuirks.ResizeAppleGpuBars;
mOpenCoreConfiguration.Booter.Quirks.SetupVirtualMap = gSettings.Quirks.OcBooterQuirks.SetupVirtualMap;
mOpenCoreConfiguration.Booter.Quirks.SignalAppleOS = gSettings.Quirks.OcBooterQuirks.SignalAppleOS;
mOpenCoreConfiguration.Booter.Quirks.SignalAppleOS = false; //gSettings.Quirks.OcBooterQuirks.SignalAppleOS;
mOpenCoreConfiguration.Booter.Quirks.SyncRuntimePermissions = gSettings.Quirks.OcBooterQuirks.SyncRuntimePermissions;
#endif
FillOCCpuInfo(&mOpenCoreCpuInfo);
//test
if (gSettings.Quirks.OcBooterQuirks.SignalAppleOS) mOpenCoreConfiguration.Uefi.Quirks.TscSyncTimeout = 750000;
else mOpenCoreConfiguration.Uefi.Quirks.TscSyncTimeout = 0;
// if OC is NOT initialized with OcMain, we need the following
// OcLoadBooterUefiSupport(&mOpenCoreConfiguration);