Remove macro from Platform.h.

This commit is contained in:
jief 2020-04-16 12:09:22 +03:00
parent 89933f64ac
commit 9dc66aee39
45 changed files with 848 additions and 868 deletions

View File

@ -74,6 +74,14 @@
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@ -152,7 +160,6 @@
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@ -187,7 +194,6 @@
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@ -312,7 +318,6 @@
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@ -410,7 +415,6 @@
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@ -501,7 +505,6 @@
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@ -597,7 +600,6 @@
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@ -682,7 +684,6 @@
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@ -778,7 +779,6 @@
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@ -875,6 +875,8 @@
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@ -939,7 +941,6 @@
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@ -974,7 +975,6 @@
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@ -1222,6 +1222,8 @@
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9AC77F2324176C04005CDD5C /* AmlGenerator.cpp */,
@ -1310,8 +1312,6 @@
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@ -1527,7 +1527,6 @@
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9AC7804324176C04005CDD5C /* string.h in Headers */,
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@ -1551,6 +1550,7 @@
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@ -1678,6 +1677,7 @@
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9AF415B6242CD75C00D2644C /* string.h in Headers */,
9AF415B8242CD75C00D2644C /* sse3_5_patcher.h in Headers */,
9AF415B9242CD75C00D2644C /* spd.h in Headers */,
9AF415BA242CD75C00D2644C /* IO.h in Headers */,
@ -1825,6 +1825,7 @@
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9AF41682242CDA5800D2644C /* ati.h in Headers */,
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9AF41693242CDA5800D2644C /* string.h in Headers */,
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9AF41696242CDA5800D2644C /* spd.h in Headers */,
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9AC7802024176C04005CDD5C /* string.cpp in Sources */,
9AC7809124176C04005CDD5C /* XStringW.cpp in Sources */,
9AC7806924176C04005CDD5C /* lockedgraphics.cpp in Sources */,
9A28CC97241AB34800F3D247 /* XString_test.cpp in Sources */,
@ -2151,6 +2150,7 @@
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9AC7802624176C04005CDD5C /* gma.cpp in Sources */,
@ -2211,6 +2211,7 @@
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9ACFE6C724309AF80071CC93 /* panic.cpp in Sources */,
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9ACFE6CA24309AF80071CC93 /* tool.cpp in Sources */,
@ -2250,7 +2251,6 @@
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9ACFE6EF24309AF80071CC93 /* LegacyBiosThunk.cpp in Sources */,
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9ACFE6F124309AF80071CC93 /* string.cpp in Sources */,
9ACFE6F224309AF80071CC93 /* XStringW.cpp in Sources */,
9A9AEB9F243F7B9200FBD7D8 /* XStringArray.cpp in Sources */,
9ACFE6F324309AF80071CC93 /* lockedgraphics.cpp in Sources */,
@ -2323,6 +2323,7 @@
9AF415FA242CD75C00D2644C /* Events.cpp in Sources */,
9AF415FB242CD75C00D2644C /* libscreen.cpp in Sources */,
9AF415FC242CD75C00D2644C /* strlen_test.cpp in Sources */,
9A105B86244852D70006DE06 /* VersionString.cpp in Sources */,
9AF415FD242CD75C00D2644C /* panic.cpp in Sources */,
9AF415FF242CD75C00D2644C /* XStringW_test.cpp in Sources */,
9AF41600242CD75C00D2644C /* tool.cpp in Sources */,
@ -2361,7 +2362,6 @@
9AF41624242CD75C00D2644C /* REFIT_MENU_SCREEN.cpp in Sources */,
9AF41625242CD75C00D2644C /* LegacyBiosThunk.cpp in Sources */,
9A09863224389A6A00826276 /* menu.cpp in Sources */,
9AF41627242CD75C00D2644C /* string.cpp in Sources */,
9AF41628242CD75C00D2644C /* XStringW.cpp in Sources */,
9AF41629242CD75C00D2644C /* lockedgraphics.cpp in Sources */,
9A9AEB9D243F7B9000FBD7D8 /* XStringArray.cpp in Sources */,
@ -2435,6 +2435,7 @@
9AF416D7242CDA5800D2644C /* Events.cpp in Sources */,
9AF416D8242CDA5800D2644C /* libscreen.cpp in Sources */,
9AF416D9242CDA5800D2644C /* strlen_test.cpp in Sources */,
9A105B87244852D70006DE06 /* VersionString.cpp in Sources */,
9AF416DA242CDA5800D2644C /* panic.cpp in Sources */,
9AF416DC242CDA5800D2644C /* XStringW_test.cpp in Sources */,
9AF416DD242CDA5800D2644C /* tool.cpp in Sources */,
@ -2473,7 +2474,6 @@
9AF41701242CDA5800D2644C /* REFIT_MENU_SCREEN.cpp in Sources */,
9AF41702242CDA5800D2644C /* LegacyBiosThunk.cpp in Sources */,
9A09863324389A6A00826276 /* menu.cpp in Sources */,
9AF41704242CDA5800D2644C /* string.cpp in Sources */,
9AF41705242CDA5800D2644C /* XStringW.cpp in Sources */,
9AF41706242CDA5800D2644C /* lockedgraphics.cpp in Sources */,
9A9AEB9E243F7B9100FBD7D8 /* XStringArray.cpp in Sources */,

View File

@ -25,6 +25,8 @@
#include "smbios.h"
#include "cpu.h"
#define EBDA_BASE_ADDRESS 0x40E
#define HPET_SIGN SIGNATURE_32('H','P','E','T')
#define APIC_SIGN SIGNATURE_32('A','P','I','C')
#define MCFG_SIGN SIGNATURE_32('M','C','F','G')

View File

@ -38,6 +38,39 @@ struct aml_chunk
typedef struct aml_chunk AML_CHUNK;
#define AML_CHUNK_NONE 0xff
#define AML_CHUNK_ZERO 0x00
#define AML_CHUNK_ONE 0x01
#define AML_CHUNK_ALIAS 0x06
#define AML_CHUNK_NAME 0x08
#define AML_CHUNK_BYTE 0x0A
#define AML_CHUNK_WORD 0x0B
#define AML_CHUNK_DWORD 0x0C
#define AML_CHUNK_STRING 0x0D
#define AML_CHUNK_QWORD 0x0E
#define AML_CHUNK_SCOPE 0x10
#define AML_CHUNK_PACKAGE 0x12
#define AML_CHUNK_METHOD 0x14
#define AML_CHUNK_RETURN 0xA4
#define AML_LOCAL0 0x60
#define AML_STORE_OP 0x70
//-----------------------------------
// defines added by pcj
#define AML_CHUNK_BUFFER 0x11
#define AML_CHUNK_STRING_BUFFER 0x15
#define AML_CHUNK_OP 0x5B
#define AML_CHUNK_REFOF 0x71
#define AML_CHUNK_DEVICE 0x82
#define AML_CHUNK_LOCAL0 0x60
#define AML_CHUNK_LOCAL1 0x61
#define AML_CHUNK_LOCAL2 0x62
#define AML_CHUNK_ARG0 0x68
#define AML_CHUNK_ARG1 0x69
#define AML_CHUNK_ARG2 0x6A
#define AML_CHUNK_ARG3 0x6B
BOOLEAN aml_add_to_parent(AML_CHUNK* parent, AML_CHUNK* node);
AML_CHUNK* aml_create_node(AML_CHUNK* parent);
VOID aml_destroy_node(AML_CHUNK* node);

View File

@ -13,7 +13,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "Platform.h"
//#include "InternalBdsLib.h"
#include "../include/Handle.h"
/**

View File

@ -16,6 +16,18 @@ extern "C" {
} // extern "C"
#endif
//#define SAFE_LOG_SIZE 80
//#define MSG_LOG_SIZE (256 * 1024)
#define PREBOOT_LOG L"EFI\\CLOVER\\misc\\preboot.log"
#define LEGBOOT_LOG L"EFI\\CLOVER\\misc\\legacy_boot.log"
#define BOOT_LOG L"EFI\\CLOVER\\misc\\boot.log"
#define SYSTEM_LOG L"EFI\\CLOVER\\misc\\system.log"
#define DEBUG_LOG L"EFI\\CLOVER\\misc\\debug.log"
//#define PREWAKE_LOG L"EFI\\CLOVER\\misc\\prewake.log"
VOID
InitBooterLog (VOID);

View File

@ -43,7 +43,6 @@
#include "smbios.h"
#include "cpu.h"
#include <Guid/DataHubRecords.h>
#define EFI_CPU_DATA_MAXIMUM_LENGTH 0x100

View File

@ -29,6 +29,26 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define DBG(...)
#endif
////
//// Max bytes needed to represent ID of a SCSI device
////
//#define EFI_SCSI_TARGET_MAX_BYTES (0x10)
////
//// bit5..7 are for Logical unit number
//// 11100000b (0xe0)
////
//#define EFI_SCSI_LOGICAL_UNIT_NUMBER_MASK 0xe0
//
// Scsi Command Length
//
#define EFI_SCSI_OP_LENGTH_SIX 0x6
//#define EFI_SCSI_OP_LENGTH_TEN 0xa
//#define EFI_SCSI_OP_LENGTH_SIXTEEN 0x10
EFI_EVENT mVirtualAddressChangeEvent = NULL;
EFI_EVENT OnReadyToBootEvent = NULL;
EFI_EVENT ExitBootServiceEvent = NULL;

View File

@ -10,6 +10,9 @@
#include "StateGenerator.h"
#include "AcpiPatcher.h"
#include "cpu.h"
#include "../include/Pci.h"
#include "../include/Devices.h"
extern "C" {
#include <IndustryStandard/PciCommand.h>

View File

@ -9,6 +9,45 @@
#define PLATFORM_FIXBIOSDSDT_H_
//DSDT fixes MASK
//0x00FF
#define FIX_DTGP bit(0)
#define FIX_WARNING bit(1)
#define FIX_SHUTDOWN bit(2)
#define FIX_MCHC bit(3)
#define FIX_HPET bit(4)
#define FIX_LPC bit(5)
#define FIX_IPIC bit(6)
#define FIX_SBUS bit(7)
//0xFF00
#define FIX_DISPLAY bit(8)
#define FIX_IDE bit(9)
#define FIX_SATA bit(10)
#define FIX_FIREWIRE bit(11)
#define FIX_USB bit(12)
#define FIX_LAN bit(13)
#define FIX_WIFI bit(14)
#define FIX_HDA bit(15)
//new bits 16-31 0xFFFF0000
//#define FIX_NEW_WAY bit(31) will be reused
#define FIX_DARWIN bit(16)
#define FIX_RTC bit(17)
#define FIX_TMR bit(18)
#define FIX_IMEI bit(19)
#define FIX_INTELGFX bit(20)
#define FIX_WAK bit(21)
#define FIX_UNUSED bit(22)
#define FIX_ADP1 bit(23)
#define FIX_PNLF bit(24)
#define FIX_S3D bit(25)
#define FIX_ACST bit(26)
#define FIX_HDMI bit(27)
#define FIX_REGIONS bit(28)
#define FIX_HEADERS bit(29)
#define FIX_MUTEX bit(30)
struct _oper_region {
CHAR8 Name[8];
UINT32 Address;

View File

@ -8,6 +8,10 @@
#ifndef PLATFORM_NVRAM_H_
#define PLATFORM_NVRAM_H_
#define NON_APPLE_SMC_SIGNATURE SIGNATURE_64('S','M','C','H','E','L','P','E')
extern EFI_GUID *gEfiBootDeviceGuid;
extern EFI_DEVICE_PATH_PROTOCOL *gEfiBootDeviceData;

View File

@ -11,86 +11,10 @@ Headers collection for procedures
//#define DEBUG_ALL 2
#include "Posix/posix.h"
#include "../include/Efi.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <Library/printf_lite.h>
#include <Uefi.h>
#include <Guid/Acpi.h>
#include <Guid/EventGroup.h>
#include <Guid/SmBios.h>
#include <Guid/Mps.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
#include <Library/DeviceTreeLib.h>
#include <Library/GenericBdsLib.h>
#include <Library/HiiLib.h>
#include <Library/HdaModels.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
#include <Library/PerformanceLib.h>
#include <Library/PeCoffGetEntryPointLib.h>
#include <Library/TimerLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/UefiRuntimeLib.h>
#include <Library/UsbMass.h>
#include <Library/VideoBiosPatchLib.h>
#include <Library/MemLogLib.h>
#include <Library/WaveLib.h>
#include <Framework/FrameworkInternalFormRepresentation.h>
#include <IndustryStandard/Acpi10.h>
#include <IndustryStandard/Acpi20.h>
#include <IndustryStandard/Atapi.h>
#include <IndustryStandard/AppleHid.h>
#include <IndustryStandard/AppleSmBios.h>
#include <IndustryStandard/AppleFeatures.h>
#include <IndustryStandard/Bmp.h>
#include <IndustryStandard/HdaCodec.h>
#include <Protocol/PciIo.h>
#include <Protocol/AudioIo.h>
#include <Protocol/Cpu.h>
#include <Protocol/CpuIo.h>
#include <Protocol/DataHub.h>
#include <Protocol/DevicePathToText.h>
#include <Protocol/EdidDiscovered.h>
#include <Protocol/EdidOverride.h>
#include <Protocol/FrameworkHii.h>
#include <Protocol/HdaIo.h>
#include <Protocol/SimplePointer.h>
#include <Protocol/Smbios.h>
#include <Protocol/VariableWrite.h>
#include <Protocol/Variable.h>
#include <Protocol/UgaDraw.h>
#include <Protocol/FSInjectProtocol.h>
#include <Protocol/MsgLog.h>
#include <Protocol/efiConsoleControl.h>
#include <Protocol/EmuVariableControl.h>
#include <Protocol/AppleSMC.h>
#include <Protocol/AppleImageCodecProtocol.h>
#ifdef __cplusplus
}
#endif
// cpp_foundation objects has to be included before lib.h
#ifdef __cplusplus
#include "../cpp_foundation/XString.h"
#include "../cpp_foundation/XStringW.h"
#include "../cpp_foundation/XArray.h"
@ -98,98 +22,19 @@ extern "C" {
#include "../cpp_util/remove_ref.h"
#endif
#include "../include/OneLinerMacros.h"
#include "../entry_scan/common.h"
#include "../libeg/BmLib.h"
#include "BootLog.h"
#include "BasicIO.h"
#include "../refit/lib.h"
#include "../refit/screen.h" // for PauseForKey
#include "string.h"
#include "boot.h"
#include "plist.h"
//#include "PiBootMode.h"
#include "VersionString.h"
#include "Settings.h"
#ifndef CLOVERAPPLICATION
#include "../refit/IO.h"
#endif
#include "device_inject.h"
#ifdef __cplusplus
#include "kext_inject.h"
//#include "entry_scan.h"
#endif
#include "Settings.h"
#define CLOVER_SIGN SIGNATURE_32('C','l','v','r')
#define NON_APPLE_SMC_SIGNATURE SIGNATURE_64('S','M','C','H','E','L','P','E')
#define PCAT_RTC_ADDRESS_REGISTER 0x70
#define PCAT_RTC_DATA_REGISTER 0x71
#ifdef _MSC_VER
#define __typeof__(x) decltype(x)
#endif
#define __typeof_am__(x) remove_ref<decltype(x)>::type
/* XML Tags */
#define kXMLTagPList "plist"
#define kXMLTagDict "dict"
#define kXMLTagKey "key"
#define kXMLTagString "string"
#define kXMLTagInteger "integer"
#define kXMLTagData "data"
#define kXMLTagDate "date"
#define kXMLTagFalse "false/"
#define kXMLTagTrue "true/"
#define kXMLTagArray "array"
#define kXMLTagReference "reference"
#define kXMLTagID "ID="
#define kXMLTagIDREF "IDREF="
#define MAX_NUM_DEVICES 64
#define HEIGHT_2K 1100
/* Decimal powers: */
#define kilo (1000ULL)
#define Mega (kilo * kilo)
#define Giga (kilo * Mega)
#define Tera (kilo * Giga)
#define Peta (kilo * Tera)
#define EBDA_BASE_ADDRESS 0x40E
#define EFI_SYSTEM_TABLE_MAX_ADDRESS 0xFFFFFFFF
#define ROUND_PAGE(x) ((((unsigned)(x)) + EFI_PAGE_SIZE - 1) & ~(EFI_PAGE_SIZE - 1))
//
// Max bytes needed to represent ID of a SCSI device
//
#define EFI_SCSI_TARGET_MAX_BYTES (0x10)
//
// bit5..7 are for Logical unit number
// 11100000b (0xe0)
//
#define EFI_SCSI_LOGICAL_UNIT_NUMBER_MASK 0xe0
//
// Scsi Command Length
//
#define EFI_SCSI_OP_LENGTH_SIX 0x6
#define EFI_SCSI_OP_LENGTH_TEN 0xa
#define EFI_SCSI_OP_LENGTH_SIXTEEN 0x10
//#define SAFE_LOG_SIZE 80
#define MSG_LOG_SIZE (256 * 1024)
#define PREBOOT_LOG L"EFI\\CLOVER\\misc\\preboot.log"
#define LEGBOOT_LOG L"EFI\\CLOVER\\misc\\legacy_boot.log"
#define BOOT_LOG L"EFI\\CLOVER\\misc\\boot.log"
#define SYSTEM_LOG L"EFI\\CLOVER\\misc\\system.log"
#define DEBUG_LOG L"EFI\\CLOVER\\misc\\debug.log"
#define PREWAKE_LOG L"EFI\\CLOVER\\misc\\prewake.log"
#ifndef DEBUG_ALL
#define MsgLog(...) DebugLog(1, __VA_ARGS__)
@ -197,481 +42,5 @@ extern "C" {
#define MsgLog(...) DebugLog(DEBUG_ALL, __VA_ARGS__)
#endif
#define CPU_MODEL_PENTIUM_M 0x09
#define CPU_MODEL_DOTHAN 0x0D
#define CPU_MODEL_YONAH 0x0E
#define CPU_MODEL_MEROM 0x0F /* same as CONROE but mobile */
#define CPU_MODEL_CONROE 0x0F /* Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton */
#define CPU_MODEL_CELERON 0x16 /* ever see? */
#define CPU_MODEL_PENRYN 0x17 /* Yorkfield, Harpertown, Penryn M */
#define CPU_MODEL_WOLFDALE 0x17 /* kind of penryn but desktop */
#define CPU_MODEL_NEHALEM 0x1A /* Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown */
#define CPU_MODEL_ATOM 0x1C /* Pineview UN */
#define CPU_MODEL_XEON_MP 0x1D /* MP 7400 UN */
#define CPU_MODEL_FIELDS 0x1E /* Lynnfield, Clarksfield, Jasper */
#define CPU_MODEL_DALES 0x1F /* Havendale, Auburndale */
#define CPU_MODEL_CLARKDALE 0x25 /* Clarkdale, Arrandale */
#define CPU_MODEL_ATOM_SAN 0x26 /* Haswell H ? */
#define CPU_MODEL_LINCROFT 0x27 /* UN */
#define CPU_MODEL_SANDY_BRIDGE 0x2A
#define CPU_MODEL_WESTMERE 0x2C /* Gulftown LGA1366 */
#define CPU_MODEL_JAKETOWN 0x2D /* Sandy Bridge Xeon LGA2011 */
#define CPU_MODEL_NEHALEM_EX 0x2E
#define CPU_MODEL_WESTMERE_EX 0x2F
#define CPU_MODEL_ATOM_Z8000 0x35
#define CPU_MODEL_ATOM_2000 0x36 /* UN */
#define CPU_MODEL_ATOM_3700 0x37 /* Bay Trail */
#define CPU_MODEL_IVY_BRIDGE 0x3A
#define CPU_MODEL_HASWELL 0x3C /* Haswell DT */
#define CPU_MODEL_HASWELL_U5 0x3D /* Haswell U5 5th generation Broadwell*/
#define CPU_MODEL_IVY_BRIDGE_E5 0x3E /* Ivy Bridge Xeon UN */
#define CPU_MODEL_HASWELL_E 0x3F /* Haswell Extreme */
//#define CPU_MODEL_HASWELL_H 0x?? // Haswell H
#define CPU_MODEL_HASWELL_ULT 0x45 /* Haswell ULT */
#define CPU_MODEL_CRYSTALWELL 0x46 /* Haswell ULX CPUID_MODEL_CRYSTALWELL */
#define CPU_MODEL_BROADWELL_HQ 0x47 /* E3-1200 v4 */
#define CPU_MODEL_MERRIFIELD 0x4A /* Tangier */
#define CPU_MODEL_AIRMONT 0x4C /* CherryTrail / Braswell */
#define CPU_MODEL_AVOTON 0x4D /* Avaton/Rangely */
#define CPU_MODEL_SKYLAKE_U 0x4E /* Skylake Mobile */
#define CPU_MODEL_BROADWELL_E5 0x4F /* Xeon E5-2695 */
#define CPU_MODEL_SKYLAKE_S 0x55 /* Skylake Server, Cooper Lake */
#define CPU_MODEL_BROADWELL_DE 0x56 /* Xeon BroadWell */
#define CPU_MODEL_KNIGHT 0x57 /* Knights Landing */
#define CPU_MODEL_MOOREFIELD 0x5A /* Annidale */
#define CPU_MODEL_GOLDMONT 0x5C /* Apollo Lake */
#define CPU_MODEL_ATOM_X3 0x5D /* Silvermont */
#define CPU_MODEL_SKYLAKE_D 0x5E /* Skylake Desktop */
#define CPU_MODEL_DENVERTON 0x5F /* Goldmont Microserver */
#define CPU_MODEL_CANNONLAKE 0x66
#define CPU_MODEL_ICELAKE_A 0x6A /* Xeon Ice Lake */
#define CPU_MODEL_ICELAKE_C 0x6C /* Xeon Ice Lake */
#define CPU_MODEL_ATOM_GM 0x7A /* Goldmont Plus */
#define CPU_MODEL_ICELAKE_D 0x7D
#define CPU_MODEL_ICELAKE 0x7E
#define CPU_MODEL_XEON_MILL 0x85 /* Knights Mill */
#define CPU_MODEL_ATOM_TM 0x86 /* Tremont */
#define CPU_MODEL_KABYLAKE1 0x8E /* Kabylake Mobile */
#define CPU_MODEL_KABYLAKE2 0x9E /* Kabylake Dektop, CoffeeLake */
#define CPU_MODEL_COMETLAKE_S 0x9F /* desktop Comet Lake */
#define CPU_MODEL_COMETLAKE_Y 0xA5 /* aka 10th generation Amber Lake Y */
#define CPU_MODEL_COMETLAKE_U 0xA6
#define CPU_VENDOR_INTEL 0x756E6547
#define CPU_VENDOR_AMD 0x68747541
/* Unknown CPU */
#define CPU_STRING_UNKNOWN "Unknown CPU Type"
//definitions from Apple XNU
/* CPU defines */
#define bit(n) (1UL << (n))
#define _Bit(n) (1ULL << (n))
#define _HBit(n) (1ULL << ((n)+32))
#define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
#define bitfield(x,h,l) RShiftU64(((x) & bitmask((h),(l))), (l))
#define quad(hi,lo) ((LShiftU64((hi), 32) | (lo)))
/*
* The CPUID_FEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 1:
*/
#define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */
#define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */
#define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */
#define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */
#define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */
#define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */
#define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */
#define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */
#define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */
#define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */
#define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */
#define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */
#define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */
#define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */
#define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */
#define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */
#define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */
#define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DS _Bit(21) /* Debug Store */
#define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */
#define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */
#define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */
#define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */
#define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */
#define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ Instruction */
#define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */
#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
#define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */
#define CPUID_FEATURE_VMX _HBit(5) /* VMX */
#define CPUID_FEATURE_SMX _HBit(6) /* SMX */
#define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_xAPIC _HBit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */
#define CPUID_FEATURE_AVX1_0 _HBit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_RDRAND _HBit(29) /* RDRAND instruction */
#define CPUID_FEATURE_F16C _HBit(30) /* Float16 convert instructions */
#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
/*
* Leaf 7, subleaf 0 additional features.
* Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
*/
#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0) /* FS/GS base read/write */
#define CPUID_LEAF7_FEATURE_SMEP _Bit(7) /* Supervisor Mode Execute Protect */
#define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9) /* ENhanced Fast STRinG copy */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
*/
#define CPUID_EXTFEATURE_SYSCALL _Bit(11) /* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XD _Bit(20) /* eXecute Disable */
#define CPUID_EXTFEATURE_1GBPAGE _Bit(26) /* 1G-Byte Page support */
#define CPUID_EXTFEATURE_RDTSCP _Bit(27) /* RDTSCP */
#define CPUID_EXTFEATURE_EM64T _Bit(29) /* Extended Mem 64 Technology */
//#define CPUID_EXTFEATURE_LAHF _HBit(20) /* LAFH/SAHF instructions */
// New definition with Snow kernel
#define CPUID_EXTFEATURE_LAHF _HBit(0) /* LAHF/SAHF instructions */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
*/
#define CPUID_EXTFEATURE_TSCI _Bit(8) /* TSC Invariant */
#define CPUID_CACHE_SIZE 16 /* Number of descriptor values */
#define CPUID_MWAIT_EXTENSION _Bit(0) /* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAK _Bit(1) /* interrupts are break events */
/* Known MSR registers */
#define MSR_IA32_PLATFORM_ID 0x0017
#define IA32_APIC_BASE 0x001B /* used also for AMD */
#define MSR_CORE_THREAD_COUNT 0x0035 /* limited use - not for Penryn or older */
#define IA32_TSC_ADJUST 0x003B
#define MSR_IA32_BIOS_SIGN_ID 0x008B /* microcode version */
#define MSR_FSB_FREQ 0x00CD /* limited use - not for i7 */
/*
101B: 100 MHz (FSB 400)
001B: 133 MHz (FSB 533)
011B: 167 MHz (FSB 667)
010B: 200 MHz (FSB 800)
000B: 267 MHz (FSB 1067)
100B: 333 MHz (FSB 1333)
110B: 400 MHz (FSB 1600)
*/
// T8300 -> 0x01A2 => 200MHz
#define MSR_PLATFORM_INFO 0x00CE /* limited use - MinRatio for i7 but Max for Yonah */
/* turbo for penryn */
//haswell
//Low Frequency Mode. LFM is Pn in the P-state table. It can be read at MSR CEh [47:40].
//Minimum Frequency Mode. MFM is the minimum ratio supported by the processor and can be read from MSR CEh [55:48].
#define MSR_PKG_CST_CONFIG_CONTROL 0x00E2 /* sandy and up */
#define MSR_PMG_IO_CAPTURE_BASE 0x00E4 /* sandy and up */
#define IA32_MPERF 0x00E7 /* TSC in C0 only */
#define IA32_APERF 0x00E8 /* actual clocks in C0 */
#define MSR_IA32_EXT_CONFIG 0x00EE /* limited use - not for i7 */
#define MSR_FLEX_RATIO 0x0194 /* limited use - not for Penryn or older */
//see no value on most CPUs
#define MSR_IA32_PERF_STATUS 0x0198
#define MSR_IA32_PERF_CONTROL 0x0199
#define MSR_IA32_CLOCK_MODULATION 0x019A
#define MSR_THERMAL_STATUS 0x019C
#define MSR_IA32_MISC_ENABLE 0x01A0
#define MSR_THERMAL_TARGET 0x01A2 /* TjMax limited use - not for Penryn or older */
#define MSR_TURBO_RATIO_LIMIT 0x01AD /* limited use - not for Penryn or older */
#define IA32_ENERGY_PERF_BIAS 0x01B0
//MSR 000001B0 0000-0000-0000-0005
#define MSR_PACKAGE_THERM_STATUS 0x01B1
//MSR 000001B1 0000-0000-8838-0000
#define IA32_PLATFORM_DCA_CAP 0x01F8
//MSR 000001FC 0000-0000-0004-005F
// Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.
#define MSR_RAPL_POWER_UNIT 0x606 /* R/O */
//MSR 00000606 0000-0000-000A-1003
#define MSR_PKGC3_IRTL 0x60A /* RW time limit to go C3 */
// bit 15 = 1 -- the value valid for C-state PM
#define MSR_PKGC6_IRTL 0x60B /* RW time limit to go C6 */
//MSR 0000060B 0000-0000-0000-8854
//Valid + 010=1024ns + 0x54=84mks
#define MSR_PKGC7_IRTL 0x60C /* RW time limit to go C7 */
//MSR 0000060C 0000-0000-0000-8854
#define MSR_PKG_C2_RESIDENCY 0x60D /* same as TSC but in C2 only */
#define MSR_PKG_RAPL_POWER_LIMIT 0x610
//MSR 00000610 0000-A580-0000-8960
#define MSR_PKG_ENERGY_STATUS 0x611
//MSR 00000611 0000-0000-3212-A857
#define MSR_PKG_POWER_INFO 0x614
//MSR 00000614 0000-0000-01E0-02F8
// Sandy Bridge IA (Core) domain MSR's.
#define MSR_PP0_POWER_LIMIT 0x638
#define MSR_PP0_ENERGY_STATUS 0x639
#define MSR_PP0_POLICY 0x63A
#define MSR_PP0_PERF_STATUS 0x63B
// Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).
#define MSR_PP1_POWER_LIMIT 0x640
#define MSR_PP1_ENERGY_STATUS 0x641
//MSR 00000641 0000-0000-0000-0000
#define MSR_PP1_POLICY 0x642
// JakeTown only Memory MSR's.
#define MSR_PKG_PERF_STATUS 0x613
#define MSR_DRAM_POWER_LIMIT 0x618
#define MSR_DRAM_ENERGY_STATUS 0x619
#define MSR_DRAM_PERF_STATUS 0x61B
#define MSR_DRAM_POWER_INFO 0x61C
//IVY_BRIDGE
#define MSR_CONFIG_TDP_NOMINAL 0x648
#define MSR_CONFIG_TDP_LEVEL1 0x649
#define MSR_CONFIG_TDP_LEVEL2 0x64A
#define MSR_CONFIG_TDP_CONTROL 0x64B /* write once to lock */
#define MSR_TURBO_ACTIVATION_RATIO 0x64C
//Skylake
#define BASE_ART_CLOCK_SOURCE 24000000ULL /* 24Mhz */
#define MSR_IA32_PM_ENABLE 0x770
#define MSR_IA32_HWP_REQUEST 0x774
//AMD
#define K8_FIDVID_STATUS 0xC0010042
#define K10_COFVID_LIMIT 0xC0010061 /* max enabled p-state (msr >> 4) & 7 */
#define K10_COFVID_CONTROL 0xC0010062 /* switch to p-state */
#define K10_PSTATE_STATUS 0xC0010064
#define K10_COFVID_STATUS 0xC0010071 /* current p-state (msr >> 16) & 7 */
/* specific settings
static void SavePState(unsigned int index, unsigned int lowMsr, unsigned int core)
{
CONST unsigned int msrIndex = 0xC0010064u + index;
CONST DWORD_PTR affinityMask = (DWORD_PTR)1 << core;
DWORD lower, higher;
RdmsrTx(msrIndex, &lower, &higher, affinityMask);
CONST DWORD lowMsrMask = 0xFE40FFFFu;
lower = (lower & ~lowMsrMask) | (lowMsr & lowMsrMask);
WrmsrTx(msrIndex, lower, higher, affinityMask);
}
MSR C0010064 8000-0185-0000-1418 [20.00x] [1.4250 V] [13.30 A] [PState Pb0]
MSR C0010065 8000-0185-0000-1615 [18.50x] [1.4125 V] [13.30 A] [PState Pb1]
MSR C0010066 8000-0173-0000-1A1A [21.00x] [1.3875 V] [11.50 A] [PState P0]
MSR C0010067 0000-0173-0000-1A1A
MSR C0010068 0000-0173-0000-181A
MSR C0010069 0000-0173-0000-1A1A
MSR C001006A 8000-0125-0000-604C [ 7.00x] [0.9500 V] [ 3.70 A] [PState P1]
MSR C001006B 0000-0000-0000-0000
*/
#define DEFAULT_FSB 100000 /* for now, hardcoding 100MHz for old CPUs */
/* CPUID Index */
#define CPUID_0 0
#define CPUID_1 1
#define CPUID_2 2
#define CPUID_3 3
#define CPUID_4 4
#define CPUID_5 5
#define CPUID_6 6
#define CPUID_80 7
#define CPUID_81 8
#define CPUID_87 9
#define CPUID_88 10
#define CPUID_81E 11
#define CPUID_15 15
#define CPUID_MAX 16
/* CPU Cache */
#define MAX_CACHE_COUNT 4
#define CPU_CACHE_LEVEL 3
/* PCI */
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
#define PCI_CLASS_MEDIA_HDA 0x03
#define GEN_PMCON_1 0xA0
#define PCIADDR(bus, dev, func) ((1 << 31) | ((bus) << 16) | ((dev) << 11) | ((func) << 8))
#define REG8(base, reg) ((volatile UINT8 *)(UINTN)(base))[(reg)]
#define REG16(base, reg) ((volatile UINT16 *)(UINTN)(base))[(reg) >> 1]
//#define REG32(base, reg) ((volatile UINT32 *)(UINTN)(base))[(reg) >> 2]
#define REG32(base, reg) (*(volatile UINT32 *)((UINTN)base + reg))
#define WRITEREG32(base, reg, value) REG32((base), (reg)) = value
#define EFI_HANDLE_TYPE_UNKNOWN 0x000
#define EFI_HANDLE_TYPE_IMAGE_HANDLE 0x001
#define EFI_HANDLE_TYPE_DRIVER_BINDING_HANDLE 0x002
#define EFI_HANDLE_TYPE_DEVICE_DRIVER 0x004
#define EFI_HANDLE_TYPE_BUS_DRIVER 0x008
#define EFI_HANDLE_TYPE_DRIVER_CONFIGURATION_HANDLE 0x010
#define EFI_HANDLE_TYPE_DRIVER_DIAGNOSTICS_HANDLE 0x020
#define EFI_HANDLE_TYPE_COMPONENT_NAME_HANDLE 0x040
#define EFI_HANDLE_TYPE_DEVICE_HANDLE 0x080
#define EFI_HANDLE_TYPE_PARENT_HANDLE 0x100
#define EFI_HANDLE_TYPE_CONTROLLER_HANDLE 0x200
#define EFI_HANDLE_TYPE_CHILD_HANDLE 0x400
#define AML_CHUNK_NONE 0xff
#define AML_CHUNK_ZERO 0x00
#define AML_CHUNK_ONE 0x01
#define AML_CHUNK_ALIAS 0x06
#define AML_CHUNK_NAME 0x08
#define AML_CHUNK_BYTE 0x0A
#define AML_CHUNK_WORD 0x0B
#define AML_CHUNK_DWORD 0x0C
#define AML_CHUNK_STRING 0x0D
#define AML_CHUNK_QWORD 0x0E
#define AML_CHUNK_SCOPE 0x10
#define AML_CHUNK_PACKAGE 0x12
#define AML_CHUNK_METHOD 0x14
#define AML_CHUNK_RETURN 0xA4
#define AML_LOCAL0 0x60
#define AML_STORE_OP 0x70
//-----------------------------------
// defines added by pcj
#define AML_CHUNK_BUFFER 0x11
#define AML_CHUNK_STRING_BUFFER 0x15
#define AML_CHUNK_OP 0x5B
#define AML_CHUNK_REFOF 0x71
#define AML_CHUNK_DEVICE 0x82
#define AML_CHUNK_LOCAL0 0x60
#define AML_CHUNK_LOCAL1 0x61
#define AML_CHUNK_LOCAL2 0x62
#define AML_CHUNK_ARG0 0x68
#define AML_CHUNK_ARG1 0x69
#define AML_CHUNK_ARG2 0x6A
#define AML_CHUNK_ARG3 0x6B
//DSDT fixes MASK
//0x00FF
#define FIX_DTGP bit(0)
#define FIX_WARNING bit(1)
#define FIX_SHUTDOWN bit(2)
#define FIX_MCHC bit(3)
#define FIX_HPET bit(4)
#define FIX_LPC bit(5)
#define FIX_IPIC bit(6)
#define FIX_SBUS bit(7)
//0xFF00
#define FIX_DISPLAY bit(8)
#define FIX_IDE bit(9)
#define FIX_SATA bit(10)
#define FIX_FIREWIRE bit(11)
#define FIX_USB bit(12)
#define FIX_LAN bit(13)
#define FIX_WIFI bit(14)
#define FIX_HDA bit(15)
//new bits 16-31 0xFFFF0000
//#define FIX_NEW_WAY bit(31) will be reused
#define FIX_DARWIN bit(16)
#define FIX_RTC bit(17)
#define FIX_TMR bit(18)
#define FIX_IMEI bit(19)
#define FIX_INTELGFX bit(20)
#define FIX_WAK bit(21)
#define FIX_UNUSED bit(22)
#define FIX_ADP1 bit(23)
#define FIX_PNLF bit(24)
#define FIX_S3D bit(25)
#define FIX_ACST bit(26)
#define FIX_HDMI bit(27)
#define FIX_REGIONS bit(28)
#define FIX_HEADERS bit(29)
#define FIX_MUTEX bit(30)
//devices
#define DEV_ATI bit(0)
#define DEV_NVIDIA bit(1)
#define DEV_INTEL bit(2)
#define DEV_HDA bit(3)
#define DEV_HDMI bit(4)
#define DEV_LAN bit(5)
#define DEV_WIFI bit(6)
#define DEV_SATA bit(7)
#define DEV_IDE bit(8)
#define DEV_LPC bit(9)
#define DEV_SMBUS bit(10)
#define DEV_USB bit(11)
#define DEV_FIREWIRE bit(12)
#define DEV_MCHC bit(13)
#define DEV_IMEI bit(14)
#define DEV_BY_PCI bit(31)
#define NUM_OF_CONFIGS 3
// Kernel scan states
#define KERNEL_SCAN_ALL (0)
#define KERNEL_SCAN_NEWEST (1)
#define KERNEL_SCAN_OLDEST (2)
#define KERNEL_SCAN_FIRST (3)
#define KERNEL_SCAN_LAST (4)
#define KERNEL_SCAN_MOSTRECENT (5)
#define KERNEL_SCAN_EARLIEST (6)
#define KERNEL_SCAN_NONE (100)
// Secure boot policies
// Deny all images
#define SECURE_BOOT_POLICY_DENY (0)
// Allow all images
#define SECURE_BOOT_POLICY_ALLOW (1)
// Query the user to choose action
#define SECURE_BOOT_POLICY_QUERY (2)
// Insert signature into db
#define SECURE_BOOT_POLICY_INSERT (3)
// White list
#define SECURE_BOOT_POLICY_WHITELIST (4)
// Black list
#define SECURE_BOOT_POLICY_BLACKLIST (5)
// User policy, white and black list with query
#define SECURE_BOOT_POLICY_USER (6)
#include "BootLog.h"
#endif

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@ -20,8 +20,8 @@ extern "C" {
void abort(void)
{
DebugLog(2, "A fatal error happened. System halted\n");
while (1) { // tis will avoid warning : Function declared 'noreturn' should not return
DebugLog(2, "A fatal error happened. System halted\n");
while (1) { // tis will avoid warning : Function declared 'noreturn' should not return
CpuDeadLoop();
}
}
}

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@ -1,9 +1,20 @@
#ifndef __CLOVER_STRING_H__
#define __CLOVER_STRING_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <Library/BaseMemoryLib.h>
}
#ifdef __GNUC__
//void* memset(void* dst, int ch, UINT64 count) __attribute__ ((used));
void* memcpy(void *dst, const void *src, size_t len) __attribute__ ((used));
#else
// void* memset(void* dst, int ch, UINT64 count);
void* memcpy(void *dst, const void *src, size_t len);
#endif
inline void* memmove(void *dst, const void *src, size_t len)
{
@ -15,4 +26,9 @@ inline void* memcpy(void *dst, const void *src, size_t len)
return CopyMem(dst,src,len);
}
#ifdef __cplusplus
}
#endif
#endif

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@ -24,6 +24,11 @@
#include "cpu.h"
#include "APFS.h"
#include "hda.h"
#include "FixBiosDsdt.h"
#include "../entry_scan/secureboot.h"
#include "../include/Pci.h"
#include "../include/Devices.h"
#include "ati_reg.h"
#ifndef DEBUG_ALL
#define DEBUG_SET 1
@ -45,6 +50,10 @@
//EFI_GUID gRandomUUID = {0x0A0B0C0D, 0x0000, 0x1010, {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}};
#define NUM_OF_CONFIGS 3
#define GEN_PMCON_1 0xA0
INTN OldChosenTheme;
INTN OldChosenConfig;
INTN OldChosenDsdt;

View File

@ -1,6 +1,11 @@
#ifndef __SETTINGS_H__
#define __SETTINGS_H__
#define CLOVER_SIGN SIGNATURE_32('C','l','v','r')
#define HEIGHT_2K 1100
#include "../gui/menu_items/menu_items.h"
#include "../Platform/plist.h"
//// SysVariables
//typedef struct SYSVARIABLES SYSVARIABLES;

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@ -7,7 +7,11 @@
#include "Platform.h"
#include "ati.h"
#include "ati_reg.h"
#include "smbios.h"
#include "FixBiosDsdt.h"
#include "../include/Pci.h"
#include "../include/Devices.h"
#ifndef DEBUG_ALL
#define DEBUG_ATI 1

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@ -7,8 +7,11 @@
* big thank to Islam M. Ahmed Zaid for the updating the collection
*/
#include "Platform.h" //this include needed for Uefi types
#include "ati_reg.h"
//#include "Platform.h" //this include needed for Uefi types
//#include "ati_reg.h"
#include "../include/Pci.h"
#include "device_inject.h"
#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x6e
#define DATVAL(x) {kPtr, sizeof(x), (UINT8 *)x}

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@ -37,6 +37,7 @@
#include "Platform.h"
#include "cpu.h"
#include "smbios.h"
#include "kernel_patcher.h"
#ifndef DEBUG_ALL
#define DEBUG_CPU 1

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@ -10,6 +10,324 @@
#include "platformdata.h"
#define CPU_MODEL_PENTIUM_M 0x09
#define CPU_MODEL_DOTHAN 0x0D
#define CPU_MODEL_YONAH 0x0E
#define CPU_MODEL_MEROM 0x0F /* same as CONROE but mobile */
#define CPU_MODEL_CONROE 0x0F /* Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton */
#define CPU_MODEL_CELERON 0x16 /* ever see? */
#define CPU_MODEL_PENRYN 0x17 /* Yorkfield, Harpertown, Penryn M */
#define CPU_MODEL_WOLFDALE 0x17 /* kind of penryn but desktop */
#define CPU_MODEL_NEHALEM 0x1A /* Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown */
#define CPU_MODEL_ATOM 0x1C /* Pineview UN */
#define CPU_MODEL_XEON_MP 0x1D /* MP 7400 UN */
#define CPU_MODEL_FIELDS 0x1E /* Lynnfield, Clarksfield, Jasper */
#define CPU_MODEL_DALES 0x1F /* Havendale, Auburndale */
#define CPU_MODEL_CLARKDALE 0x25 /* Clarkdale, Arrandale */
#define CPU_MODEL_ATOM_SAN 0x26 /* Haswell H ? */
#define CPU_MODEL_LINCROFT 0x27 /* UN */
#define CPU_MODEL_SANDY_BRIDGE 0x2A
#define CPU_MODEL_WESTMERE 0x2C /* Gulftown LGA1366 */
#define CPU_MODEL_JAKETOWN 0x2D /* Sandy Bridge Xeon LGA2011 */
#define CPU_MODEL_NEHALEM_EX 0x2E
#define CPU_MODEL_WESTMERE_EX 0x2F
#define CPU_MODEL_ATOM_Z8000 0x35
#define CPU_MODEL_ATOM_2000 0x36 /* UN */
#define CPU_MODEL_ATOM_3700 0x37 /* Bay Trail */
#define CPU_MODEL_IVY_BRIDGE 0x3A
#define CPU_MODEL_HASWELL 0x3C /* Haswell DT */
#define CPU_MODEL_HASWELL_U5 0x3D /* Haswell U5 5th generation Broadwell*/
#define CPU_MODEL_IVY_BRIDGE_E5 0x3E /* Ivy Bridge Xeon UN */
#define CPU_MODEL_HASWELL_E 0x3F /* Haswell Extreme */
//#define CPU_MODEL_HASWELL_H 0x?? // Haswell H
#define CPU_MODEL_HASWELL_ULT 0x45 /* Haswell ULT */
#define CPU_MODEL_CRYSTALWELL 0x46 /* Haswell ULX CPUID_MODEL_CRYSTALWELL */
#define CPU_MODEL_BROADWELL_HQ 0x47 /* E3-1200 v4 */
#define CPU_MODEL_MERRIFIELD 0x4A /* Tangier */
#define CPU_MODEL_AIRMONT 0x4C /* CherryTrail / Braswell */
#define CPU_MODEL_AVOTON 0x4D /* Avaton/Rangely */
#define CPU_MODEL_SKYLAKE_U 0x4E /* Skylake Mobile */
#define CPU_MODEL_BROADWELL_E5 0x4F /* Xeon E5-2695 */
#define CPU_MODEL_SKYLAKE_S 0x55 /* Skylake Server, Cooper Lake */
#define CPU_MODEL_BROADWELL_DE 0x56 /* Xeon BroadWell */
#define CPU_MODEL_KNIGHT 0x57 /* Knights Landing */
#define CPU_MODEL_MOOREFIELD 0x5A /* Annidale */
#define CPU_MODEL_GOLDMONT 0x5C /* Apollo Lake */
#define CPU_MODEL_ATOM_X3 0x5D /* Silvermont */
#define CPU_MODEL_SKYLAKE_D 0x5E /* Skylake Desktop */
#define CPU_MODEL_DENVERTON 0x5F /* Goldmont Microserver */
#define CPU_MODEL_CANNONLAKE 0x66
#define CPU_MODEL_ICELAKE_A 0x6A /* Xeon Ice Lake */
#define CPU_MODEL_ICELAKE_C 0x6C /* Xeon Ice Lake */
#define CPU_MODEL_ATOM_GM 0x7A /* Goldmont Plus */
#define CPU_MODEL_ICELAKE_D 0x7D
#define CPU_MODEL_ICELAKE 0x7E
#define CPU_MODEL_XEON_MILL 0x85 /* Knights Mill */
#define CPU_MODEL_ATOM_TM 0x86 /* Tremont */
#define CPU_MODEL_KABYLAKE1 0x8E /* Kabylake Mobile */
#define CPU_MODEL_KABYLAKE2 0x9E /* Kabylake Dektop, CoffeeLake */
#define CPU_MODEL_COMETLAKE_S 0x9F /* desktop Comet Lake */
#define CPU_MODEL_COMETLAKE_Y 0xA5 /* aka 10th generation Amber Lake Y */
#define CPU_MODEL_COMETLAKE_U 0xA6
#define CPU_VENDOR_INTEL 0x756E6547
#define CPU_VENDOR_AMD 0x68747541
/* Unknown CPU */
#define CPU_STRING_UNKNOWN "Unknown CPU Type"
/* CPU defines */
/*
* The CPUID_FEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 1:
*/
#define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */
#define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */
#define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */
#define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */
#define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */
#define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */
#define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */
#define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */
#define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */
#define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */
#define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */
#define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */
#define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */
#define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */
#define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */
#define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */
#define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */
#define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DS _Bit(21) /* Debug Store */
#define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */
#define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */
#define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */
#define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */
#define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */
#define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ Instruction */
#define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */
#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
#define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */
#define CPUID_FEATURE_VMX _HBit(5) /* VMX */
#define CPUID_FEATURE_SMX _HBit(6) /* SMX */
#define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_xAPIC _HBit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */
#define CPUID_FEATURE_AVX1_0 _HBit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_RDRAND _HBit(29) /* RDRAND instruction */
#define CPUID_FEATURE_F16C _HBit(30) /* Float16 convert instructions */
#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
/*
* Leaf 7, subleaf 0 additional features.
* Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
*/
#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0) /* FS/GS base read/write */
#define CPUID_LEAF7_FEATURE_SMEP _Bit(7) /* Supervisor Mode Execute Protect */
#define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9) /* ENhanced Fast STRinG copy */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
*/
#define CPUID_EXTFEATURE_SYSCALL _Bit(11) /* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XD _Bit(20) /* eXecute Disable */
#define CPUID_EXTFEATURE_1GBPAGE _Bit(26) /* 1G-Byte Page support */
#define CPUID_EXTFEATURE_RDTSCP _Bit(27) /* RDTSCP */
#define CPUID_EXTFEATURE_EM64T _Bit(29) /* Extended Mem 64 Technology */
//#define CPUID_EXTFEATURE_LAHF _HBit(20) /* LAFH/SAHF instructions */
// New definition with Snow kernel
#define CPUID_EXTFEATURE_LAHF _HBit(0) /* LAHF/SAHF instructions */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
*/
#define CPUID_EXTFEATURE_TSCI _Bit(8) /* TSC Invariant */
#define CPUID_CACHE_SIZE 16 /* Number of descriptor values */
#define CPUID_MWAIT_EXTENSION _Bit(0) /* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAK _Bit(1) /* interrupts are break events */
/* Known MSR registers */
#define MSR_IA32_PLATFORM_ID 0x0017
//#define IA32_APIC_BASE 0x001B /* used also for AMD */
#define MSR_CORE_THREAD_COUNT 0x0035 /* limited use - not for Penryn or older */
//#define IA32_TSC_ADJUST 0x003B
#define MSR_IA32_BIOS_SIGN_ID 0x008B /* microcode version */
#define MSR_FSB_FREQ 0x00CD /* limited use - not for i7 */
/*
101B: 100 MHz (FSB 400)
001B: 133 MHz (FSB 533)
011B: 167 MHz (FSB 667)
010B: 200 MHz (FSB 800)
000B: 267 MHz (FSB 1067)
100B: 333 MHz (FSB 1333)
110B: 400 MHz (FSB 1600)
*/
// T8300 -> 0x01A2 => 200MHz
#define MSR_PLATFORM_INFO 0x00CE /* limited use - MinRatio for i7 but Max for Yonah */
/* turbo for penryn */
//haswell
//Low Frequency Mode. LFM is Pn in the P-state table. It can be read at MSR CEh [47:40].
//Minimum Frequency Mode. MFM is the minimum ratio supported by the processor and can be read from MSR CEh [55:48].
#define MSR_PKG_CST_CONFIG_CONTROL 0x00E2 /* sandy and up */
#define MSR_PMG_IO_CAPTURE_BASE 0x00E4 /* sandy and up */
#define IA32_MPERF 0x00E7 /* TSC in C0 only */
#define IA32_APERF 0x00E8 /* actual clocks in C0 */
#define MSR_IA32_EXT_CONFIG 0x00EE /* limited use - not for i7 */
#define MSR_FLEX_RATIO 0x0194 /* limited use - not for Penryn or older */
//see no value on most CPUs
#define MSR_IA32_PERF_STATUS 0x0198
#define MSR_IA32_PERF_CONTROL 0x0199
#define MSR_IA32_CLOCK_MODULATION 0x019A
#define MSR_THERMAL_STATUS 0x019C
#define MSR_IA32_MISC_ENABLE 0x01A0
#define MSR_THERMAL_TARGET 0x01A2 /* TjMax limited use - not for Penryn or older */
#define MSR_TURBO_RATIO_LIMIT 0x01AD /* limited use - not for Penryn or older */
#define IA32_ENERGY_PERF_BIAS 0x01B0
//MSR 000001B0 0000-0000-0000-0005
#define MSR_PACKAGE_THERM_STATUS 0x01B1
//MSR 000001B1 0000-0000-8838-0000
#define IA32_PLATFORM_DCA_CAP 0x01F8
//MSR 000001FC 0000-0000-0004-005F
// Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.
#define MSR_RAPL_POWER_UNIT 0x606 /* R/O */
//MSR 00000606 0000-0000-000A-1003
#define MSR_PKGC3_IRTL 0x60A /* RW time limit to go C3 */
// bit 15 = 1 -- the value valid for C-state PM
#define MSR_PKGC6_IRTL 0x60B /* RW time limit to go C6 */
//MSR 0000060B 0000-0000-0000-8854
//Valid + 010=1024ns + 0x54=84mks
#define MSR_PKGC7_IRTL 0x60C /* RW time limit to go C7 */
//MSR 0000060C 0000-0000-0000-8854
#define MSR_PKG_C2_RESIDENCY 0x60D /* same as TSC but in C2 only */
#define MSR_PKG_RAPL_POWER_LIMIT 0x610
//MSR 00000610 0000-A580-0000-8960
#define MSR_PKG_ENERGY_STATUS 0x611
//MSR 00000611 0000-0000-3212-A857
#define MSR_PKG_POWER_INFO 0x614
//MSR 00000614 0000-0000-01E0-02F8
// Sandy Bridge IA (Core) domain MSR's.
#define MSR_PP0_POWER_LIMIT 0x638
#define MSR_PP0_ENERGY_STATUS 0x639
#define MSR_PP0_POLICY 0x63A
#define MSR_PP0_PERF_STATUS 0x63B
// Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).
#define MSR_PP1_POWER_LIMIT 0x640
#define MSR_PP1_ENERGY_STATUS 0x641
//MSR 00000641 0000-0000-0000-0000
#define MSR_PP1_POLICY 0x642
// JakeTown only Memory MSR's.
#define MSR_PKG_PERF_STATUS 0x613
#define MSR_DRAM_POWER_LIMIT 0x618
#define MSR_DRAM_ENERGY_STATUS 0x619
#define MSR_DRAM_PERF_STATUS 0x61B
#define MSR_DRAM_POWER_INFO 0x61C
//IVY_BRIDGE
#define MSR_CONFIG_TDP_NOMINAL 0x648
#define MSR_CONFIG_TDP_LEVEL1 0x649
#define MSR_CONFIG_TDP_LEVEL2 0x64A
#define MSR_CONFIG_TDP_CONTROL 0x64B /* write once to lock */
#define MSR_TURBO_ACTIVATION_RATIO 0x64C
//Skylake
#define BASE_ART_CLOCK_SOURCE 24000000ULL /* 24Mhz */
#define MSR_IA32_PM_ENABLE 0x770
#define MSR_IA32_HWP_REQUEST 0x774
//AMD
#define K8_FIDVID_STATUS 0xC0010042
#define K10_COFVID_LIMIT 0xC0010061 /* max enabled p-state (msr >> 4) & 7 */
#define K10_COFVID_CONTROL 0xC0010062 /* switch to p-state */
#define K10_PSTATE_STATUS 0xC0010064
#define K10_COFVID_STATUS 0xC0010071 /* current p-state (msr >> 16) & 7 */
/* specific settings
static void SavePState(unsigned int index, unsigned int lowMsr, unsigned int core)
{
CONST unsigned int msrIndex = 0xC0010064u + index;
CONST DWORD_PTR affinityMask = (DWORD_PTR)1 << core;
DWORD lower, higher;
RdmsrTx(msrIndex, &lower, &higher, affinityMask);
CONST DWORD lowMsrMask = 0xFE40FFFFu;
lower = (lower & ~lowMsrMask) | (lowMsr & lowMsrMask);
WrmsrTx(msrIndex, lower, higher, affinityMask);
}
MSR C0010064 8000-0185-0000-1418 [20.00x] [1.4250 V] [13.30 A] [PState Pb0]
MSR C0010065 8000-0185-0000-1615 [18.50x] [1.4125 V] [13.30 A] [PState Pb1]
MSR C0010066 8000-0173-0000-1A1A [21.00x] [1.3875 V] [11.50 A] [PState P0]
MSR C0010067 0000-0173-0000-1A1A
MSR C0010068 0000-0173-0000-181A
MSR C0010069 0000-0173-0000-1A1A
MSR C001006A 8000-0125-0000-604C [ 7.00x] [0.9500 V] [ 3.70 A] [PState P1]
MSR C001006B 0000-0000-0000-0000
*/
#define DEFAULT_FSB 100000 /* for now, hardcoding 100MHz for old CPUs */
/* CPUID Index */
#define CPUID_0 0
#define CPUID_1 1
#define CPUID_2 2
#define CPUID_3 3
#define CPUID_4 4
#define CPUID_5 5
#define CPUID_6 6
#define CPUID_80 7
#define CPUID_81 8
#define CPUID_87 9
#define CPUID_88 10
#define CPUID_81E 11
#define CPUID_15 15
#define CPUID_MAX 16
/* CPU Cache */
#define MAX_CACHE_COUNT 4
#define CPU_CACHE_LEVEL 3
typedef struct {
//values from CPUID

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@ -9,6 +9,9 @@
#include "Platform.h"
#include "device_inject.h"
#include "FixBiosDsdt.h"
#include "../include/Devices.h"
#ifndef DEBUG_INJECT
#ifndef DEBUG_ALL
@ -24,6 +27,8 @@
#define DBG(...) DebugLog(DEBUG_INJECT, __VA_ARGS__)
#endif
#define MAX_NUM_DEVICES 64
UINT32 devices_number = 1;
UINT32 builtin_set = 0;
DevPropString *device_inject_string = NULL;

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@ -10,60 +10,14 @@
#ifndef __LIBSAIO_DEVICE_INJECT_H
#define __LIBSAIO_DEVICE_INJECT_H
#include "../include/Pci.h"
/* No more used
#define DP_ADD_TEMP_VAL(dev, val) devprop_add_value(dev, (CHAR8*)val[0], (UINT8*)val[1], (UINT32)AsciiStrLen(val[1]))
#define DP_ADD_TEMP_VAL_DATA(dev, val) devprop_add_value(dev, (CHAR8*)val.name, (UINT8*)val.data, val.size)
*/
#define MAX_PCI_DEV_PATHS 16
//#define REG8(reg) ((volatile UINT8 *)regs)[(reg)]
//#define REG16(reg) ((volatile UINT16 *)regs)[(reg) >> 1]
//#define REG32(reg) ((volatile UINT32 *)regs)[(reg) >> 2]
//UINT32 REG32(UINT32 reg);
//VOID WRITEREG32 (UINT32 reg, UINT32 value);
typedef struct {
UINT32 :2;
UINT32 reg :6;
UINT32 func:3;
UINT32 dev :5;
UINT32 bus :8;
UINT32 :7;
UINT32 eb :1;
} pci_addr_t;
typedef union {
pci_addr_t bits;
UINT32 addr;
} pci_dev_t;
typedef struct pci_dt_t {
// EFI_PCI_IO_PROTOCOL *PciIo;
// PCI_TYPE00 Pci;
EFI_HANDLE DeviceHandle;
UINT8* regs;
pci_dev_t dev;
UINT16 vendor_id;
UINT16 device_id;
union {
struct {
UINT16 vendor_id;
UINT16 device_id;
} subsys;
UINT32 subsys_id;
} subsys_id;
UINT8 revision;
UINT8 subclass;
UINT16 class_id;
struct pci_dt_t *parent;
struct pci_dt_t *children;
struct pci_dt_t *next;
BOOLEAN used;
} pci_dt_t;
#pragma pack(1)
/* Option ROM header */

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@ -64,6 +64,8 @@
#include "Platform.h"
#include "gma.h"
#include "platformdata.h"
#include "FixBiosDsdt.h"
#include "../include/Devices.h"
#ifndef DEBUG_GMA
#ifndef DEBUG_ALL

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@ -19,7 +19,10 @@
*/
#include "Platform.h"
//#include <Library/HdaModels.h>
#include "FixBiosDsdt.h"
#include "../include/Devices.h"
#include "../include/Pci.h"
#include "device_inject.h"
#ifndef DEBUG_HDA
#ifndef DEBUG_ALL

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@ -11,6 +11,7 @@
#include "Nvram.h"
#include "FixBiosDsdt.h"
#include "cpu.h"
#include "kext_inject.h"
#include "kernel_patcher.h"
#include "sse3_patcher.h"

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@ -6,6 +6,7 @@
#ifndef __LIBSAIO_KERNEL_PATCHER_H
#define __LIBSAIO_KERNEL_PATCHER_H
#include "boot.h"
#define CPUFAMILY_INTEL_6_13 0xaa33392b
#define CPUFAMILY_INTEL_YONAH 0x73d67300

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@ -1,4 +1,5 @@
#include "Platform.h"
#include "kext_inject.h"
#include "DataHubCpu.h"
#ifndef DEBUG_ALL

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@ -52,6 +52,9 @@
#include "device_inject.h"
#include "smbios.h"
#include "card_vlist.h"
#include "FixBiosDsdt.h"
#include "../include/Pci.h"
#include "../include/Devices.h"
#ifndef DEBUG_NVIDIA
#ifndef DEBUG_ALL

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@ -52,6 +52,7 @@
//#include "device_inject.h"
#include "card_vlist.h"
#include "../include/Pci.h"
extern CHAR8* gDeviceProperties;

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@ -44,6 +44,23 @@
#endif
/* XML Tags */
#define kXMLTagPList "plist"
#define kXMLTagDict "dict"
#define kXMLTagKey "key"
#define kXMLTagString "string"
#define kXMLTagInteger "integer"
#define kXMLTagData "data"
#define kXMLTagDate "date"
#define kXMLTagFalse "false/"
#define kXMLTagTrue "true/"
#define kXMLTagArray "array"
#define kXMLTagReference "reference"
#define kXMLTagID "ID="
#define kXMLTagIDREF "IDREF="
struct Symbol {
UINTN refCount;
struct Symbol *next;

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@ -46,12 +46,12 @@ extern "C" {
#define REMAP_SMBIOS_TABLE_GUID { 0xeb9d2d35, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } }
#define CPUID_EXTFEATURE_EM64T _Bit(29)
#define CPUID_EXTFEATURE_XD _Bit(20)
#define CPUID_FEATURE_VMX _HBit(5)
#define CPUID_FEATURE_EST _HBit(7)
#define MAX_OEM_STRING 256
#define ROUND_PAGE(x) ((((unsigned)(x)) + EFI_PAGE_SIZE - 1) & ~(EFI_PAGE_SIZE - 1))
EFI_GUID *gTableGuidArray[] = {&gEfiSmbiosTableGuid, &gEfiSmbios3TableGuid};
const CHAR8 unknown[] = "unknown";

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@ -12,10 +12,10 @@ extern "C" {
#if 1 //!defined(_MSC_VER)
#ifdef __GNUC__
void* memset(void* dst, int ch, UINT64 count) __attribute__ ((used));
void* memcpy(void* dst, const void* src, UINT64 count) __attribute__ ((used));
//void* memcpy(void* dst, const void* src, UINT64 count) __attribute__ ((used));
#else
void* memset(void* dst, int ch, UINT64 count);
void* memcpy(void* dst, const void* src, UINT64 count);
// void* memcpy(void* dst, const void* src, UINT64 count);
#endif
void* memset(void* dst, int ch, UINT64 count)
@ -23,12 +23,12 @@ void* memset(void* dst, int ch, UINT64 count)
SetMem(dst, count, (UINT8)(ch));
return dst;
}
void* memcpy(void* dst, const void* src, UINT64 count)
{
CopyMem(dst, src, count);
return dst;
}
//
//void* memcpy(void* dst, const void* src, UINT64 count)
//{
// CopyMem(dst, src, count);
// return dst;
//}
#endif
} // extern "C"

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@ -33,6 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "loader.h"
#include "../cpp_foundation/XStringW.h"
#include "entry_scan.h"
#include "../Platform/Settings.h"
@ -72,6 +73,7 @@ const XString LINUX_DEFAULT_OPTIONS = "ro add_efi_memmap quiet splash vt.handoff
#define BOOT_LOADER_PATH L"\\EFI\\BOOT\\BOOTIA32.efi"
#endif
extern LOADER_ENTRY *SubMenuKextInjectMgmt(LOADER_ENTRY *Entry);
// Linux loader path data

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@ -10,6 +10,16 @@
//#define DUMP_KERNEL_KEXT_PATCHES 1
// Kernel scan states
#define KERNEL_SCAN_ALL (0)
#define KERNEL_SCAN_NEWEST (1)
#define KERNEL_SCAN_OLDEST (2)
#define KERNEL_SCAN_FIRST (3)
#define KERNEL_SCAN_LAST (4)
#define KERNEL_SCAN_MOSTRECENT (5)
#define KERNEL_SCAN_EARLIEST (6)
#define KERNEL_SCAN_NONE (100)
UINT8 GetOSTypeFromPath (IN CONST CHAR16 *Path);

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@ -0,0 +1,32 @@
/*
* secureboot.h
*
* Created on: 16 Apr 2020
* Author: jief
*/
#ifndef ENTRY_SCAN_SECUREBOOT_H_
#define ENTRY_SCAN_SECUREBOOT_H_
// Secure boot policies
// Deny all images
#define SECURE_BOOT_POLICY_DENY (0)
// Allow all images
#define SECURE_BOOT_POLICY_ALLOW (1)
// Query the user to choose action
#define SECURE_BOOT_POLICY_QUERY (2)
// Insert signature into db
#define SECURE_BOOT_POLICY_INSERT (3)
// White list
#define SECURE_BOOT_POLICY_WHITELIST (4)
// Black list
#define SECURE_BOOT_POLICY_BLACKLIST (5)
// User policy, white and black list with query
#define SECURE_BOOT_POLICY_USER (6)
#endif /* ENTRY_SCAN_SECUREBOOT_H_ */

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@ -53,6 +53,7 @@
#include "../refit/menu.h" // for DrawTextXY. Must disappear soon.
#include "../Platform/AcpiPatcher.h"
#include "../Platform/Nvram.h"
#include "../refit/screen.h"
#ifndef DEBUG_ALL
#define DEBUG_MENU 1
@ -67,13 +68,8 @@
#endif
XPointer REFIT_MENU_SCREEN::mPointer;
//
//
////#define PREBOOT_LOG L"EFI\\CLOVER\\misc\\preboot.log"
//
////#define LSTR(s) L##s
//
//// scrolling definitions
// scrolling definitions
static INTN MaxItemOnScreen = -1;

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@ -0,0 +1,33 @@
/*
* Pci.h
*
* Created on: 16 Apr 2020
* Author: jief
*/
#ifndef INCLUDE_DEVICES_H_
#define INCLUDE_DEVICES_H_
//devices
#define DEV_ATI bit(0)
#define DEV_NVIDIA bit(1)
#define DEV_INTEL bit(2)
#define DEV_HDA bit(3)
#define DEV_HDMI bit(4)
#define DEV_LAN bit(5)
#define DEV_WIFI bit(6)
#define DEV_SATA bit(7)
#define DEV_IDE bit(8)
#define DEV_LPC bit(9)
#define DEV_SMBUS bit(10)
#define DEV_USB bit(11)
#define DEV_FIREWIRE bit(12)
#define DEV_MCHC bit(13)
#define DEV_IMEI bit(14)
#define DEV_BY_PCI bit(31)
#endif /* INCLUDE_DEVICES_H_ */

94
rEFIt_UEFI/include/Efi.h Normal file
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@ -0,0 +1,94 @@
/*
* Efi.h
*
* Created on: 16 Apr 2020
* Author: jief
*/
#ifndef INCLUDE_EFI_H_
#define INCLUDE_EFI_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <Library/printf_lite.h>
#include <Uefi.h>
#include <Guid/Acpi.h>
#include <Guid/EventGroup.h>
#include <Guid/SmBios.h>
#include <Guid/Mps.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
#include <Library/DeviceTreeLib.h>
#include <Library/GenericBdsLib.h>
#include <Library/HiiLib.h>
#include <Library/HdaModels.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
#include <Library/PerformanceLib.h>
#include <Library/PeCoffGetEntryPointLib.h>
#include <Library/TimerLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/UefiRuntimeLib.h>
#include <Library/UsbMass.h>
#include <Library/VideoBiosPatchLib.h>
#include <Library/MemLogLib.h>
#include <Library/WaveLib.h>
#include <Framework/FrameworkInternalFormRepresentation.h>
#include <IndustryStandard/Acpi10.h>
#include <IndustryStandard/Acpi20.h>
#include <IndustryStandard/Atapi.h>
#include <IndustryStandard/AppleHid.h>
#include <IndustryStandard/AppleSmBios.h>
#include <IndustryStandard/AppleFeatures.h>
#include <IndustryStandard/Bmp.h>
#include <IndustryStandard/HdaCodec.h>
#include <Protocol/PciIo.h>
#include <Protocol/AudioIo.h>
#include <Protocol/Cpu.h>
#include <Protocol/CpuIo.h>
#include <Protocol/DataHub.h>
#include <Protocol/DevicePathToText.h>
#include <Protocol/EdidDiscovered.h>
#include <Protocol/EdidOverride.h>
#include <Protocol/FrameworkHii.h>
#include <Protocol/HdaIo.h>
#include <Protocol/SimplePointer.h>
#include <Protocol/Smbios.h>
#include <Protocol/VariableWrite.h>
#include <Protocol/Variable.h>
#include <Protocol/UgaDraw.h>
#include <Protocol/FSInjectProtocol.h>
#include <Protocol/MsgLog.h>
#include <Protocol/efiConsoleControl.h>
#include <Protocol/EmuVariableControl.h>
#include <Protocol/AppleSMC.h>
#include <Protocol/AppleImageCodecProtocol.h>
#ifdef __cplusplus
}
#endif
#define EFI_SYSTEM_TABLE_MAX_ADDRESS 0xFFFFFFFF
#endif /* INCLUDE_EFI_H_ */

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@ -23,8 +23,6 @@ Revision History
#ifndef _HANDLE_H
#define _HANDLE_H
#include "libeg.h"
#define EFI_HANDLE_TYPE_UNKNOWN 0x000
#define EFI_HANDLE_TYPE_IMAGE_HANDLE 0x001
#define EFI_HANDLE_TYPE_DRIVER_BINDING_HANDLE 0x002
@ -38,128 +36,5 @@ Revision History
#define EFI_HANDLE_TYPE_CONTROLLER_HANDLE 0x200
#define EFI_HANDLE_TYPE_CHILD_HANDLE 0x400
EFI_FILE_SYSTEM_INFO *
EfiLibFileSystemInfo (
IN EFI_FILE_HANDLE FHand
);
/*EFI_FILE_SYSTEM_VOLUME_LABEL_INFO *
LibFileSystemVolumeLabelInfo (
IN EFI_FILE_HANDLE FHand
);
EFI_STATUS
LibScanHandleDatabase (
EFI_HANDLE DriverBindingHandle, OPTIONAL
UINT32 *DriverBindingHandleIndex, OPTIONAL
EFI_HANDLE ControllerHandle, OPTIONAL
UINT32 *ControllerHandleIndex, OPTIONAL
UINTN *HandleCount,
EFI_HANDLE **HandleBuffer,
UINT32 **HandleType
);
EFI_STATUS
LibGetManagingDriverBindingHandles (
EFI_HANDLE ControllerHandle,
UINTN *DriverBindingHandleCount,
EFI_HANDLE **DriverBindingHandleBuffer
);
EFI_STATUS
LibGetParentControllerHandles (
EFI_HANDLE ControllerHandle,
UINTN *ParentControllerHandleCount,
EFI_HANDLE **ParentControllerHandleBuffer
);
*/
EFI_STATUS
LibGetManagedChildControllerHandles (
EFI_HANDLE DriverBindingHandle,
EFI_HANDLE ControllerHandle,
UINTN *ChildControllerHandleCount,
EFI_HANDLE **ChildControllerHandleBuffer
);
EFI_STATUS
LibGetManagedControllerHandles (
EFI_HANDLE DriverBindingHandle,
UINTN *ControllerHandleCount,
EFI_HANDLE **ControllerHandleBuffer
);
EFI_STATUS
LibGetChildControllerHandles (
EFI_HANDLE ControllerHandle,
UINTN *HandleCount,
EFI_HANDLE **HandleBuffer
);
EFI_STATUS
LibInstallProtocolInterfaces (
IN OUT EFI_HANDLE *Handle,
...
);
VOID
LibUninstallProtocolInterfaces (
IN EFI_HANDLE Handle,
...
);
EFI_STATUS
LibReinstallProtocolInterfaces (
IN OUT EFI_HANDLE *Handle,
...
);
EFI_STATUS
LibLocateHandleByDiskSignature (
IN UINT8 MBRType,
IN UINT8 SignatureType,
IN VOID *Signature,
IN OUT UINTN *NoHandles,
OUT EFI_HANDLE **Buffer
);
EFI_STATUS
LibLocateHandle (
IN EFI_LOCATE_SEARCH_TYPE SearchType,
IN EFI_GUID * Protocol OPTIONAL,
IN VOID *SearchKey OPTIONAL,
IN OUT UINTN *NoHandles,
OUT EFI_HANDLE **Buffer
);
EFI_STATUS
LibLocateProtocol (
IN EFI_GUID *ProtocolGuid,
OUT VOID **Interface
);
EFI_HANDLE
ShellHandleFromIndex (
IN UINTN Value
);
UINTN
ShellHandleNoFromIndex (
IN UINTN Value
);
UINTN
ShellHandleToIndex (
IN EFI_HANDLE Handle
);
UINTN
ShellHandleNoFromStr (
IN CHAR16 *Str
);
UINTN
ShellGetHandleNum (
VOID
);
#endif

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@ -0,0 +1,43 @@
/*
* OneLinerMacros.h
*
* Created on: 16 Apr 2020
* Author: jief
*/
#ifndef INCLUDE_ONELINERMACROS_H_
#define INCLUDE_ONELINERMACROS_H_
/* Decimal powers: */
#define kilo (1000ULL)
#define Mega (kilo * kilo)
#define Giga (kilo * Mega)
#define Tera (kilo * Giga)
#define Peta (kilo * Tera)
#define bit(n) (1UL << (n))
#define _Bit(n) (1ULL << (n))
#define _HBit(n) (1ULL << ((n)+32))
#define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
#define bitfield(x,h,l) RShiftU64(((x) & bitmask((h),(l))), (l))
#define quad(hi,lo) ((LShiftU64((hi), 32) | (lo)))
#define REG8(base, reg) ((volatile UINT8 *)(UINTN)(base))[(reg)]
#define REG16(base, reg) ((volatile UINT16 *)(UINTN)(base))[(reg) >> 1]
//#define REG32(base, reg) ((volatile UINT32 *)(UINTN)(base))[(reg) >> 2]
#define REG32(base, reg) (*(volatile UINT32 *)((UINTN)base + reg))
#define WRITEREG32(base, reg, value) REG32((base), (reg)) = value
#ifdef _MSC_VER
#define __typeof__(x) decltype(x)
#endif
#define __typeof_am__(x) remove_ref<decltype(x)>::type
#endif /* INCLUDE_ONELINERMACROS_H_ */

69
rEFIt_UEFI/include/Pci.h Normal file
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@ -0,0 +1,69 @@
/*
* Pci.h
*
* Created on: 16 Apr 2020
* Author: jief
*/
#ifndef INCLUDE_PCI_H_
#define INCLUDE_PCI_H_
/* PCI */
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
#define PCI_CLASS_MEDIA_HDA 0x03
#define PCIADDR(bus, dev, func) ((1 << 31) | ((bus) << 16) | ((dev) << 11) | ((func) << 8))
typedef struct {
UINT32 :2;
UINT32 reg :6;
UINT32 func:3;
UINT32 dev :5;
UINT32 bus :8;
UINT32 :7;
UINT32 eb :1;
} pci_addr_t;
typedef union {
pci_addr_t bits;
UINT32 addr;
} pci_dev_t;
typedef struct pci_dt_t {
// EFI_PCI_IO_PROTOCOL *PciIo;
// PCI_TYPE00 Pci;
EFI_HANDLE DeviceHandle;
UINT8* regs;
pci_dev_t dev;
UINT16 vendor_id;
UINT16 device_id;
union {
struct {
UINT16 vendor_id;
UINT16 device_id;
} subsys;
UINT32 subsys_id;
} subsys_id;
UINT8 revision;
UINT8 subclass;
UINT16 class_id;
struct pci_dt_t *parent;
struct pci_dt_t *children;
struct pci_dt_t *next;
BOOLEAN used;
} pci_dt_t;
#endif /* INCLUDE_PCI_H_ */

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@ -35,6 +35,7 @@
*/
#include "Platform.h"
#include "screen.h"
#ifndef DEBUG_ALL
#define DEBUG_LIB 1

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@ -68,6 +68,8 @@
#include "../Platform/Injectors.h"
#include "../Platform/StartupSound.h"
#include "../Platform/BootOptions.h"
#include "../Platform/boot.h"
#include "../Platform/kext_inject.h"
#ifndef DEBUG_ALL
#define DEBUG_MAIN 1
@ -91,6 +93,10 @@
#endif
#define PCAT_RTC_ADDRESS_REGISTER 0x70
#define PCAT_RTC_DATA_REGISTER 0x71
// variables
BOOLEAN gGuiIsReady = FALSE;

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@ -55,6 +55,9 @@
#include "../Platform/platformdata.h"
#include "../Platform/cpu.h"
#include "../Platform/Nvram.h"
#include "../Platform/FixBiosDsdt.h"
#include "../include/Devices.h"
#include "../Platform/boot.h"
#ifndef DEBUG_ALL
#define DEBUG_MENU 1
@ -69,19 +72,10 @@
#endif
//#define PREBOOT_LOG L"EFI\\CLOVER\\misc\\preboot.log"
//#define VBIOS_BIN L"EFI\\CLOVER\\misc\\c0000.bin"
//CONST CHAR16 *VBIOS_BIN = L"EFI\\CLOVER\\misc\\c0000.bin"; // tmporarily moved in shared_wint_menu
//#define LSTR(s) L##s
REFIT_MENU_SCREEN OptionMenu(4, L"Options"_XSW, L""_XSW);
extern CONST CHAR8 *AudioOutputNames[];
#include "../Platform/string.h"
INTN LayoutMainMenuHeight = 376;
INTN LayoutAnimMoveForMenuX = 0;
//