mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-09-21 02:51:04 +02:00
take into account tiger lake
Signed-off-by: SergeySlice <sergey.slice@gmail.com>
This commit is contained in:
SergeySlice
parent
e24ceaa470
commit
a17071034c
@ -267,7 +267,9 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
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case CPU_MODEL_COMETLAKE_S:
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case CPU_MODEL_COMETLAKE_Y:
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case CPU_MODEL_COMETLAKE_U:
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{
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case CPU_MODEL_TIGERLAKE_C:
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case CPU_MODEL_TIGERLAKE_D:
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{
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maximum.Control.Control = RShiftU64(AsmReadMsr64(MSR_PLATFORM_INFO), 8) & 0xff;
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if (gSettings.MaxMultiplier) {
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DBG("Using custom MaxMultiplier %d instead of automatic %d\n",
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@ -333,7 +335,9 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
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(gCPUStructure.Model == CPU_MODEL_ICELAKE_C) ||
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(gCPUStructure.Model == CPU_MODEL_ICELAKE_D) ||
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(gCPUStructure.Model == CPU_MODEL_ICELAKE) ||
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(gCPUStructure.Model == CPU_MODEL_COMETLAKE_S) ||
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(gCPUStructure.Model == CPU_MODEL_TIGERLAKE_C) ||
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(gCPUStructure.Model == CPU_MODEL_TIGERLAKE_D) ||
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(gCPUStructure.Model == CPU_MODEL_COMETLAKE_S) ||
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(gCPUStructure.Model == CPU_MODEL_COMETLAKE_Y) ||
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(gCPUStructure.Model == CPU_MODEL_COMETLAKE_U)) {
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j = i << 8;
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@ -287,6 +287,8 @@ void GetCPUProperties (void)
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gCPUStructure.Turbo = ((gCPUStructure.CPUID[CPUID_6][EAX] & BIT1) != 0);
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DBG(" The CPU%s supported turbo\n", gCPUStructure.Turbo?"":" not");
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//get cores and threads
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BOOLEAN PerfBias = (gCPUStructure.CPUID[CPUID_6][ECX] & BIT3) != 0;
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DBG(" Energy PerfBias is %s visible:\n", PerfBias?"":" not");
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switch (gCPUStructure.Model)
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{
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case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)
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@ -324,8 +326,10 @@ void GetCPUProperties (void)
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case CPU_MODEL_COMETLAKE_S:
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case CPU_MODEL_COMETLAKE_Y:
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case CPU_MODEL_COMETLAKE_U:
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case CPU_MODEL_TIGERLAKE_C:
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case CPU_MODEL_TIGERLAKE_D:
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msr = AsmReadMsr64(MSR_CORE_THREAD_COUNT); //0x35
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DBG("MSR 0x35 %16llX\n", msr);
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DBG("MSR 0x35 %16llX\n", msr);
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gCPUStructure.Cores = (UINT8)bitfield((UINT32)msr, 31, 16);
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gCPUStructure.Threads = (UINT8)bitfield((UINT32)msr, 15, 0);
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break;
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@ -515,7 +519,9 @@ void GetCPUProperties (void)
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case CPU_MODEL_COMETLAKE_S:
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case CPU_MODEL_COMETLAKE_Y:
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case CPU_MODEL_COMETLAKE_U:
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gCPUStructure.TSCFrequency = MultU64x32(gCPUStructure.CurrentSpeed, Mega); //MHz -> Hz
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case CPU_MODEL_TIGERLAKE_C:
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case CPU_MODEL_TIGERLAKE_D:
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gCPUStructure.TSCFrequency = MultU64x32(gCPUStructure.CurrentSpeed, Mega); //MHz -> Hz
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gCPUStructure.CPUFrequency = gCPUStructure.TSCFrequency;
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@ -1393,6 +1399,8 @@ UINT16 GetAdvancedCpuType ()
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case CPU_MODEL_COMETLAKE_S:
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case CPU_MODEL_COMETLAKE_Y:
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case CPU_MODEL_COMETLAKE_U:
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case CPU_MODEL_TIGERLAKE_C:
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case CPU_MODEL_TIGERLAKE_D:
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if (AsciiStrStr(gCPUStructure.BrandString, "Core(TM) i3"))
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return 0x905; // Core i3 - Apple doesn't use it
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if (AsciiStrStr(gCPUStructure.BrandString, "Core(TM) i5"))
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@ -43,33 +43,35 @@
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//#define CPU_MODEL_HASWELL_H 0x?? // Haswell H
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#define CPU_MODEL_HASWELL_ULT 0x45 /* Haswell ULT */
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#define CPU_MODEL_CRYSTALWELL 0x46 /* Haswell ULX CPUID_MODEL_CRYSTALWELL */
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#define CPU_MODEL_BROADWELL_HQ 0x47 /* E3-1200 v4 */
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#define CPU_MODEL_BROADWELL_HQ 0x47 /* E3-1200 v4 5th */
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#define CPU_MODEL_MERRIFIELD 0x4A /* Tangier */
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#define CPU_MODEL_AIRMONT 0x4C /* CherryTrail / Braswell */
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#define CPU_MODEL_AVOTON 0x4D /* Avaton/Rangely */
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#define CPU_MODEL_SKYLAKE_U 0x4E /* Skylake Mobile */
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#define CPU_MODEL_BROADWELL_E5 0x4F /* Xeon E5-2695 */
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#define CPU_MODEL_BROADWELL_E5 0x4F /* Xeon E5-2695 5th */
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#define CPU_MODEL_SKYLAKE_S 0x55 /* Skylake Server, Cooper Lake */
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#define CPU_MODEL_BROADWELL_DE 0x56 /* Xeon BroadWell */
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#define CPU_MODEL_BROADWELL_DE 0x56 /* Xeon BroadWell 5th */
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#define CPU_MODEL_KNIGHT 0x57 /* Knights Landing */
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#define CPU_MODEL_MOOREFIELD 0x5A /* Annidale */
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#define CPU_MODEL_GOLDMONT 0x5C /* Apollo Lake */
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#define CPU_MODEL_ATOM_X3 0x5D /* Silvermont */
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#define CPU_MODEL_SKYLAKE_D 0x5E /* Skylake Desktop */
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#define CPU_MODEL_DENVERTON 0x5F /* Goldmont Microserver */
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#define CPU_MODEL_CANNONLAKE 0x66
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#define CPU_MODEL_CANNONLAKE 0x66 /* 8h generation Cannon Lake */
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#define CPU_MODEL_ICELAKE_A 0x6A /* Xeon Ice Lake */
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#define CPU_MODEL_ICELAKE_C 0x6C /* Xeon Ice Lake */
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#define CPU_MODEL_ATOM_GM 0x7A /* Goldmont Plus */
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#define CPU_MODEL_ICELAKE_D 0x7D
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#define CPU_MODEL_ICELAKE 0x7E
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#define CPU_MODEL_ICELAKE_D 0x7D /* 10h Ice Lake */
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#define CPU_MODEL_ICELAKE 0x7E /* 10h Ice Lake */
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#define CPU_MODEL_XEON_MILL 0x85 /* Knights Mill */
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#define CPU_MODEL_ATOM_TM 0x86 /* Tremont */
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#define CPU_MODEL_KABYLAKE1 0x8E /* Kabylake Mobile */
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#define CPU_MODEL_KABYLAKE2 0x9E /* Kabylake Dektop, CoffeeLake */
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#define CPU_MODEL_TIGERLAKE_C 0x8C /* 11h generation Tiger Lake */
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#define CPU_MODEL_TIGERLAKE_D 0x8D /* 11h generation Tiger Lake */
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#define CPU_MODEL_KABYLAKE1 0x8E /* 7h Kabylake Mobile */
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#define CPU_MODEL_KABYLAKE2 0x9E /* 7h CoffeeLake */
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#define CPU_MODEL_COMETLAKE_S 0x9F /* desktop Comet Lake */
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#define CPU_MODEL_COMETLAKE_Y 0xA5 /* aka 10th generation Amber Lake Y */
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#define CPU_MODEL_COMETLAKE_U 0xA6
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#define CPU_MODEL_COMETLAKE_Y 0xA5 /* 10h Comet Lake */
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#define CPU_MODEL_COMETLAKE_U 0xA6 /* 10h Comet Lake */
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#define CPU_VENDOR_INTEL 0x756E6547
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#define CPU_VENDOR_AMD 0x68747541
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@ -214,9 +216,13 @@ const char CPU_STRING_UNKNOWN[] = "Unknown CPU Type";
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#define MSR_IA32_MISC_ENABLE 0x01A0
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#define MSR_THERMAL_TARGET 0x01A2 /* TjMax limited use - not for Penryn or older */
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#define MSR_TURBO_RATIO_LIMIT 0x01AD /* limited use - not for Penryn or older */
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#define MSR_MISC_PWR_MGMT 0x01AA /* EIST Hardware Coordination Disable (R/W) */
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/* defined for Goldmont, Nehalem, Sandy and up
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* bit0=1 == disable
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* bit1=1 == enable MSR 1B0
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*/
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#define IA32_ENERGY_PERF_BIAS 0x01B0
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#define IA32_ENERGY_PERF_BIAS 0x01B0 /* 0=fast 15=low energy If CPUID.6H:ECX[3] = 1 */
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//MSR 000001B0 0000-0000-0000-0005
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#define MSR_PACKAGE_THERM_STATUS 0x01B1
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//MSR 000001B1 0000-0000-8838-0000
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