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take into account tiger lake

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Signed-off-by: SergeySlice <sergey.slice@gmail.com>
This commit is contained in:
SergeySlice 2021-02-06 19:18:48 +03:00
parent e24ceaa470
commit a17071034c
3 changed files with 34 additions and 16 deletions
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8
rEFIt_UEFI/Platform/StateGenerator.cpp
View File

@ -267,7 +267,9 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
case CPU_MODEL_COMETLAKE_S: case CPU_MODEL_COMETLAKE_S:
case CPU_MODEL_COMETLAKE_Y: case CPU_MODEL_COMETLAKE_Y:
case CPU_MODEL_COMETLAKE_U: case CPU_MODEL_COMETLAKE_U:
{ case CPU_MODEL_TIGERLAKE_C:
case CPU_MODEL_TIGERLAKE_D:
{
maximum.Control.Control = RShiftU64(AsmReadMsr64(MSR_PLATFORM_INFO), 8) & 0xff; maximum.Control.Control = RShiftU64(AsmReadMsr64(MSR_PLATFORM_INFO), 8) & 0xff;
if (gSettings.MaxMultiplier) { if (gSettings.MaxMultiplier) {
DBG("Using custom MaxMultiplier %d instead of automatic %d\n", DBG("Using custom MaxMultiplier %d instead of automatic %d\n",
@ -333,7 +335,9 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
(gCPUStructure.Model == CPU_MODEL_ICELAKE_C) || (gCPUStructure.Model == CPU_MODEL_ICELAKE_C) ||
(gCPUStructure.Model == CPU_MODEL_ICELAKE_D) || (gCPUStructure.Model == CPU_MODEL_ICELAKE_D) ||
(gCPUStructure.Model == CPU_MODEL_ICELAKE) || (gCPUStructure.Model == CPU_MODEL_ICELAKE) ||
(gCPUStructure.Model == CPU_MODEL_COMETLAKE_S) || (gCPUStructure.Model == CPU_MODEL_TIGERLAKE_C) ||
(gCPUStructure.Model == CPU_MODEL_TIGERLAKE_D) ||
(gCPUStructure.Model == CPU_MODEL_COMETLAKE_S) ||
(gCPUStructure.Model == CPU_MODEL_COMETLAKE_Y) || (gCPUStructure.Model == CPU_MODEL_COMETLAKE_Y) ||
(gCPUStructure.Model == CPU_MODEL_COMETLAKE_U)) { (gCPUStructure.Model == CPU_MODEL_COMETLAKE_U)) {
j = i << 8; j = i << 8;

12
rEFIt_UEFI/Platform/cpu.cpp
View File

@ -287,6 +287,8 @@ void GetCPUProperties (void)
gCPUStructure.Turbo = ((gCPUStructure.CPUID[CPUID_6][EAX] & BIT1) != 0); gCPUStructure.Turbo = ((gCPUStructure.CPUID[CPUID_6][EAX] & BIT1) != 0);
DBG(" The CPU%s supported turbo\n", gCPUStructure.Turbo?"":" not"); DBG(" The CPU%s supported turbo\n", gCPUStructure.Turbo?"":" not");
//get cores and threads //get cores and threads
BOOLEAN PerfBias = (gCPUStructure.CPUID[CPUID_6][ECX] & BIT3) != 0;
DBG(" Energy PerfBias is %s visible:\n", PerfBias?"":" not");
switch (gCPUStructure.Model) switch (gCPUStructure.Model)
{ {
case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)
@ -324,8 +326,10 @@ void GetCPUProperties (void)
case CPU_MODEL_COMETLAKE_S: case CPU_MODEL_COMETLAKE_S:
case CPU_MODEL_COMETLAKE_Y: case CPU_MODEL_COMETLAKE_Y:
case CPU_MODEL_COMETLAKE_U: case CPU_MODEL_COMETLAKE_U:
case CPU_MODEL_TIGERLAKE_C:
case CPU_MODEL_TIGERLAKE_D:
msr = AsmReadMsr64(MSR_CORE_THREAD_COUNT); //0x35 msr = AsmReadMsr64(MSR_CORE_THREAD_COUNT); //0x35
DBG("MSR 0x35 %16llX\n", msr); DBG("MSR 0x35 %16llX\n", msr);
gCPUStructure.Cores = (UINT8)bitfield((UINT32)msr, 31, 16); gCPUStructure.Cores = (UINT8)bitfield((UINT32)msr, 31, 16);
gCPUStructure.Threads = (UINT8)bitfield((UINT32)msr, 15, 0); gCPUStructure.Threads = (UINT8)bitfield((UINT32)msr, 15, 0);
break; break;
@ -515,7 +519,9 @@ void GetCPUProperties (void)
case CPU_MODEL_COMETLAKE_S: case CPU_MODEL_COMETLAKE_S:
case CPU_MODEL_COMETLAKE_Y: case CPU_MODEL_COMETLAKE_Y:
case CPU_MODEL_COMETLAKE_U: case CPU_MODEL_COMETLAKE_U:
gCPUStructure.TSCFrequency = MultU64x32(gCPUStructure.CurrentSpeed, Mega); //MHz -> Hz case CPU_MODEL_TIGERLAKE_C:
case CPU_MODEL_TIGERLAKE_D:
gCPUStructure.TSCFrequency = MultU64x32(gCPUStructure.CurrentSpeed, Mega); //MHz -> Hz
gCPUStructure.CPUFrequency = gCPUStructure.TSCFrequency; gCPUStructure.CPUFrequency = gCPUStructure.TSCFrequency;
@ -1393,6 +1399,8 @@ UINT16 GetAdvancedCpuType ()
case CPU_MODEL_COMETLAKE_S: case CPU_MODEL_COMETLAKE_S:
case CPU_MODEL_COMETLAKE_Y: case CPU_MODEL_COMETLAKE_Y:
case CPU_MODEL_COMETLAKE_U: case CPU_MODEL_COMETLAKE_U:
case CPU_MODEL_TIGERLAKE_C:
case CPU_MODEL_TIGERLAKE_D:
if (AsciiStrStr(gCPUStructure.BrandString, "Core(TM) i3")) if (AsciiStrStr(gCPUStructure.BrandString, "Core(TM) i3"))
return 0x905; // Core i3 - Apple doesn't use it return 0x905; // Core i3 - Apple doesn't use it
if (AsciiStrStr(gCPUStructure.BrandString, "Core(TM) i5")) if (AsciiStrStr(gCPUStructure.BrandString, "Core(TM) i5"))

30
rEFIt_UEFI/Platform/cpu.h
View File

@ -43,33 +43,35 @@
//#define CPU_MODEL_HASWELL_H 0x?? // Haswell H //#define CPU_MODEL_HASWELL_H 0x?? // Haswell H
#define CPU_MODEL_HASWELL_ULT 0x45 /* Haswell ULT */ #define CPU_MODEL_HASWELL_ULT 0x45 /* Haswell ULT */
#define CPU_MODEL_CRYSTALWELL 0x46 /* Haswell ULX CPUID_MODEL_CRYSTALWELL */ #define CPU_MODEL_CRYSTALWELL 0x46 /* Haswell ULX CPUID_MODEL_CRYSTALWELL */
#define CPU_MODEL_BROADWELL_HQ 0x47 /* E3-1200 v4 */ #define CPU_MODEL_BROADWELL_HQ 0x47 /* E3-1200 v4 5th */
#define CPU_MODEL_MERRIFIELD 0x4A /* Tangier */ #define CPU_MODEL_MERRIFIELD 0x4A /* Tangier */
#define CPU_MODEL_AIRMONT 0x4C /* CherryTrail / Braswell */ #define CPU_MODEL_AIRMONT 0x4C /* CherryTrail / Braswell */
#define CPU_MODEL_AVOTON 0x4D /* Avaton/Rangely */ #define CPU_MODEL_AVOTON 0x4D /* Avaton/Rangely */
#define CPU_MODEL_SKYLAKE_U 0x4E /* Skylake Mobile */ #define CPU_MODEL_SKYLAKE_U 0x4E /* Skylake Mobile */
#define CPU_MODEL_BROADWELL_E5 0x4F /* Xeon E5-2695 */ #define CPU_MODEL_BROADWELL_E5 0x4F /* Xeon E5-2695 5th */
#define CPU_MODEL_SKYLAKE_S 0x55 /* Skylake Server, Cooper Lake */ #define CPU_MODEL_SKYLAKE_S 0x55 /* Skylake Server, Cooper Lake */
#define CPU_MODEL_BROADWELL_DE 0x56 /* Xeon BroadWell */ #define CPU_MODEL_BROADWELL_DE 0x56 /* Xeon BroadWell 5th */
#define CPU_MODEL_KNIGHT 0x57 /* Knights Landing */ #define CPU_MODEL_KNIGHT 0x57 /* Knights Landing */
#define CPU_MODEL_MOOREFIELD 0x5A /* Annidale */ #define CPU_MODEL_MOOREFIELD 0x5A /* Annidale */
#define CPU_MODEL_GOLDMONT 0x5C /* Apollo Lake */ #define CPU_MODEL_GOLDMONT 0x5C /* Apollo Lake */
#define CPU_MODEL_ATOM_X3 0x5D /* Silvermont */ #define CPU_MODEL_ATOM_X3 0x5D /* Silvermont */
#define CPU_MODEL_SKYLAKE_D 0x5E /* Skylake Desktop */ #define CPU_MODEL_SKYLAKE_D 0x5E /* Skylake Desktop */
#define CPU_MODEL_DENVERTON 0x5F /* Goldmont Microserver */ #define CPU_MODEL_DENVERTON 0x5F /* Goldmont Microserver */
#define CPU_MODEL_CANNONLAKE 0x66 #define CPU_MODEL_CANNONLAKE 0x66 /* 8h generation Cannon Lake */
#define CPU_MODEL_ICELAKE_A 0x6A /* Xeon Ice Lake */ #define CPU_MODEL_ICELAKE_A 0x6A /* Xeon Ice Lake */
#define CPU_MODEL_ICELAKE_C 0x6C /* Xeon Ice Lake */ #define CPU_MODEL_ICELAKE_C 0x6C /* Xeon Ice Lake */
#define CPU_MODEL_ATOM_GM 0x7A /* Goldmont Plus */ #define CPU_MODEL_ATOM_GM 0x7A /* Goldmont Plus */
#define CPU_MODEL_ICELAKE_D 0x7D #define CPU_MODEL_ICELAKE_D 0x7D /* 10h Ice Lake */
#define CPU_MODEL_ICELAKE 0x7E #define CPU_MODEL_ICELAKE 0x7E /* 10h Ice Lake */
#define CPU_MODEL_XEON_MILL 0x85 /* Knights Mill */ #define CPU_MODEL_XEON_MILL 0x85 /* Knights Mill */
#define CPU_MODEL_ATOM_TM 0x86 /* Tremont */ #define CPU_MODEL_ATOM_TM 0x86 /* Tremont */
#define CPU_MODEL_KABYLAKE1 0x8E /* Kabylake Mobile */ #define CPU_MODEL_TIGERLAKE_C 0x8C /* 11h generation Tiger Lake */
#define CPU_MODEL_KABYLAKE2 0x9E /* Kabylake Dektop, CoffeeLake */ #define CPU_MODEL_TIGERLAKE_D 0x8D /* 11h generation Tiger Lake */
#define CPU_MODEL_KABYLAKE1 0x8E /* 7h Kabylake Mobile */
#define CPU_MODEL_KABYLAKE2 0x9E /* 7h CoffeeLake */
#define CPU_MODEL_COMETLAKE_S 0x9F /* desktop Comet Lake */ #define CPU_MODEL_COMETLAKE_S 0x9F /* desktop Comet Lake */
#define CPU_MODEL_COMETLAKE_Y 0xA5 /* aka 10th generation Amber Lake Y */ #define CPU_MODEL_COMETLAKE_Y 0xA5 /* 10h Comet Lake */
#define CPU_MODEL_COMETLAKE_U 0xA6 #define CPU_MODEL_COMETLAKE_U 0xA6 /* 10h Comet Lake */
#define CPU_VENDOR_INTEL 0x756E6547 #define CPU_VENDOR_INTEL 0x756E6547
#define CPU_VENDOR_AMD 0x68747541 #define CPU_VENDOR_AMD 0x68747541
@ -214,9 +216,13 @@ const char CPU_STRING_UNKNOWN[] = "Unknown CPU Type";
#define MSR_IA32_MISC_ENABLE 0x01A0 #define MSR_IA32_MISC_ENABLE 0x01A0
#define MSR_THERMAL_TARGET 0x01A2 /* TjMax limited use - not for Penryn or older */ #define MSR_THERMAL_TARGET 0x01A2 /* TjMax limited use - not for Penryn or older */
#define MSR_TURBO_RATIO_LIMIT 0x01AD /* limited use - not for Penryn or older */ #define MSR_TURBO_RATIO_LIMIT 0x01AD /* limited use - not for Penryn or older */
#define MSR_MISC_PWR_MGMT 0x01AA /* EIST Hardware Coordination Disable (R/W) */
/* defined for Goldmont, Nehalem, Sandy and up
* bit0=1 == disable
* bit1=1 == enable MSR 1B0
*/
#define IA32_ENERGY_PERF_BIAS 0x01B0 /* 0=fast 15=low energy If CPUID.6H:ECX[3] = 1 */
#define IA32_ENERGY_PERF_BIAS 0x01B0
//MSR 000001B0 0000-0000-0000-0005 //MSR 000001B0 0000-0000-0000-0005
#define MSR_PACKAGE_THERM_STATUS 0x01B1 #define MSR_PACKAGE_THERM_STATUS 0x01B1
//MSR 000001B1 0000-0000-8838-0000 //MSR 000001B1 0000-0000-8838-0000