From a27759ec865c69e2fc3abdbc7d636dd5f416ef12 Mon Sep 17 00:00:00 2001
From: Slice <sergey.slice@gmail.com>
Date: Mon, 2 Dec 2024 20:32:06 +0300
Subject: [PATCH] some settings for new processors Arrow Lake

Signed-off-by: Slice <sergey.slice@gmail.com>
---
 Include/IndustryStandard/ProcessorInfo.h | 1 +
 rEFIt_UEFI/Platform/StateGenerator.cpp   | 4 +++-
 rEFIt_UEFI/Platform/cpu.cpp              | 9 +++++++++
 rEFIt_UEFI/Platform/cpu.h                | 2 +-
 4 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/Include/IndustryStandard/ProcessorInfo.h b/Include/IndustryStandard/ProcessorInfo.h
index 08aa23a08..df72b95f7 100755
--- a/Include/IndustryStandard/ProcessorInfo.h
+++ b/Include/IndustryStandard/ProcessorInfo.h
@@ -204,6 +204,7 @@ enum {
 #define CPU_MODEL_RAPTORLAKE     0xB7  /* 13h Raptor Lake */
 #define CPU_MODEL_RAPTORLAKE_B   0xBF  /* 13h Raptor Lake, i5-13400h */
 #define CPU_MODEL_METEORLAKE     0xAA  /* 14h Meteor Lake */
+#define CPU_MODEL_ARROWLAKE		 0xC6
 
 #define CPU_SOCKET_UNKNOWN  0x02
 #define CPU_SOCKET_PGA478   0x0F
diff --git a/rEFIt_UEFI/Platform/StateGenerator.cpp b/rEFIt_UEFI/Platform/StateGenerator.cpp
index 63eeafa16..2f7c8ff6e 100644
--- a/rEFIt_UEFI/Platform/StateGenerator.cpp
+++ b/rEFIt_UEFI/Platform/StateGenerator.cpp
@@ -282,6 +282,7 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
           case CPU_MODEL_RAPTORLAKE_B:
           case CPU_MODEL_RAPTORLAKE:
           case CPU_MODEL_METEORLAKE:
+          case CPU_MODEL_ARROWLAKE:
           {
             maximum.Control.Control = RShiftU64(AsmReadMsr64(MSR_PLATFORM_INFO), 8) & 0xff;
             if (gSettings.ACPI.SSDT.MaxMultiplier) {
@@ -356,6 +357,7 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
                     (gCPUStructure.Model == CPU_MODEL_ALDERLAKE_ULT)  ||
                     (gCPUStructure.Model == CPU_MODEL_RAPTORLAKE_B) ||
                     (gCPUStructure.Model == CPU_MODEL_METEORLAKE) ||
+					(gCPUStructure.Model == CPU_MODEL_ARROWLAKE  ) ||
                     (gCPUStructure.Model == CPU_MODEL_COMETLAKE_S) ||
                     (gCPUStructure.Model == CPU_MODEL_COMETLAKE_Y) ||
                     (gCPUStructure.Model == CPU_MODEL_COMETLAKE_U)) {
@@ -377,7 +379,7 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
                 p_states_count++;
               }
             }
-            break;
+            break;//case CPU_MODEL_ARROWLAKE:
           }
           default:
             MsgLog ("Unsupported CPU (0x%X): P-States not generated !!!\n", gCPUStructure.Family);
diff --git a/rEFIt_UEFI/Platform/cpu.cpp b/rEFIt_UEFI/Platform/cpu.cpp
index c593cc894..2a97cc042 100644
--- a/rEFIt_UEFI/Platform/cpu.cpp
+++ b/rEFIt_UEFI/Platform/cpu.cpp
@@ -336,6 +336,7 @@ void GetCPUProperties (void)
       case CPU_MODEL_ALDERLAKE_ULT:
       case CPU_MODEL_RAPTORLAKE_B:
       case CPU_MODEL_METEORLAKE:
+      case CPU_MODEL_ARROWLAKE:
         msr = AsmReadMsr64(MSR_CORE_THREAD_COUNT);  //0x35
         DBG("MSR 0x35    %16llX\n", msr);
         gCPUStructure.Cores   = (UINT8)bitfield((UINT32)msr, 31, 16);
@@ -391,6 +392,9 @@ void GetCPUProperties (void)
     } else if ( gCPUStructure.BrandString.contains("W36") ) {
       gCPUStructure.Cores   = 6;
       gCPUStructure.Threads = 6;
+    } else if ( gCPUStructure.BrandString.contains("285K") ) {
+      gCPUStructure.Cores   = 24;
+      gCPUStructure.Threads = 24;
     } else { //other Penryn and Wolfdale
       gCPUStructure.Cores   = 0;
       gCPUStructure.Threads = 0;
@@ -535,6 +539,7 @@ void GetCPUProperties (void)
            case CPU_MODEL_RAPTORLAKE_B:
            case CPU_MODEL_RAPTORLAKE:
            case CPU_MODEL_METEORLAKE:
+           case CPU_MODEL_ARROWLAKE:
 
             gCPUStructure.TSCFrequency = MultU64x32(gCPUStructure.CurrentSpeed, Mega); //MHz -> Hz
              gCPUStructure.CPUFrequency = gCPUStructure.TSCFrequency;
@@ -1422,6 +1427,7 @@ UINT16 GetAdvancedCpuType()
           case CPU_MODEL_ROCKETLAKE:
           case CPU_MODEL_RAPTORLAKE:
           case CPU_MODEL_METEORLAKE:
+          case CPU_MODEL_ARROWLAKE:
             if ( gCPUStructure.BrandString.contains("Core(TM) i3") )
               return 0x905; // Core i3 - Apple doesn't use it
             if ( gCPUStructure.BrandString.contains("Core(TM) i5-1") )
@@ -1446,6 +1452,8 @@ UINT16 GetAdvancedCpuType()
               return 0xE05;
             if ( gCPUStructure.BrandString.contains("Xeon") )
               return 0xF01;
+            if ( gCPUStructure.BrandString.contains("Core(TM) Ultra") )
+              return 0x1009; // Core Ultra 9
             if (gCPUStructure.Cores <= 2) {
               return 0x605;
             }
@@ -1676,6 +1684,7 @@ MacModel GetDefaultModel()
       case CPU_MODEL_ROCKETLAKE:
       case CPU_MODEL_RAPTORLAKE:
       case CPU_MODEL_METEORLAKE:
+      case CPU_MODEL_ARROWLAKE:
         DefaultType = MacPro71;
         break;
       default:
diff --git a/rEFIt_UEFI/Platform/cpu.h b/rEFIt_UEFI/Platform/cpu.h
index 6ec56b5ee..50f7ecc4c 100644
--- a/rEFIt_UEFI/Platform/cpu.h
+++ b/rEFIt_UEFI/Platform/cpu.h
@@ -82,7 +82,7 @@
 #define CPU_MODEL_METEORLAKE    0xAA  /* 14h Meteor Lake */
 #define CPU_MODEL_RAPTORLAKE    0xB7  /* 13h Raptor Lake */
 #define CPU_MODEL_RAPTORLAKE_B  0xBF  /* 13h Raptor Lake, i5-13400h */
-
+#define CPU_MODEL_ARROWLAKE		0xC6
 
 #define CPU_VENDOR_INTEL        0x756E6547
 #define CPU_VENDOR_AMD          0x68747541