mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-11-10 09:40:53 +01:00
collect definitions
Signed-off-by: SergeySlice <sergey.slice@gmail.com>
This commit is contained in:
SergeySlice
parent
62f10b11a8
commit
ad2d256e46
@ -222,7 +222,7 @@ const radeon_card_info_t radeon_cards[] = {
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{ 0x6667, CHIP_FAMILY_HAINAN, "AMD Radeon R5 M230", kNull }, // Mobile
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{ 0x666F, CHIP_FAMILY_HAINAN, "AMD Radeon HD 8550M", kNull }, // Mobile R5 M230 in Lenovo
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/* Vega 20 */
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/* Vega 20 */
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{ 0x66AF, CHIP_FAMILY_VEGA20, "AMD Radeon VII", kNull },
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@ -337,7 +337,7 @@ const radeon_card_info_t radeon_cards[] = {
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{ 0x67E9, CHIP_FAMILY_BAFFIN, "AMD Radeon Polaris 11", kNull },
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{ 0x67EB, CHIP_FAMILY_BAFFIN, "AMD Radeon Polaris 11", kNull },
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{ 0x67EF, CHIP_FAMILY_BAFFIN, "AMD Radeon Pro 555", kAcre }, //fb=Caroni in 10.13.6
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{ 0x67FF, CHIP_FAMILY_BAFFIN, "AMD Radeon RX 560", kNull },
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{ 0x67FF, CHIP_FAMILY_BAFFIN, "AMD Radeon RX 560", kNull },
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// PITCAIRN
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{ 0x6800, CHIP_FAMILY_PITCAIRN, "AMD Radeon HD 7970M", kBuri }, // Mobile
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@ -513,6 +513,7 @@ const radeon_card_info_t radeon_cards[] = {
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// Navi15
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{ 0x7340, CHIP_FAMILY_NAVI10, "AMD Radeon RX5500", kNull },
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// Navi2x
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{ 0x73A5, CHIP_FAMILY_NAVI20, "AMD Radeon RX6950XT", kNull },
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{ 0x73AF, CHIP_FAMILY_NAVI20, "AMD Radeon RX6900XT", kNull },
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{ 0x73BF, CHIP_FAMILY_NAVI20, "AMD Radeon RX6800XT", kNull },
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{ 0x73EF, CHIP_FAMILY_NAVI20, "AMD Radeon RX6650XT", kNull },
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@ -1703,7 +1704,7 @@ XBool validate_rom(option_rom_header_t *rom_header, pci_dt_t *pci_dev)
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option_rom_pci_header_t *rom_pci_header;
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if (rom_header->signature != 0xaa55) {
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DBG("invalid ROM signature %hX\n", rom_header->signature);
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DBG("invalid ROM signature %hX\n", rom_header->signature);
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return false;
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}
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@ -1715,7 +1716,7 @@ XBool validate_rom(option_rom_header_t *rom_header, pci_dt_t *pci_dev)
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}
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if (rom_pci_header->vendor_id != pci_dev->vendor_id || rom_pci_header->device_id != pci_dev->device_id){
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DBG("invalid ROM vendor=%04hX deviceID=%04hX\n", rom_pci_header->vendor_id, rom_pci_header->device_id);
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DBG("invalid ROM vendor=%04hX deviceID=%04hX\n", rom_pci_header->vendor_id, rom_pci_header->device_id);
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return false;
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}
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@ -1728,8 +1729,8 @@ XBool load_vbios_file(UINT16 vendor_id, UINT16 device_id)
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UINTN bufferLen = 0;
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UINT8* buffer = 0;
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XStringW FileName = SWPrintf("ROM\\%04hX_%04hX.rom", vendor_id, device_id);
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if ( selfOem.oemDirExists() ) {
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XStringW FileName = SWPrintf("ROM\\%04hX_%04hX.rom", vendor_id, device_id);
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if ( selfOem.oemDirExists() ) {
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if (FileExists(&selfOem.getOemDir(), FileName)) {
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DBG("Found oem generic VBIOS ROM file (%04hX_%04hX.rom)\n", vendor_id, device_id);
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Status = egLoadFile(&selfOem.getOemDir(), FileName.wc_str(), &buffer, &bufferLen);
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@ -1737,7 +1738,7 @@ XBool load_vbios_file(UINT16 vendor_id, UINT16 device_id)
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}
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if ( Status == EFI_NOT_FOUND ) {
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if (FileExists(&self.getCloverDir(), FileName)){
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DBG("Found generic VBIOS ROM file (%04hX_%04hX.rom)\n", vendor_id, device_id);
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DBG("Found generic VBIOS ROM file (%04hX_%04hX.rom)\n", vendor_id, device_id);
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Status = egLoadFile(&self.getCloverDir(), FileName.wc_str(), &buffer, &bufferLen);
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}
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}
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@ -1748,7 +1749,7 @@ XBool load_vbios_file(UINT16 vendor_id, UINT16 device_id)
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card->rom = 0;
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return false;
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}
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DBG("Loaded ROM len=%llu\n", bufferLen);
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DBG("Loaded ROM len=%llu\n", bufferLen);
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card->rom_size = (UINT32)bufferLen;
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card->rom = (__typeof__(card->rom))AllocateZeroPool(bufferLen);
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if (!card->rom) {
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@ -1782,7 +1783,7 @@ void get_vram_size(void)
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card->vram_size = 128 << 20; //default 128Mb, this is minimum for OS
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if (gSettings.Graphics.VRAM != 0) {
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card->vram_size = gSettings.Graphics.VRAM << 20;
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DBG("Set VRAM from config=%lluMb\n", gSettings.Graphics.VRAM);
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DBG("Set VRAM from config=%lluMb\n", gSettings.Graphics.VRAM);
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// WRITEREG32(card->mmio, RADEON_CONFIG_MEMSIZE, card->vram_size);
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} else {
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if (chip_family >= CHIP_FAMILY_CEDAR) {
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@ -1801,11 +1802,11 @@ void get_vram_size(void)
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WRITEREG32(card->mmio, RADEON_CONFIG_MEMSIZE, (UINT32)card->vram_size);
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}
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}
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DBG("Set VRAM for %s =%lluMb\n", chip_family_name[card->info->chip_family], (UINT64)RShiftU64(card->vram_size, 20));
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DBG("Set VRAM for %s =%lluMb\n", chip_family_name[card->info->chip_family], (UINT64)RShiftU64(card->vram_size, 20));
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}
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gSettings.Graphics.VRAM = (UINT64)RShiftU64(card->vram_size, 20);
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DBG("ATI: get_vram_size returned 0x%llX\n", card->vram_size);
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DBG("ATI: get_vram_size returned 0x%llX\n", card->vram_size);
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}
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XBool read_vbios(XBool from_pci)
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@ -1814,13 +1815,13 @@ XBool read_vbios(XBool from_pci)
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if (from_pci) {
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rom_addr = (option_rom_header_t *)(UINTN)(pci_config_read32(card->pci_dev, PCI_EXPANSION_ROM_BASE) & ~0x7ff);
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DBG(" @0x%llX\n", (uintptr_t)rom_addr);
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DBG(" @0x%llX\n", (uintptr_t)rom_addr);
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} else {
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rom_addr = (option_rom_header_t *)(UINTN)0xc0000;
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}
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if (!validate_rom(rom_addr, card->pci_dev)) {
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DBG("There is no ROM @0x%llX\n", (uintptr_t)rom_addr);
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DBG("There is no ROM @0x%llX\n", (uintptr_t)rom_addr);
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// gBS->Stall(3000000);
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return false;
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}
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@ -1960,19 +1961,19 @@ XBool radeon_card_posted(void)
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#if 0
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//dump radeon registers after BIOS POST
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reg = (UINTN)REG32(card->mmio, RADEON_BIOS_0_SCRATCH);
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// DBG("BIOS_0_SCRATCH=0x%08llX, ", reg);
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// DBG("BIOS_0_SCRATCH=0x%08llX, ", reg);
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reg = (UINTN)REG32(card->mmio, RADEON_BIOS_1_SCRATCH);
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// DBG("1=0x%08llX, ", reg);
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// DBG("1=0x%08llX, ", reg);
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reg = (UINTN)REG32(card->mmio, RADEON_BIOS_2_SCRATCH);
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// DBG("2=0x%08llX, ", reg);
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// DBG("2=0x%08llX, ", reg);
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reg = (UINTN)REG32(card->mmio, RADEON_BIOS_3_SCRATCH);
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// DBG("3=0x%08llX, ", reg);
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// DBG("3=0x%08llX, ", reg);
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reg = (UINTN)REG32(card->mmio, RADEON_BIOS_4_SCRATCH);
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DBG("RADEON_BIOS_4_SCRATCH=0x%08llX, ", reg);
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DBG("RADEON_BIOS_4_SCRATCH=0x%08llX, ", reg);
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reg = (UINTN)REG32(card->mmio, RADEON_BIOS_5_SCRATCH);
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// DBG("5=0x%08llX, ", reg);
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// DBG("5=0x%08llX, ", reg);
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reg = (UINTN)REG32(card->mmio, RADEON_BIOS_6_SCRATCH);
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// DBG("6=0x%08llX\n", reg);
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// DBG("6=0x%08llX\n", reg);
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#endif
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// first check CRTCs
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@ -1983,13 +1984,13 @@ XBool radeon_card_posted(void)
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return false;
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}
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if (reg & RADEON_CRTC_EN) {
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DBG(" card posted because CRTC_EN, GEN_CNTL=%llX\n", reg);
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DBG(" card posted because CRTC_EN, GEN_CNTL=%llX\n", reg);
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return true;
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}
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// then check MEM_SIZE, in case something turned the crtcs off
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reg = (UINTN)REG32(card->mmio, R600_CONFIG_MEMSIZE);
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if (reg) {
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DBG(" card posted because CONFIG_MEMSIZE=0x%llX\n", reg);
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DBG(" card posted because CONFIG_MEMSIZE=0x%llX\n", reg);
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return true;
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}
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return false;
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@ -2054,7 +2055,7 @@ static XBool init_card(pci_dt_t *pci_dev)
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}
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if (!card->info || !card->info->device_id || !card->info->cfg_name) {
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DBG("Unsupported ATI card! Device ID: [%04hX:%04hX] Subsystem ID: [%08X] \n",
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DBG("Unsupported ATI card! Device ID: [%04hX:%04hX] Subsystem ID: [%08X] \n",
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pci_dev->vendor_id, pci_dev->device_id, pci_dev->subsys_id_union.subsys_id);
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DBG("search for brothers family\n");
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for (i = 0; radeon_cards[i].device_id ; i++) {
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@ -2077,9 +2078,9 @@ static XBool init_card(pci_dt_t *pci_dev)
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card->io = (UINT8 *)(UINTN)(pci_config_read32(pci_dev, PCI_BASE_ADDRESS_4) & ~0x03);
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Reg5 = (UINTN)(pci_config_read32(pci_dev, PCI_BASE_ADDRESS_5) & ~0x0f);
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ExpansionRom = pci_config_read32(pci_dev, PCI_EXPANSION_ROM_BASE); //0x30 as Chimera
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DBG("Framebuffer @0x%8llx MMIO @0x%8llx I/O Port @0x%8llx ROM Addr @0x%08llX\n",
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DBG("Framebuffer @0x%8llx MMIO @0x%8llx I/O Port @0x%8llx ROM Addr @0x%08llX\n",
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(UINTN)card->fb, (UINTN)card->mmio, (UINTN)card->io, ExpansionRom);
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DBG("PCI region 1 = 0x%8llX, region3 = 0x%8llX, region5 = 0x%8llX\n", Reg1, Reg3, Reg5);
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DBG("PCI region 1 = 0x%8llX, region3 = 0x%8llX, region5 = 0x%8llX\n", Reg1, Reg3, Reg5);
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if (card->info->chip_family >= CHIP_FAMILY_HAINAN && Reg5 != 0) {
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card->mmio = (UINT8 *)Reg5;
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DBG("Use region5 as MMIO space\n");
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@ -2129,12 +2130,12 @@ static XBool init_card(pci_dt_t *pci_dev)
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n_ports = card_configs[card->info->cfg_name].ports;
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// which means one of the fb's or kNull
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DBG("Framebuffer set to device's default: %s\n", card->cfg_name);
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DBG(" N ports defaults to %lld\n", n_ports);
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DBG(" N ports defaults to %lld\n", n_ports);
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}
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if (gSettings.Graphics.VideoPorts != 0) {
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n_ports = gSettings.Graphics.VideoPorts;
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DBG(" use N ports setting from config.plist: %lld\n", n_ports);
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DBG(" use N ports setting from config.plist: %lld\n", n_ports);
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}
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if (n_ports > 0) {
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@ -2246,7 +2247,7 @@ XBool setup_ati_devprop(LOADER_ENTRY *Entry, pci_dt_t *ati_dev)
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}
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}
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DBG("ATI %s %s %dMB (%s) [%04hX:%04hX] (subsys [%04hX:%04hX]):: %s\n",
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DBG("ATI %s %s %dMB (%s) [%04hX:%04hX] (subsys [%04hX:%04hX]):: %s\n",
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chip_family_name[card->info->chip_family], card->info->model_name,
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(UINT32)RShiftU64(card->vram_size, 20), card->cfg_name,
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ati_dev->vendor_id, ati_dev->device_id,
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@ -67,5 +67,230 @@ typedef struct pci_dt_t {
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XBool used = false;
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} pci_dt_t;
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#if 0
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//
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// Definitions of PCI class bytes and manipulation macros.
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//
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#define PCI_CLASS_OLD 0x00
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#define PCI_CLASS_OLD_OTHER 0x00
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#define PCI_CLASS_OLD_VGA 0x01
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#define PCI_CLASS_MASS_STORAGE 0x01
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#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
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#define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00
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#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11
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#define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12
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#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13
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#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21
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#define PCI_CLASS_MASS_STORAGE_IDE 0x01
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#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
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#define PCI_CLASS_MASS_STORAGE_IPI 0x03
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#define PCI_CLASS_MASS_STORAGE_RAID 0x04
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#define PCI_CLASS_MASS_STORAGE_ATA 0x05
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#define PCI_IF_MASS_STORAGE_SINGLE_DMA 0x20
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#define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30
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#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06
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#define PCI_IF_MASS_STORAGE_SATA 0x00
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#define PCI_IF_MASS_STORAGE_AHCI 0x01
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#define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02
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#define PCI_CLASS_MASS_STORAGE_SAS 0x07
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#define PCI_IF_MASS_STORAGE_SAS 0x00
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#define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01
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#define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08
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#define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00
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#define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01
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#define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02
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#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
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#define PCI_CLASS_NETWORK 0x02
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#define PCI_CLASS_NETWORK_ETHERNET 0x00
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#define PCI_CLASS_NETWORK_TOKENRING 0x01
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#define PCI_CLASS_NETWORK_FDDI 0x02
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#define PCI_CLASS_NETWORK_ATM 0x03
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#define PCI_CLASS_NETWORK_ISDN 0x04
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#define PCI_CLASS_NETWORK_WORLDFIP 0x05
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#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06
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#define PCI_CLASS_NETWORK_INFINIBAND 0x07
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#define PCI_CLASS_NETWORK_OTHER 0x80
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#define PCI_CLASS_DISPLAY 0x03
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#define PCI_CLASS_DISPLAY_VGA 0x00
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#define PCI_IF_VGA_VGA 0x00
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#define PCI_IF_VGA_8514 0x01
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#define PCI_CLASS_DISPLAY_XGA 0x01
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#define PCI_CLASS_DISPLAY_3D 0x02
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#define PCI_CLASS_DISPLAY_OTHER 0x80
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#define PCI_CLASS_MEDIA 0x04
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#define PCI_CLASS_MEDIA_VIDEO 0x00
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#define PCI_CLASS_MEDIA_AUDIO 0x01
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#define PCI_CLASS_MEDIA_TELEPHONE 0x02
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#define PCI_CLASS_MEDIA_HDA 0x03
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#define PCI_CLASS_MEDIA_MIXED_MODE 0x03 //other name
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#define PCI_CLASS_MEDIA_OTHER 0x80
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#define PCI_CLASS_MEMORY_CONTROLLER 0x05
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#define PCI_CLASS_MEMORY_RAM 0x00
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#define PCI_CLASS_MEMORY_FLASH 0x01
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#define PCI_CLASS_MEMORY_OTHER 0x80
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#define PCI_CLASS_BRIDGE 0x06
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#define PCI_CLASS_BRIDGE_HOST 0x00
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#define PCI_CLASS_BRIDGE_ISA 0x01
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#define PCI_CLASS_BRIDGE_EISA 0x02
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#define PCI_CLASS_BRIDGE_MCA 0x03
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#define PCI_CLASS_BRIDGE_P2P 0x04
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#define PCI_IF_BRIDGE_P2P 0x00
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#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
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#define PCI_CLASS_BRIDGE_PCMCIA 0x05
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#define PCI_CLASS_BRIDGE_NUBUS 0x06
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#define PCI_CLASS_BRIDGE_CARDBUS 0x07
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#define PCI_CLASS_BRIDGE_RACEWAY 0x08
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#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09
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#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40
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#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80
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#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A
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#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B
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#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00
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#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01
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#define PCI_CLASS_BRIDGE_OTHER 0x80
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#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
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#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers
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#define PCI_SUBCLASS_SERIAL 0x00
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#define PCI_IF_GENERIC_XT 0x00
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#define PCI_IF_16450 0x01
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#define PCI_IF_16550 0x02
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#define PCI_IF_16650 0x03
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#define PCI_IF_16750 0x04
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#define PCI_IF_16850 0x05
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#define PCI_IF_16950 0x06
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#define PCI_SUBCLASS_PARALLEL 0x01
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#define PCI_IF_PARALLEL_PORT 0x00
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#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
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#define PCI_IF_ECP_PARALLEL_PORT 0x02
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#define PCI_IF_1284_CONTROLLER 0x03
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#define PCI_IF_1284_DEVICE 0xFE
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#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
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#define PCI_SUBCLASS_MODEM 0x03
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#define PCI_IF_GENERIC_MODEM 0x00
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#define PCI_IF_16450_MODEM 0x01
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#define PCI_IF_16550_MODEM 0x02
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#define PCI_IF_16650_MODEM 0x03
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#define PCI_IF_16750_MODEM 0x04
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#define PCI_SUBCLASS_GPIB 0x04
|
||||
#define PCI_SUBCLASS_SMART_CARD 0x05
|
||||
#define PCI_SUBCLASS_SCC_OTHER 0x80
|
||||
|
||||
#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
|
||||
#define PCI_SUBCLASS_PIC 0x00
|
||||
#define PCI_IF_8259_PIC 0x00
|
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#define PCI_IF_ISA_PIC 0x01
|
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#define PCI_IF_EISA_PIC 0x02
|
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#define PCI_IF_HPET 0x03
|
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#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
|
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#define PCI_IF_APIC_CONTROLLER2 0x20
|
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#define PCI_SUBCLASS_DMA 0x01
|
||||
#define PCI_IF_8237_DMA 0x00
|
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#define PCI_IF_ISA_DMA 0x01
|
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#define PCI_IF_EISA_DMA 0x02
|
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#define PCI_SUBCLASS_TIMER 0x02
|
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#define PCI_IF_8254_TIMER 0x00
|
||||
#define PCI_IF_ISA_TIMER 0x01
|
||||
#define PCI_IF_EISA_TIMER 0x02
|
||||
#define PCI_SUBCLASS_RTC 0x03
|
||||
#define PCI_IF_GENERIC_RTC 0x00
|
||||
#define PCI_IF_ISA_RTC 0x01
|
||||
#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller
|
||||
#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
|
||||
#define PCI_SUBCLASS_IOMMU 0x06
|
||||
#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
|
||||
|
||||
#define PCI_CLASS_INPUT_DEVICE 0x09
|
||||
#define PCI_SUBCLASS_KEYBOARD 0x00
|
||||
#define PCI_SUBCLASS_PEN 0x01
|
||||
#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
|
||||
#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
|
||||
#define PCI_SUBCLASS_GAMEPORT 0x04
|
||||
#define PCI_IF_GAMEPORT 0x00
|
||||
#define PCI_IF_GAMEPORT1 0x10
|
||||
#define PCI_SUBCLASS_INPUT_OTHER 0x80
|
||||
|
||||
#define PCI_CLASS_DOCKING_STATION 0x0A
|
||||
#define PCI_SUBCLASS_DOCKING_GENERIC 0x00
|
||||
#define PCI_SUBCLASS_DOCKING_OTHER 0x80
|
||||
|
||||
#define PCI_CLASS_PROCESSOR 0x0B
|
||||
#define PCI_SUBCLASS_PROC_386 0x00
|
||||
#define PCI_SUBCLASS_PROC_486 0x01
|
||||
#define PCI_SUBCLASS_PROC_PENTIUM 0x02
|
||||
#define PCI_SUBCLASS_PROC_ALPHA 0x10
|
||||
#define PCI_SUBCLASS_PROC_POWERPC 0x20
|
||||
#define PCI_SUBCLASS_PROC_MIPS 0x30
|
||||
#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor
|
||||
#define PCI_SUBCLASS_PROC_OTHER 0x80
|
||||
|
||||
#define PCI_CLASS_SERIAL 0x0C
|
||||
#define PCI_CLASS_SERIAL_FIREWIRE 0x00
|
||||
#define PCI_IF_1394 0x00
|
||||
#define PCI_IF_1394_OPEN_HCI 0x10
|
||||
#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
|
||||
#define PCI_CLASS_SERIAL_SSA 0x02
|
||||
#define PCI_CLASS_SERIAL_USB 0x03
|
||||
#define PCI_IF_UHCI 0x00
|
||||
#define PCI_IF_OHCI 0x10
|
||||
#define PCI_IF_EHCI 0x20
|
||||
#define PCI_IF_XHCI 0x30
|
||||
#define PCI_IF_USB_OTHER 0x80
|
||||
#define PCI_IF_USB_DEVICE 0xFE
|
||||
#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
|
||||
#define PCI_CLASS_SERIAL_SMB 0x05
|
||||
#define PCI_CLASS_SERIAL_IB 0x06
|
||||
#define PCI_CLASS_SERIAL_IPMI 0x07
|
||||
#define PCI_IF_IPMI_SMIC 0x00
|
||||
#define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style
|
||||
#define PCI_IF_IPMI_BT 0x02 ///< Block Transfer
|
||||
#define PCI_CLASS_SERIAL_SERCOS 0x08
|
||||
#define PCI_CLASS_SERIAL_CANBUS 0x09
|
||||
#define PCI_CLASS_SERIAL_OTHER 0x80
|
||||
|
||||
|
||||
|
||||
#define PCI_CLASS_WIRELESS 0x0D
|
||||
#define PCI_SUBCLASS_IRDA 0x00
|
||||
#define PCI_SUBCLASS_IR 0x01
|
||||
#define PCI_SUBCLASS_RF 0x10
|
||||
#define PCI_SUBCLASS_BLUETOOTH 0x11
|
||||
#define PCI_SUBCLASS_BROADBAND 0x12
|
||||
#define PCI_SUBCLASS_ETHERNET_80211A 0x20
|
||||
#define PCI_SUBCLASS_ETHERNET_80211B 0x21
|
||||
#define PCI_SUBCLASS_WIRELESS_OTHER 0x80
|
||||
|
||||
#define PCI_CLASS_INTELLIGENT_IO 0x0E
|
||||
|
||||
#define PCI_CLASS_SATELLITE 0x0F
|
||||
#define PCI_SUBCLASS_TV 0x01
|
||||
#define PCI_SUBCLASS_AUDIO 0x02
|
||||
#define PCI_SUBCLASS_VOICE 0x03
|
||||
#define PCI_SUBCLASS_DATA 0x04
|
||||
#define PCI_SUBCLASS_SATELLITE_OTHER 0x80
|
||||
|
||||
#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller
|
||||
#define PCI_SUBCLASS_NET_COMPUT 0x00
|
||||
#define PCI_SUBCLASS_ENTERTAINMENT 0x10
|
||||
#define PCI_SUBCLASS_SECURITY_OTHER 0x80
|
||||
|
||||
#define PCI_CLASS_DPIO 0x11
|
||||
#define PCI_SUBCLASS_DPIO 0x00
|
||||
#define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01
|
||||
#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10
|
||||
#define PCI_SUBCLASS_MANAGEMENT_CARD 0x20
|
||||
#define PCI_SUBCLASS_DPIO_OTHER 0x80
|
||||
|
||||
#define PCI_CLASS_PROCESSING_ACCELERATOR 0x12
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* INCLUDE_PCI_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user