diff --git a/Include/IndustryStandard/ProcessorInfo.h b/Include/IndustryStandard/ProcessorInfo.h index b5ae679fa..04789e477 100755 --- a/Include/IndustryStandard/ProcessorInfo.h +++ b/Include/IndustryStandard/ProcessorInfo.h @@ -200,7 +200,7 @@ enum { #define CPU_MODEL_TIGERLAKE_D 0x8D /* 11h generation Tiger Lake */ #define CPU_MODEL_ALDERLAKE 0x97 /* 12h generation Alder Lake */ #define CPU_MODEL_ROCKETLAKE 0xA7 /* 11h Rocket Lake */ - +#define CPU_MODEL_RAPTORLAKE 0xB7 /* 13h Raptor Lake */ #define CPU_SOCKET_UNKNOWN 0x02 #define CPU_SOCKET_PGA478 0x0F diff --git a/MdePkg/Include/Protocol/MpService.h b/MdePkg/Include/Protocol/MpService.h index 8c7018eb0..e3a7244fc 100644 --- a/MdePkg/Include/Protocol/MpService.h +++ b/MdePkg/Include/Protocol/MpService.h @@ -79,7 +79,7 @@ typedef struct _EFI_MP_SERVICES_PROTOCOL EFI_MP_SERVICES_PROTOCOL; #define PROCESSOR_HEALTH_STATUS_BIT 0x00000004 /// -/// Structure that describes the pyhiscal location of a logical CPU. +/// Structure that describes the physical location of a logical CPU. /// typedef struct { /// diff --git a/rEFIt_UEFI/Platform/StateGenerator.cpp b/rEFIt_UEFI/Platform/StateGenerator.cpp index 3736468e4..3f84e83b1 100644 --- a/rEFIt_UEFI/Platform/StateGenerator.cpp +++ b/rEFIt_UEFI/Platform/StateGenerator.cpp @@ -277,7 +277,8 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number) case CPU_MODEL_TIGERLAKE_D: case CPU_MODEL_ALDERLAKE: case CPU_MODEL_ROCKETLAKE: - { + case CPU_MODEL_RAPTORLAKE: + { maximum.Control.Control = RShiftU64(AsmReadMsr64(MSR_PLATFORM_INFO), 8) & 0xff; if (gSettings.ACPI.SSDT.MaxMultiplier) { DBG("Using custom MaxMultiplier %d instead of automatic %d\n", @@ -346,7 +347,8 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number) (gCPUStructure.Model == CPU_MODEL_TIGERLAKE_C) || (gCPUStructure.Model == CPU_MODEL_TIGERLAKE_D) || (gCPUStructure.Model == CPU_MODEL_ROCKETLAKE) || - (gCPUStructure.Model == CPU_MODEL_ALDERLAKE) || + (gCPUStructure.Model == CPU_MODEL_ALDERLAKE) || + (gCPUStructure.Model == CPU_MODEL_RAPTORLAKE) || (gCPUStructure.Model == CPU_MODEL_COMETLAKE_S) || (gCPUStructure.Model == CPU_MODEL_COMETLAKE_Y) || (gCPUStructure.Model == CPU_MODEL_COMETLAKE_U)) { diff --git a/rEFIt_UEFI/Platform/cpu.cpp b/rEFIt_UEFI/Platform/cpu.cpp index 35367e818..7aec0f0c8 100755 --- a/rEFIt_UEFI/Platform/cpu.cpp +++ b/rEFIt_UEFI/Platform/cpu.cpp @@ -328,6 +328,7 @@ void GetCPUProperties (void) case CPU_MODEL_TIGERLAKE_D: case CPU_MODEL_ALDERLAKE: case CPU_MODEL_ROCKETLAKE: + case CPU_MODEL_RAPTORLAKE: msr = AsmReadMsr64(MSR_CORE_THREAD_COUNT); //0x35 DBG("MSR 0x35 %16llX\n", msr); gCPUStructure.Cores = (UINT8)bitfield((UINT32)msr, 31, 16); @@ -523,6 +524,7 @@ void GetCPUProperties (void) case CPU_MODEL_TIGERLAKE_D: case CPU_MODEL_ALDERLAKE: case CPU_MODEL_ROCKETLAKE: + case CPU_MODEL_RAPTORLAKE: gCPUStructure.TSCFrequency = MultU64x32(gCPUStructure.CurrentSpeed, Mega); //MHz -> Hz gCPUStructure.CPUFrequency = gCPUStructure.TSCFrequency; @@ -1402,6 +1404,7 @@ UINT16 GetAdvancedCpuType() case CPU_MODEL_TIGERLAKE_D: case CPU_MODEL_ALDERLAKE: case CPU_MODEL_ROCKETLAKE: + case CPU_MODEL_RAPTORLAKE: if ( gCPUStructure.BrandString.contains("Core(TM) i3") ) return 0x905; // Core i3 - Apple doesn't use it if ( gCPUStructure.BrandString.contains("Core(TM) i5-1") ) @@ -1651,6 +1654,7 @@ MacModel GetDefaultModel() break; case CPU_MODEL_ALDERLAKE: case CPU_MODEL_COMETLAKE_S: + case CPU_MODEL_RAPTORLAKE: DefaultType = MacPro71; break; default: diff --git a/rEFIt_UEFI/Platform/cpu.h b/rEFIt_UEFI/Platform/cpu.h index d2b69f6f9..e03fdca1d 100644 --- a/rEFIt_UEFI/Platform/cpu.h +++ b/rEFIt_UEFI/Platform/cpu.h @@ -78,6 +78,7 @@ #define CPU_MODEL_COMETLAKE_Y 0xA5 /* 10h Comet Lake */ #define CPU_MODEL_COMETLAKE_U 0xA6 /* 10h Comet Lake */ #define CPU_MODEL_ROCKETLAKE 0xA7 /* 11h Rocket Lake */ +#define CPU_MODEL_RAPTORLAKE 0xB7 /* 11h Raptor Lake */ #define CPU_VENDOR_INTEL 0x756E6547 #define CPU_VENDOR_AMD 0x68747541