mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-11-12 09:54:36 +01:00
update IndustryStandards
Signed-off-by: SergeySlice <sergey.slice@gmail.com>
This commit is contained in:
parent
5bc175a753
commit
f28e98fb33
@ -92,6 +92,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
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#define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41
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#define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42
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#define SMBIOS_TYPE_TPM_DEVICE 43
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#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION 44
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///
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/// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.
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@ -727,7 +728,10 @@ typedef enum {
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ProcessorFamilyMII = 0x012E,
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ProcessorFamilyWinChip = 0x0140,
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ProcessorFamilyDSP = 0x015E,
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ProcessorFamilyVideoProcessor = 0x01F4
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ProcessorFamilyVideoProcessor = 0x01F4,
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ProcessorFamilyRiscvRV32 = 0x0200,
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ProcessorFamilyRiscVRV64 = 0x0201,
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ProcessorFamilyRiscVRV128 = 0x0202
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} PROCESSOR_FAMILY2_DATA;
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///
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@ -856,6 +860,33 @@ typedef struct {
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UINT32 ProcessorReserved4 :2;
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} PROCESSOR_FEATURE_FLAGS;
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typedef struct {
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UINT16 ProcessorReserved1 :1;
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UINT16 ProcessorUnknown :1;
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UINT16 Processor64BitCapable :1;
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UINT16 ProcessorMultiCore :1;
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UINT16 ProcessorHardwareThread :1;
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UINT16 ProcessorExecuteProtection :1;
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UINT16 ProcessorEnhancedVirtualization :1;
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UINT16 ProcessorPowerPerformanceCtrl :1;
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UINT16 Processor128BitCapable :1;
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UINT16 ProcessorArm64SocId :1;
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UINT16 ProcessorReserved2 :6;
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} PROCESSOR_CHARACTERISTIC_FLAGS;
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///
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/// Processor Information - Status
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///
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typedef union {
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struct {
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UINT8 CpuStatus :3; ///< Indicates the status of the processor.
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UINT8 Reserved1 :3; ///< Reserved for future use. Must be set to zero.
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UINT8 SocketPopulated :1; ///< Indicates if the processor socket is populated or not.
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UINT8 Reserved2 :1; ///< Reserved for future use. Must be set to zero.
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} Bits;
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UINT8 Data;
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} PROCESSOR_STATUS_DATA;
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typedef struct {
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PROCESSOR_SIGNATURE Signature;
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PROCESSOR_FEATURE_FLAGS FeatureFlags;
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@ -1289,7 +1320,13 @@ typedef enum {
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SlotTypePciExpressGen3X2 = 0xB3,
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SlotTypePciExpressGen3X4 = 0xB4,
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SlotTypePciExpressGen3X8 = 0xB5,
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SlotTypePciExpressGen3X16 = 0xB6
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SlotTypePciExpressGen3X16 = 0xB6,
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SlotTypePciExpressGen4 = 0xB8,
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SlotTypePciExpressGen4X1 = 0xB9,
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SlotTypePciExpressGen4X2 = 0xBA,
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SlotTypePciExpressGen4X4 = 0xBB,
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SlotTypePciExpressGen4X8 = 0xBC,
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SlotTypePciExpressGen4X16 = 0xBD
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} MISC_SLOT_TYPE;
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///
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@ -1689,7 +1726,11 @@ typedef enum {
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MemoryTypeLpddr2 = 0x1C,
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MemoryTypeLpddr3 = 0x1D,
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MemoryTypeLpddr4 = 0x1E,
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MemoryTypeLogicalNonVolatileDevice = 0x1F
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MemoryTypeLogicalNonVolatileDevice = 0x1F,
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MemoryTypeHBM = 0x20,
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MemoryTypeHBM2 = 0x21,
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MemoryTypeDdr5 = 0x22,
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MemoryTypeLpddr5 = 0x23
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} MEMORY_DEVICE_TYPE;
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///
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@ -2508,6 +2549,34 @@ typedef struct {
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UINT8 InterfaceTypeSpecificData[4]; ///< This field has a minimum of four bytes
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} SMBIOS_TABLE_TYPE42;
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///
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/// Processor Specific Block - Processor Architecture Type
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///
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typedef enum{
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ProcessorSpecificBlockArchTypeReserved = 0x00,
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ProcessorSpecificBlockArchTypeIa32 = 0x01,
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ProcessorSpecificBlockArchTypeX64 = 0x02,
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ProcessorSpecificBlockArchTypeItanium = 0x03,
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ProcessorSpecificBlockArchTypeAarch32 = 0x04,
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ProcessorSpecificBlockArchTypeAarch64 = 0x05,
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ProcessorSpecificBlockArchTypeRiscVRV32 = 0x06,
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ProcessorSpecificBlockArchTypeRiscVRV64 = 0x07,
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ProcessorSpecificBlockArchTypeRiscVRV128 = 0x08
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} PROCESSOR_SPECIFIC_BLOCK_ARCH_TYPE;
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///
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/// Processor Specific Block is the standard container of processor-specific data.
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///
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typedef struct {
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UINT8 Length;
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UINT8 ProcessorArchType;
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///
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/// Below followed by Processor-specific data
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///
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///
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} PROCESSOR_SPECIFIC_BLOCK;
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///
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/// TPM Device (Type 43).
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///
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@ -2523,6 +2592,30 @@ typedef struct {
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UINT32 OemDefined;
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} SMBIOS_TABLE_TYPE43;
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///
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/// Processor Additional Information(Type 44).
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///
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/// The information in this structure defines the processor additional information in case
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/// SMBIOS type 4 is not sufficient to describe processor characteristics.
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/// The SMBIOS type 44 structure has a reference handle field to link back to the related
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/// SMBIOS type 4 structure. There may be multiple SMBIOS type 44 structures linked to the
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/// same SMBIOS type 4 structure. For example, when cores are not identical in a processor,
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/// SMBIOS type 44 structures describe different core-specific information.
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///
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/// SMBIOS type 44 defines the standard header for the processor-specific block, while the
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/// contents of processor-specific data are maintained by processor
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/// architecture workgroups or vendors in separate documents.
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///
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typedef struct {
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SMBIOS_STRUCTURE Hdr;
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SMBIOS_HANDLE RefHandle; ///< This field refer to associated SMBIOS type 4
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///
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/// Below followed by Processor-specific block
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///
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PROCESSOR_SPECIFIC_BLOCK ProcessorSpecificBlock;
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} SMBIOS_TABLE_TYPE44;
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///
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/// Inactive (Type 126)
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///
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@ -2586,6 +2679,7 @@ typedef union {
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SMBIOS_TABLE_TYPE41 *Type41;
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SMBIOS_TABLE_TYPE42 *Type42;
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SMBIOS_TABLE_TYPE43 *Type43;
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SMBIOS_TABLE_TYPE44 *Type44;
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SMBIOS_TABLE_TYPE126 *Type126;
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SMBIOS_TABLE_TYPE127 *Type127;
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UINT8 *Raw;
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@ -13843,86 +13843,86 @@
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A5814B6E2538171000CF4451 /* IndustryStandard */ = {
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isa = PBXGroup;
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children = (
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A5814B6F2538171000CF4451 /* IpmiNetFnFirmware.h */,
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A5814B702538171000CF4451 /* SdramSpdLpDdr.h */,
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A5814B712538171000CF4451 /* ElTorito.h */,
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A5814B722538171000CF4451 /* SdramSpdDdr3.h */,
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A5814B732538171000CF4451 /* Acpi62.h */,
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A5814B742538171000CF4451 /* WindowsSmmSecurityMitigationTable.h */,
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A5814B752538171000CF4451 /* Nvme.h */,
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A5814B762538171000CF4451 /* IoRemappingTable.h */,
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A5814B772538171000CF4451 /* LowPowerIdleTable.h */,
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A5814B782538171000CF4451 /* Emmc.h */,
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A5814B792538171000CF4451 /* WatchdogActionTable.h */,
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A5814B7A2538171000CF4451 /* DmaRemappingReportingTable.h */,
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A5814B7B2538171000CF4451 /* AlertStandardFormatTable.h */,
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A5814B7C2538171000CF4451 /* Acpi40.h */,
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A5814B7D2538171000CF4451 /* Bmp.h */,
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A5814B7E2538171000CF4451 /* UefiTcgPlatform.h */,
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A5814B7F2538171000CF4451 /* SerialPortConsoleRedirectionTable.h */,
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A5814B802538171000CF4451 /* Pci22.h */,
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A5814B812538171000CF4451 /* Mbr.h */,
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A5814B822538171000CF4451 /* Acpi61.h */,
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A5814B832538171000CF4451 /* SdramSpdDdr4.h */,
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A5814B842538171000CF4451 /* TcgStorageOpal.h */,
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A5814B852538171000CF4451 /* IpmiNetFnChassis.h */,
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A5814B862538171000CF4451 /* Acpi.h */,
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A5814B872538171000CF4451 /* Tpm2Acpi.h */,
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A5814B882538171000CF4451 /* PeImage.h */,
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A5814B892538171000CF4451 /* PciExpress30.h */,
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A5814B8A2538171000CF4451 /* SdramSpd.h */,
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A5814B8B2538171000CF4451 /* Acpi10.h */,
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A5814B8C2538171000CF4451 /* MemoryMappedConfigurationSpaceAccessTable.h */,
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A5814B8D2538171000CF4451 /* IpmiFruInformationStorage.h */,
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A5814B8E2538171000CF4451 /* IpmiNetFnStorage.h */,
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A5814B8F2538171000CF4451 /* IScsiBootFirmwareTable.h */,
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A5814B902538171000CF4451 /* Bluetooth.h */,
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A5814B912538171000CF4451 /* AcpiAml.h */,
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A5814B922538171000CF4451 /* Acpi50.h */,
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A5814B932538171000CF4451 /* Tpm20.h */,
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A5814B942538171000CF4451 /* PciCodeId.h */,
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A5814B952538171000CF4451 /* IpmiNetFnTransport.h */,
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A5814B962538171000CF4451 /* Dhcp.h */,
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A5814B972538171000CF4451 /* TpmPtp.h */,
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A5814B982538171000CF4451 /* Acpi20.h */,
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A5814B992538171000CF4451 /* Pci23.h */,
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A5814B9A2538171000CF4451 /* IpmiNetFnApp.h */,
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A5814B9B2538171000CF4451 /* PciExpress40.h */,
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A5814B9C2538171000CF4451 /* IpmiNetFnSensorEvent.h */,
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A5814B9D2538171000CF4451 /* Acpi60.h */,
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A5814B9E2538171000CF4451 /* PciExpress21.h */,
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A5814B9F2538171000CF4451 /* PciExpress31.h */,
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A5814BA02538171000CF4451 /* TcgStorageCore.h */,
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A5814BA12538171000CF4451 /* HighPrecisionEventTimerTable.h */,
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A5814BA22538171000CF4451 /* Usb.h */,
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A5814BA32538171000CF4451 /* Acpi51.h */,
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A5814BA42538171000CF4451 /* Sd.h */,
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A5814BA52538171000CF4451 /* WatchdogResourceTable.h */,
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A5814BA62538171000CF4451 /* Acpi30.h */,
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A5814BA72538171000CF4451 /* Udf.h */,
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A5814BA82538171000CF4451 /* DebugPortTable.h */,
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A5814BA92538171000CF4451 /* SmBios.h */,
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A5814BAA2538171000CF4451 /* MemoryOverwriteRequestControlLock.h */,
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A5814BAB2538171000CF4451 /* Atapi.h */,
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A5814BAC2538171000CF4451 /* TcpaAcpi.h */,
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A5814BAD2538171000CF4451 /* LegacyBiosMpTable.h */,
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A5814BAE2538171000CF4451 /* TpmTis.h */,
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A5814B7C2538171000CF4451 /* Acpi40.h */,
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A5814B922538171000CF4451 /* Acpi50.h */,
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A5814BA32538171000CF4451 /* Acpi51.h */,
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A5814B9D2538171000CF4451 /* Acpi60.h */,
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A5814B822538171000CF4451 /* Acpi61.h */,
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A5814B732538171000CF4451 /* Acpi62.h */,
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A5814BAF2538171000CF4451 /* Acpi63.h */,
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A5814BB02538171000CF4451 /* SmBus.h */,
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A5814BB12538171000CF4451 /* Http11.h */,
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A5814BB22538171000CF4451 /* TcgPhysicalPresence.h */,
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A5814BB32538171000CF4451 /* IpmiNetFnGroupExtension.h */,
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A5814BB42538171000CF4451 /* Tls1.h */,
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A5814BB52538171000CF4451 /* Pci.h */,
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A5814B912538171000CF4451 /* AcpiAml.h */,
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A5814B7B2538171000CF4451 /* AlertStandardFormatTable.h */,
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A5814BAB2538171000CF4451 /* Atapi.h */,
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A5814B902538171000CF4451 /* Bluetooth.h */,
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A5814B7D2538171000CF4451 /* Bmp.h */,
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A5814BB62538171000CF4451 /* DebugPort2Table.h */,
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A5814BB72538171000CF4451 /* Scsi.h */,
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A5814BB82538171000CF4451 /* Pci30.h */,
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A5814BA82538171000CF4451 /* DebugPortTable.h */,
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A5814B962538171000CF4451 /* Dhcp.h */,
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A5814B7A2538171000CF4451 /* DmaRemappingReportingTable.h */,
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A5814B712538171000CF4451 /* ElTorito.h */,
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A5814B782538171000CF4451 /* Emmc.h */,
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A5814BA12538171000CF4451 /* HighPrecisionEventTimerTable.h */,
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A5814BB92538171000CF4451 /* Hsti.h */,
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A5814BBA2538171000CF4451 /* WindowsUxCapsule.h */,
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A5814BBB2538171000CF4451 /* Tpm12.h */,
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A5814BB12538171000CF4451 /* Http11.h */,
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A5814B762538171000CF4451 /* IoRemappingTable.h */,
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A5814BBC2538171000CF4451 /* Ipmi.h */,
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A5814B8D2538171000CF4451 /* IpmiFruInformationStorage.h */,
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A5814B9A2538171000CF4451 /* IpmiNetFnApp.h */,
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A5814BBD2538171000CF4451 /* IpmiNetFnBridge.h */,
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A5814B852538171000CF4451 /* IpmiNetFnChassis.h */,
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A5814B6F2538171000CF4451 /* IpmiNetFnFirmware.h */,
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A5814BB32538171000CF4451 /* IpmiNetFnGroupExtension.h */,
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A5814B9C2538171000CF4451 /* IpmiNetFnSensorEvent.h */,
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A5814B8E2538171000CF4451 /* IpmiNetFnStorage.h */,
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A5814B952538171000CF4451 /* IpmiNetFnTransport.h */,
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A5814B8F2538171000CF4451 /* IScsiBootFirmwareTable.h */,
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A5814BAD2538171000CF4451 /* LegacyBiosMpTable.h */,
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A5814B772538171000CF4451 /* LowPowerIdleTable.h */,
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A5814B812538171000CF4451 /* Mbr.h */,
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A5814B8C2538171000CF4451 /* MemoryMappedConfigurationSpaceAccessTable.h */,
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A5814BAA2538171000CF4451 /* MemoryOverwriteRequestControlLock.h */,
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A5814B752538171000CF4451 /* Nvme.h */,
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A5814BB52538171000CF4451 /* Pci.h */,
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A5814B802538171000CF4451 /* Pci22.h */,
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A5814B992538171000CF4451 /* Pci23.h */,
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A5814BB82538171000CF4451 /* Pci30.h */,
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A5814B942538171000CF4451 /* PciCodeId.h */,
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A5814B9E2538171000CF4451 /* PciExpress21.h */,
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A5814B892538171000CF4451 /* PciExpress30.h */,
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A5814B9F2538171000CF4451 /* PciExpress31.h */,
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A5814B9B2538171000CF4451 /* PciExpress40.h */,
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A5814B882538171000CF4451 /* PeImage.h */,
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A5814BB72538171000CF4451 /* Scsi.h */,
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A5814BA42538171000CF4451 /* Sd.h */,
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A5814B8A2538171000CF4451 /* SdramSpd.h */,
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A5814B722538171000CF4451 /* SdramSpdDdr3.h */,
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A5814B832538171000CF4451 /* SdramSpdDdr4.h */,
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A5814B702538171000CF4451 /* SdramSpdLpDdr.h */,
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A5814B7F2538171000CF4451 /* SerialPortConsoleRedirectionTable.h */,
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A5814BBE2538171000CF4451 /* ServiceProcessorManagementInterfaceTable.h */,
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A5814BA92538171000CF4451 /* SmBios.h */,
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A5814BB02538171000CF4451 /* SmBus.h */,
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A5814BB22538171000CF4451 /* TcgPhysicalPresence.h */,
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A5814BA02538171000CF4451 /* TcgStorageCore.h */,
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A5814B842538171000CF4451 /* TcgStorageOpal.h */,
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A5814BAC2538171000CF4451 /* TcpaAcpi.h */,
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A5814BB42538171000CF4451 /* Tls1.h */,
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A5814B872538171000CF4451 /* Tpm2Acpi.h */,
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A5814BBB2538171000CF4451 /* Tpm12.h */,
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A5814B932538171000CF4451 /* Tpm20.h */,
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A5814B972538171000CF4451 /* TpmPtp.h */,
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A5814BAE2538171000CF4451 /* TpmTis.h */,
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A5814BA72538171000CF4451 /* Udf.h */,
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A5814B7E2538171000CF4451 /* UefiTcgPlatform.h */,
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A5814BA22538171000CF4451 /* Usb.h */,
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A5814B792538171000CF4451 /* WatchdogActionTable.h */,
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A5814BA52538171000CF4451 /* WatchdogResourceTable.h */,
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A5814B742538171000CF4451 /* WindowsSmmSecurityMitigationTable.h */,
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A5814BBA2538171000CF4451 /* WindowsUxCapsule.h */,
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);
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path = IndustryStandard;
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sourceTree = "<group>";
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