mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-11-12 09:54:36 +01:00
exclude newyer theme
Signed-off-by: SergeySlice <sergey.slice@gmail.com>
This commit is contained in:
SergeySlice
parent
1148542685
commit
fd93022f92
@ -1166,7 +1166,7 @@ if [[ -d "${SRCROOT}/CloverV2/EFI/CLOVER/drivers/$DRIVERS_OFF/$DRIVERS_UEFI/Memo
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buildpackage "$packageRefId" "${driverName}" "${PKG_BUILD_DIR}/${driverName}" "${driverDestDir}"
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addChoice --group="MemoryFix64UEFI" --title="$driverName" \
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--start-selected="choicePreviouslySelected('$packageRefId')" \
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--start-visible="true" --start-selected="true" \
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--pkg-refs="$packageRefId" "${driverName}"
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rm -R -f "${PKG_BUILD_DIR}/${driverName}"
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done
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@ -1333,7 +1333,7 @@ fi
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if [[ ${NOEXTRAS} != *"Clover Themes"* ]]; then
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echo "======================== Themes ========================"
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addGroupChoices "Themes"
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local specialThemes=('christmas' 'newyear')
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local specialThemes=('christmas')
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# Using themes section from Azi's/package branch.
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packagesidentity="${clover_package_identity}".themes
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@ -1369,7 +1369,7 @@ if [[ ${NOEXTRAS} != *"Clover Themes"* ]]; then
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for (( i = 0 ; i < ${#specialThemes[@]} ; i++ )); do
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local themeName=${specialThemes[$i]##*/}
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# Don't add christmas and newyear themes if month < 11
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[[ $currentMonth -lt 11 ]] && [[ "$themeName" == christmas || "$themeName" == newyear ]] && continue
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[[ $currentMonth -lt 11 ]] && [[ "$themeName" == christmas ]] && continue
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mkdir -p "${PKG_BUILD_DIR}/${themeName}/Root/"
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rsync -r --exclude=.svn --exclude="*~" "$artwork/${specialThemes[$i]}/" "${PKG_BUILD_DIR}/${themeName}/Root/${themeName}"
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packageRefId=$(getPackageRefId "${packagesidentity}" "${themeName}")
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@ -284,7 +284,7 @@ void GetCPUProperties (void)
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if (gCPUStructure.Vendor == CPU_VENDOR_INTEL) {
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// Determine turbo boost support
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DoCpuid(6, gCPUStructure.CPUID[CPUID_6]);
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gCPUStructure.Turbo = ((gCPUStructure.CPUID[CPUID_6][EAX] & (1 << 1)) != 0);
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gCPUStructure.Turbo = ((gCPUStructure.CPUID[CPUID_6][EAX] & BIT1) != 0);
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DBG(" The CPU%s supported turbo\n", gCPUStructure.Turbo?"":" not");
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//get cores and threads
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switch (gCPUStructure.Model)
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@ -351,6 +351,15 @@ void GetCPUProperties (void)
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break;
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}
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}
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if (gCPUStructure.Vendor == CPU_VENDOR_INTEL) {
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DoCpuid(7, gCPUStructure.CPUID[CPUID_7]);
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if ((gCPUStructure.CPUID[CPUID_7][EBX] & BIT1) != 0) {
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DBG(" IA32_TSC_ADJUST MSR is supported \n");
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msr = AsmReadMsr64(IA32_TSC_ADJUST); //0x3B
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DBG(" value to adjust = %llu\n", msr);
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}
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}
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//workaround for Xeon Harpertown and Yorkfield
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if ((gCPUStructure.Model == CPU_MODEL_PENRYN) &&
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@ -512,7 +521,7 @@ void GetCPUProperties (void)
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//----test C3 patch
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msr = AsmReadMsr64(MSR_PKG_CST_CONFIG_CONTROL); //0xE2
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MsgLog("MSR 0xE2 before patch %08llX\n", msr);
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MsgLog("MSR 0xE2 before patch %08llX\n", msr);
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if (msr & 0x8000) {
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MsgLog("MSR 0xE2 is locked, PM patches will be turned on\n");
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NeedPMfix = TRUE;
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@ -524,13 +533,13 @@ void GetCPUProperties (void)
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// MsgLog("MSR 0xE4 %08X\n", msr);
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//------------
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msr = AsmReadMsr64(MSR_PLATFORM_INFO); //0xCE
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MsgLog("MSR 0xCE %08llX_%08llX\n", (msr>>32), msr & 0xFFFFFFFFull);
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MsgLog("MSR 0xCE %08llX_%08llX\n", (msr>>32), msr & 0xFFFFFFFFull);
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gCPUStructure.MaxRatio = (UINT8)RShiftU64(msr, 8) & 0xff;
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gCPUStructure.MinRatio = (UINT8)MultU64x32(RShiftU64(msr, 40) & 0xff, 10);
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//--- Check if EIST locked
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msr = AsmReadMsr64(MSR_IA32_MISC_ENABLE); //0x1A0
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if (msr & _Bit(20)) {
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MsgLog("MSR 0x1A0 %08llX\n", msr);
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MsgLog("MSR 0x1A0 %08llX\n", msr);
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MsgLog(" EIST is locked and %s\n", (msr & _Bit(16))?"enabled":"disabled");
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}
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@ -545,13 +554,13 @@ void GetCPUProperties (void)
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AsmWriteMsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));
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gBS->Stall(10);
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msr = AsmReadMsr64(MSR_FLEX_RATIO);
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MsgLog("corrected FLEX_RATIO = %llX\n", msr);
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MsgLog("corrected FLEX_RATIO = %llX\n", msr);
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}
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}
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}
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if ((gCPUStructure.CPUID[CPUID_6][ECX] & (1 << 3)) != 0) {
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msr = AsmReadMsr64(IA32_ENERGY_PERF_BIAS); //0x1B0
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MsgLog("MSR 0x1B0 %08llX\n", msr);
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MsgLog("MSR 0x1B0 %08llX\n", msr);
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}
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if(gCPUStructure.MaxRatio) {
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@ -633,8 +642,8 @@ void GetCPUProperties (void)
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gCPUStructure.Turbo4 = (UINT16)(gCPUStructure.MaxRatio + 10);
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}
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DBG("MSR dumps:\n");
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DBG("\t@0x00CD=%llx\n", msr);
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DBG("\t@0x0198=%llx\n", AsmReadMsr64(MSR_IA32_PERF_STATUS));
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DBG("\t@0x00CD=%llx\n", msr);
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DBG("\t@0x0198=%llx\n", AsmReadMsr64(MSR_IA32_PERF_STATUS));
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break;
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default:
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gCPUStructure.TSCFrequency = MultU64x32(gCPUStructure.CurrentSpeed, Mega); //MHz -> Hz
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@ -679,8 +688,6 @@ void GetCPUProperties (void)
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UINT64 busFrequency = 0;
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UINT64 cpuFrequency = 0;
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gCPUStructure.TSCFrequency = MultU64x32(gCPUStructure.CurrentSpeed, Mega); //MHz -> Hz
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DBG("CurrentSpeed: %llu\n", DivU64x32(gCPUStructure.TSCFrequency, Mega));
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@ -1112,7 +1119,7 @@ void GetCPUProperties (void)
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//Slice - why 2:1? Intel spec said 3:4 - QCLK_RATIO at offset 0x50
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// && (Device == 2) && (Function == 1)) {
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&& (Device == 3) && (Function == 4)) {
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DBG("Found QCLK_RATIO at bus 0x%02llX dev=%llX funs=%llX\n", Bus, Device, Function);
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DBG("Found QCLK_RATIO at bus 0x%02llX dev=%llX funs=%llX\n", Bus, Device, Function);
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Status = PciIo->Mem.Read (
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PciIo,
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EfiPciIoWidthUint32,
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@ -182,7 +182,7 @@ const char CPU_STRING_UNKNOWN[] = "Unknown CPU Type";
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#define MSR_IA32_PLATFORM_ID 0x0017
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//#define IA32_APIC_BASE 0x001B /* used also for AMD */
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#define MSR_CORE_THREAD_COUNT 0x0035 /* limited use - not for Penryn or older */
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//#define IA32_TSC_ADJUST 0x003B
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#define IA32_TSC_ADJUST 0x003B
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#define MSR_IA32_BIOS_SIGN_ID 0x008B /* microcode version */
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#define MSR_FSB_FREQ 0x00CD /* limited use - not for i7 */
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/*
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@ -316,11 +316,12 @@ MSR C001006B 0000-0000-0000-0000
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#define CPUID_4 4
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#define CPUID_5 5
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#define CPUID_6 6
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#define CPUID_80 7
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#define CPUID_81 8
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#define CPUID_87 9
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#define CPUID_88 10
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#define CPUID_81E 11
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#define CPUID_7 7
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#define CPUID_80 10
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#define CPUID_81 11
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#define CPUID_87 12
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#define CPUID_88 13
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#define CPUID_81E 14
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#define CPUID_15 15
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#define CPUID_MAX 16
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