152 lines
5.6 KiB
NASM
152 lines
5.6 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; Pen any hot-added CPU in a 16-bit, real mode HLT loop, after it leaves SMM by
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; executing the RSM instruction.
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;
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; Copyright (c) 2020, Red Hat, Inc.
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;
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; The routine implemented here is stored into normal RAM, under 1MB, at the
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; beginning of a page that is allocated as EfiReservedMemoryType. On any
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; hot-added CPU, it is executed after *at least* the first RSM (i.e., after
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; SMBASE relocation).
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;
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; The first execution of this code occurs as follows:
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;
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; - The hot-added CPU is in RESET state.
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;
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; - The ACPI CPU hotplug event handler triggers a broadcast SMI, from the OS.
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;
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; - Existent CPUs (BSP and APs) enter SMM.
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;
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; - The hot-added CPU remains in RESET state, but an SMI is pending for it now.
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; (See "SYSTEM MANAGEMENT INTERRUPT (SMI)" in the Intel SDM.)
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;
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; - In SMM, pre-existent CPUs that are not elected SMM Monarch, keep themselves
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; busy with their wait loops.
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;
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; - From the root MMI handler, the SMM Monarch:
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;
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; - places this routine in the reserved page,
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;
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; - clears the "about to leave SMM" byte in SMRAM,
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;
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; - clears the last byte of the reserved page,
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;
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; - sends an INIT-SIPI-SIPI sequence to the hot-added CPU,
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;
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; - un-gates the default SMI handler by APIC ID.
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;
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; - The startup vector in the SIPI that is sent by the SMM Monarch points to
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; this code; i.e., to the reserved page. (Example: 0x9_F000.)
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;
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; - The SMM Monarch starts polling the "about to leave SMM" byte in SMRAM.
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;
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; - The hot-added CPU boots, and immediately enters SMM due to the pending SMI.
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; It starts executing the default SMI handler.
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;
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; - Importantly, the SMRAM Save State Map captures the following information,
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; when the hot-added CPU enters SMM:
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;
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; - CS selector: assumes the 16 most significant bits of the 20-bit (i.e.,
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; below 1MB) startup vector from the SIPI. (Example: 0x9F00.)
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;
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; - CS attributes: Accessed, Readable, User (S=1), CodeSegment (bit#11),
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; Present.
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;
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; - CS limit: 0xFFFF.
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;
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; - CS base: the CS selector value shifted left by 4 bits. That is, the CS
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; base equals the SIPI startup vector. (Example: 0x9_F000.)
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;
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; - IP: the least significant 4 bits from the SIPI startup vector. Because
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; the routine is page-aligned, these bits are zero (hence IP is zero).
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;
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; - ES, SS, DS, FS, GS selectors: 0.
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;
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; - ES, SS, DS, FS, GS attributes: same as the CS attributes, minus
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; CodeSegment (bit#11).
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;
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; - ES, SS, DS, FS, GS limits: 0xFFFF.
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;
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; - ES, SS, DS, FS, GS bases: 0.
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;
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; - The hot-added CPU sets its new SMBASE value in the SMRAM Save State Map.
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;
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; - The hot-added CPU sets the "about to leave SMM" byte in SMRAM, then
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; executes the RSM instruction immediately after, leaving SMM.
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;
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; - The SMM Monarch notices that the "about to leave SMM" byte in SMRAM has
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; been set, and starts polling the last byte in the reserved page.
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;
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; - The hot-added CPU jumps ("returns") to the code below (in the reserved
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; page), according to the register state listed in the SMRAM Save State Map.
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;
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; - The hot-added CPU sets the last byte of the reserved page, then halts
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; itself.
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;
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; - The SMM Monarch notices that the hot-added CPU is done with SMBASE
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; relocation.
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;
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; Note that, if the OS is malicious and sends INIT-SIPI-SIPI to the hot-added
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; CPU before allowing the ACPI CPU hotplug event handler to trigger a broadcast
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; SMI, then said broadcast SMI will yank the hot-added CPU directly into SMM,
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; without becoming pending for it (as the hot-added CPU is no longer in RESET
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; state). This is OK, because:
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;
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; - The default SMI handler copes with this, as it is gated by APIC ID. The
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; hot-added CPU won't start the actual SMBASE relocation until the SMM
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; Monarch lets it.
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;
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; - The INIT-SIPI-SIPI sequence that the SMM Monarch sends to the hot-added CPU
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; will be ignored in this sate (it won't even be latched). See "SMI HANDLER
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; EXECUTION ENVIRONMENT" in the Intel SDM: "INIT operations are inhibited
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; when the processor enters SMM".
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;
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; - When the hot-added CPU (e.g., CPU#1) executes the RSM (having relocated
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; SMBASE), it returns to the OS. The OS can use CPU#1 to attack the last byte
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; of the reserved page, while another CPU (e.g., CPU#2) is relocating SMBASE,
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; in order to trick the SMM Monarch (e.g., CPU#0) to open the APIC ID gate
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; for yet another CPU (e.g., CPU#3). However, the SMM Monarch won't look at
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; the last byte of the reserved page, until CPU#2 sets the "about to leave
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; SMM" byte in SMRAM. This leaves a very small window (just one instruction's
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; worth before the RSM) for CPU#3 to "catch up" with CPU#2, and overwrite
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; CPU#2's SMBASE with its own.
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;
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; In other words, we do not / need not prevent a malicious OS from booting the
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; hot-added CPU early; instead we provide benign OSes with a pen for hot-added
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; CPUs.
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;------------------------------------------------------------------------------
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SECTION .data
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BITS 16
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GLOBAL ASM_PFX (mPostSmmPen) ; UINT8[]
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GLOBAL ASM_PFX (mPostSmmPenSize) ; UINT16
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ASM_PFX (mPostSmmPen):
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;
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; Point DS at the same reserved page.
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;
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mov ax, cs
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mov ds, ax
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;
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; Inform the SMM Monarch that we're done with SMBASE relocation, by setting
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; the last byte in the reserved page.
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;
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mov byte [ds : word 0xFFF], 1
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;
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; Halt now, until we get woken by another SMI, or (more likely) the OS
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; reboots us with another INIT-SIPI-SIPI.
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;
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HltLoop:
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cli
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hlt
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jmp HltLoop
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ASM_PFX (mPostSmmPenSize):
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dw $ - ASM_PFX (mPostSmmPen)
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