191 lines
6.5 KiB
C
191 lines
6.5 KiB
C
/*
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* NVidia injector
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*
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* Copyright (C) 2009 Jasmin Fazlic, iNDi
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*
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* NVidia injector modified by Fabio (ErmaC) on May 2012,
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* for allow the cosmetics injection also based on SubVendorID and SubDeviceID.
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*
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* NVidia injector is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* NVidia driver and injector is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
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*
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* Alternatively you can choose to comply with APSL
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*
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* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
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*
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*
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* Copyright 2005-2006 Erik Waling
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* Copyright 2006 Stephane Marchesin
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* Copyright 2007-2009 Stuart Bennett
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __LIBSAIO_NVIDIA_H
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#define __LIBSAIO_NVIDIA_H
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//#include "device_inject.h"
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//#include "card_vlist.h"
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#include "../include/Pci.h"
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extern CHAR8* gDeviceProperties;
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//XBool setup_nvidia_devprop(pci_dt_t *nvda_dev);
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typedef struct nvidia_pci_info_t
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{
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UINT32 device; // VendorID + DeviceID
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CONST CHAR8 *name_model;
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} nvidia_pci_info_t;
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typedef struct nvidia_card_info_t
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{
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UINT32 device; // VendorID + DeviceID
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UINT32 subdev; // SubdeviceID + SubvendorID
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CONST CHAR8 *name_model;
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UINT8 *custom_NVCAP;
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} nvidia_card_info_t;
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#define DCB_MAX_NUM_ENTRIES 16
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#define DCB_MAX_NUM_I2C_ENTRIES 16
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#define DCB_LOC_ON_CHIP 0
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struct bios {
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UINT16 signature; /* 0x55AA */
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UINT8 size; /* Size in multiples of 512 */
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};
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#define NVIDIA_ROM_SIZE 0x20000
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#define PATCH_ROM_SUCCESS 1
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#define PATCH_ROM_SUCCESS_HAS_LVDS 2
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#define PATCH_ROM_FAILED 0
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#define MAX_NUM_DCB_ENTRIES 16
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#define TYPE_GROUPED 0xff
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#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(UINT8) )
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#define NVPM_LEN ( sizeof(default_NVPM) / sizeof(UINT8) )
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#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(UINT8) )
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#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(UINT8) )
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#define NV_SUB_IDS 0x00000000
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#define NV_PMC_OFFSET 0x000000
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#define NV_PMC_SIZE 0x2ffff
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#define NV_PDISPLAY_OFFSET 0x610000
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#define NV_PDISPLAY_SIZE 0x10000
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#define NV_PROM_OFFSET 0x300000
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#define NV_PROM_SIZE 0x0001ffff
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#define NV_PRAMIN_OFFSET 0x00700000
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#define NV_PRAMIN_SIZE 0x00100000
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#define NV04_PFB_FIFO_DATA 0x0010020c
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#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000
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#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
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#define NVC0_MEM_CTRLR_COUNT 0x00121c74
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#define NVC0_MEM_CTRLR_RAM_AMOUNT 0x0010f20c
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#define NV_PBUS_PCI_NV_20 0x00001850
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#define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0)
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#define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0)
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#define NV_ARCH_03 0x03
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#define NV_ARCH_04 0x04
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#define NV_ARCH_10 0x10
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#define NV_ARCH_20 0x20
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#define NV_ARCH_30 0x30
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#define NV_ARCH_40 0x40
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#define NV_ARCH_TESLA 0x50
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#define NV_ARCH_FERMI1 0xC0 // Fermi
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#define NV_ARCH_FERMI2 0xD0 // Fermi
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#define NV_ARCH_KEPLER1 0xE0 // Kepler - GT 6XX/GTX 6XX/GTX 6XX Ti
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#define NV_ARCH_KEPLER2 0xF0 // Kepler - Tesla K20X/GTX 780/GTX TITAN/TITAN LE
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#define NV_ARCH_KEPLER3 0x100 // Kepler - GT 630.Rev2/635/640.Rev2/710/720/730/740
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#define NV_ARCH_MAXWELL1 0x110 // Maxwell - GTX 745/750/750 Ti
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#define NV_ARCH_MAXWELL2 0x120 // Maxwell - GTX 9XX/9XX Ti/TITAN X
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#define NV_ARCH_PASCAL 0x130 // Pascal - GTX 10XX/10XX Ti/TITAN X/Xp
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#define NV_ARCH_VOLTA 0x140 // Volta - Titan V/Quadro GV100
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#define NV_ARCH_TURING 0x160 // Turing - GTX 16xx/RTX 20xx
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#define CHIPSET_NV03 0x0010
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#define CHIPSET_NV04 0x0020
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#define CHIPSET_NV10 0x0100
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#define CHIPSET_NV11 0x0110
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#define CHIPSET_NV15 0x0150
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#define CHIPSET_NV17 0x0170
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#define CHIPSET_NV18 0x0180
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#define CHIPSET_NFORCE 0x01A0
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#define CHIPSET_NFORCE2 0x01F0
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#define CHIPSET_NV20 0x0200
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#define CHIPSET_NV25 0x0250
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#define CHIPSET_NV28 0x0280
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#define CHIPSET_NV30 0x0300
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#define CHIPSET_NV31 0x0310
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#define CHIPSET_NV34 0x0320
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#define CHIPSET_NV35 0x0330
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#define CHIPSET_NV36 0x0340
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#define CHIPSET_NV40 0x0040
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#define CHIPSET_NV41 0x00C0
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#define CHIPSET_NV43 0x0140
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#define CHIPSET_NV44 0x0160
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#define CHIPSET_NV44A 0x0220
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#define CHIPSET_NV45 0x0210
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#define CHIPSET_NV50 0x0190
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#define CHIPSET_NV84 0x0400
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#define CHIPSET_MISC_BRIDGED 0x00F0
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#define CHIPSET_G70 0x0090
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#define CHIPSET_G71 0x0290
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#define CHIPSET_G72 0x01D0
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#define CHIPSET_G73 0x0390
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// integrated GeForces (6100, 6150)
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#define CHIPSET_C51 0x0240
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// variant of C51, seems based on a G70 design
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#define CHIPSET_C512 0x03D0
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#define CHIPSET_G73_BRIDGED 0x02E0
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#ifndef DONT_DEFINE_GLOBALS
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extern UINT8 default_NVCAP[];
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#endif
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extern const UINT8 default_NVPM[];
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extern const UINT8 default_dcfg_0[];
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extern const UINT8 default_dcfg_1[];
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XBool
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setup_nvidia_devprop (
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pci_dt_t *nvda_dev
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);
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CONST CHAR8* get_nvidia_model(UINT32 device_id, UINT32 subsys_id);
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#endif /* !__LIBSAIO_NVIDIA_H */
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