mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-11-29 12:35:53 +01:00
182 lines
7.6 KiB
C
182 lines
7.6 KiB
C
/** @file
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Virtual Memory Management Services to set or clear the memory encryption bit
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Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
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**/
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#ifndef TDX_VIRTUAL_MEMORY_
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#define TDX_VIRTUAL_MEMORY_
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/CacheMaintenanceLib.h>
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#include <Library/DebugLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Uefi.h>
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#define SYS_CODE64_SEL 0x38
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#pragma pack(1)
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//
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// Page-Map Level-4 Offset (PML4) and
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// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
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//
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typedef union {
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struct {
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UINT64 Present : 1; // 0 = Not present in memory,
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// 1 = Present in memory
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UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough : 1; // 0 = Write-Back caching,
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// 1 = Write-Through caching
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UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed : 1; // 0 = Not accessed,
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// 1 = Accessed (set by CPU)
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UINT64 Reserved : 1; // Reserved
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UINT64 MustBeZero : 2; // Must Be Zero
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UINT64 Available : 3; // Available for use by system software
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UINT64 PageTableBaseAddress : 40; // Page Table Base Address
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UINT64 AvabilableHigh : 11; // Available for use by system software
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UINT64 Nx : 1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} PAGE_MAP_AND_DIRECTORY_POINTER;
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//
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// Page Table Entry 4KB
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//
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typedef union {
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struct {
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UINT64 Present : 1; // 0 = Not present in memory,
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// 1 = Present in memory
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UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough : 1; // 0 = Write-Back caching,
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// 1 = Write-Through caching
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UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed : 1; // 0 = Not accessed,
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// 1 = Accessed (set by CPU)
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UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by
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// processor on access to page
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UINT64 PAT : 1; //
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UINT64 Global : 1; // 0 = Not global page, 1 = global page
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// TLB not cleared on CR3 write
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UINT64 Available : 3; // Available for use by system software
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UINT64 PageTableBaseAddress : 40; // Page Table Base Address
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UINT64 AvabilableHigh : 11; // Available for use by system software
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UINT64 Nx : 1; // 0 = Execute Code,
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// 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_4K_ENTRY;
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//
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// Page Table Entry 2MB
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//
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typedef union {
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struct {
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UINT64 Present : 1; // 0 = Not present in memory,
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// 1 = Present in memory
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UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough : 1; // 0 = Write-Back caching,
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// 1=Write-Through caching
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UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed : 1; // 0 = Not accessed,
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// 1 = Accessed (set by CPU)
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UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by
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// processor on access to page
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UINT64 MustBe1 : 1; // Must be 1
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UINT64 Global : 1; // 0 = Not global page, 1 = global page
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// TLB not cleared on CR3 write
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UINT64 Available : 3; // Available for use by system software
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UINT64 PAT : 1; //
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UINT64 MustBeZero : 8; // Must be zero;
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UINT64 PageTableBaseAddress : 31; // Page Table Base Address
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UINT64 AvabilableHigh : 11; // Available for use by system software
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UINT64 Nx : 1; // 0 = Execute Code,
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// 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_ENTRY;
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//
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// Page Table Entry 1GB
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//
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typedef union {
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struct {
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UINT64 Present : 1; // 0 = Not present in memory,
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// 1 = Present in memory
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UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough : 1; // 0 = Write-Back caching,
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// 1 = Write-Through caching
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UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed : 1; // 0 = Not accessed,
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// 1 = Accessed (set by CPU)
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UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by
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// processor on access to page
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UINT64 MustBe1 : 1; // Must be 1
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UINT64 Global : 1; // 0 = Not global page, 1 = global page
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// TLB not cleared on CR3 write
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UINT64 Available : 3; // Available for use by system software
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UINT64 PAT : 1; //
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UINT64 MustBeZero : 17; // Must be zero;
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UINT64 PageTableBaseAddress : 22; // Page Table Base Address
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UINT64 AvabilableHigh : 11; // Available for use by system software
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UINT64 Nx : 1; // 0 = Execute Code,
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// 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_1G_ENTRY;
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#pragma pack()
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#define IA32_PG_P BIT0
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#define IA32_PG_RW BIT1
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#define IA32_PG_PS BIT7
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#define PAGING_PAE_INDEX_MASK 0x1FF
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#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
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#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
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#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
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#define PAGING_L1_ADDRESS_SHIFT 12
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#define PAGING_L2_ADDRESS_SHIFT 21
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#define PAGING_L3_ADDRESS_SHIFT 30
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#define PAGING_L4_ADDRESS_SHIFT 39
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#define PAGING_PML4E_NUMBER 4
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#define PAGETABLE_ENTRY_MASK ((1UL << 9) - 1)
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#define PML4_OFFSET(x) ( (x >> 39) & PAGETABLE_ENTRY_MASK)
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#define PDP_OFFSET(x) ( (x >> 30) & PAGETABLE_ENTRY_MASK)
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#define PDE_OFFSET(x) ( (x >> 21) & PAGETABLE_ENTRY_MASK)
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#define PTE_OFFSET(x) ( (x >> 12) & PAGETABLE_ENTRY_MASK)
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#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
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#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB
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#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB
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#define PAGE_TABLE_POOL_UNIT_PAGES \
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EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)
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#define PAGE_TABLE_POOL_ALIGN_MASK \
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(~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))
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typedef struct {
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VOID *NextPool;
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UINTN Offset;
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UINTN FreePages;
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} PAGE_TABLE_POOL;
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#endif
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