mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-11-15 10:15:32 +01:00
695 lines
13 KiB
C
695 lines
13 KiB
C
/*++
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Copyright (c) 2006 - 2010 Intel Corporation. All rights reserved
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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VideoModes.c
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Abstract:
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Intel Video Controller Driver
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Revision History
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--*/
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#include "Gop.h"
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//
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// MODE 0 - Turns off display controller.
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//
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MODE_FORMAT DS_0_0_0_0[] = {
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{
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DPLLADivisor,
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0x00000000,
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FALSE
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},
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{
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DPLLAControl,
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0x00000000,
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FALSE
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},
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{
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HTOTAL_A,
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0x00000000,
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FALSE
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},
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{
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HBLANK_A,
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0x00000000,
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FALSE
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},
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{
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HSYNC_A,
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0x00000000,
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FALSE
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},
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{
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VTOTAL_A,
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0x00000000,
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FALSE
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},
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{
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VBLANK_A,
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0x00000000,
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FALSE
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},
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{
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VSYNC_A,
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0x00000000,
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FALSE
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},
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{
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PIPESRC_A,
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0x00000000,
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FALSE
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},
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{
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BDRCOLRPTRN_A,
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0x00000000,
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FALSE
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},
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{
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ColorChannel_Red_A,
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0x00000000,
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FALSE
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},
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{
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ColorChannel_Grn_A,
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0x00000000,
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FALSE
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},
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{
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ColorChannel_Blue_A,
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0x00000000,
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FALSE
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},
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{
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PIPEASTAT,
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0x00000000,
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FALSE
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},
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{
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DSPASTRIDE,
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0x00000000,
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FALSE
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},
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{
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ADPA,
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0x00000000,
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FALSE
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},
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};
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//
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// Make sure there are NUM_DS_ENTRIES in the structure
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//
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//C_ASSERT(sizeof (DS_0_0_0_0) == NUM_DS_ENTRIES * sizeof (MODE_FORMAT));
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//
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// 640x480 Modes 60Hz
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// MODE 640x480x32x60
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//
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MODE_FORMAT DS_640_480_32_60[] = {
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{
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HTOTAL_A,
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0x031f027f,
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FALSE
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},
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{
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HBLANK_A,
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0x03170287,
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FALSE
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},
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{
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HSYNC_A,
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0x02ef028f,
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FALSE
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},
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{
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VTOTAL_A,
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0x020c01df,
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FALSE
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},
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{
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VBLANK_A,
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0x020401e7,
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FALSE
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},
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{
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VSYNC_A,
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0x01eb01e9,
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FALSE
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},
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{
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PIPESRC_A,
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0x027f01df,
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FALSE
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},
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{
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BDRCOLRPTRN_A,
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0x00000000,
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FALSE
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},
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{
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ColorChannel_Red_A,
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0x00000000,
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FALSE
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},
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{
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ColorChannel_Grn_A,
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0x00000000,
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FALSE
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},
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{
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ColorChannel_Blue_A,
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0x00000000,
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FALSE
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},
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{
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DPLLADivisor,
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0x00200067,
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FALSE
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},
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{
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DPLLAControl,
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0x94400000,
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FALSE
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},
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{
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PIPEASTAT,
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0x00000203,
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FALSE
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},
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{
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DSPASTRIDE,
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0x00000a00,
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FALSE
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},
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{
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ADPA,
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0x80000000,
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FALSE
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},
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};
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//C_ASSERT(sizeof (DS_640_480_32_60) == NUM_DS_ENTRIES * sizeof (MODE_FORMAT));
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//
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// 800x600 Modes 60Hz
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// MODE 800x600x32x60
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//
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MODE_FORMAT DS_800_600_32_60[] = {
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{
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HTOTAL_A,
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0x041f031f,
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FALSE
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},
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{
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HBLANK_A,
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0x041f031f,
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FALSE
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},
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{
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HSYNC_A,
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0x03c70347,
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FALSE
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},
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{
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VTOTAL_A,
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0x02730257,
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FALSE
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},
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{
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VBLANK_A,
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0x02730257,
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FALSE
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},
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{
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VSYNC_A,
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0x025c0258,
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FALSE
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},
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{
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PIPESRC_A,
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0x031f0257,
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FALSE
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},
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{
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BDRCOLRPTRN_A,
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0x00000000,
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FALSE
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},
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{
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ColorChannel_Red_A,
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0x00000000,
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FALSE
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},
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{
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ColorChannel_Grn_A,
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0x00000000,
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FALSE
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},
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{
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ColorChannel_Blue_A,
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0x00000000,
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FALSE
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},
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{
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DPLLADivisor,
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0x0020007B,
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FALSE
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},
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{
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DPLLAControl,
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0x94100000,
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FALSE
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},
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{
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PIPEASTAT,
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0x00000203,
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FALSE
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},
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{
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DSPASTRIDE,
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0x00000c80,
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FALSE
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},
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{
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ADPA,
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0x80000018,
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FALSE
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},
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};
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//C_ASSERT(sizeof (DS_800_600_32_60) == NUM_DS_ENTRIES * sizeof (MODE_FORMAT));
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//
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// 1024x768 Modes 60Hz
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// MODE 1024x768x32x60
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//
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MODE_FORMAT DS_1024_768_32_60[] = {
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{
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HTOTAL_A,
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0x053F03FF,
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FALSE
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},
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{
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HBLANK_A,
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0x053F03FF,
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FALSE
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},
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{
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HSYNC_A,
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0x049F0417,
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FALSE
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},
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{
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VTOTAL_A,
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0x032502FF,
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FALSE
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},
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{
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VBLANK_A,
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0x032502FF,
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FALSE
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},
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{
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VSYNC_A,
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0x03080302,
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FALSE
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},
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{
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PIPESRC_A,
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0x03FF02FF,
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FALSE
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},
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{
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BDRCOLRPTRN_A,
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0x00000000,
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FALSE
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},
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{
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ColorChannel_Red_A,
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0x00000000,
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FALSE
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},
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{
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ColorChannel_Grn_A,
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0x00000000,
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FALSE
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},
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{
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ColorChannel_Blue_A,
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0x00000000,
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FALSE
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},
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{
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DPLLADivisor,
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0x0010006A,
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FALSE
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},
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{
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DPLLAControl,
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0x94040000,
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FALSE
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},
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{
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PIPEASTAT,
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0x00000203,
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FALSE
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},
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{
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DSPASTRIDE,
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0x00001000,
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FALSE
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},
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{
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ADPA,
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0x80000000,
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FALSE
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},
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};
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//C_ASSERT(sizeof (DS_1024_768_32_60) == NUM_DS_ENTRIES * sizeof (MODE_FORMAT));
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//
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// Generic shutdown controller; this is used to turn off the controller
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// before changing the mode. These must be done in this order. The order
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// in which these entries appear in the table is the order in which the
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// values are written to the h/w.
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//
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MODE_FORMAT mDISPLAY_SHUTDOWN[] = {
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{
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DSPACNTR,
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0x00000000,
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FALSE
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},
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//
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// Turn off display plane A
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//
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{
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ADPA,
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0x00000000,
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FALSE
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},
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//
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// Turn off port (disable sync signals)
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//
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{
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PIPEACONF,
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0x00000000,
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FALSE
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},
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//
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// Shutdown pipe
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//
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{
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VGACNTRL,
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0x00000000,
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FALSE
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},
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//
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// Turn off VGA display register
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//
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{
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DPLLAControl,
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0x00000000,
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FALSE
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},
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//
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// Turn off PLL
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//
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{
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PGTBL_CTL,
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0x00000000,
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FALSE
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},
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//
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// { PGTBL_CTL, 0x00000000, TRUE },
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//
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};
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UINT16 mNUM_SHUTDOWN_ENTRIES = sizeof (mDISPLAY_SHUTDOWN) / sizeof (mDISPLAY_SHUTDOWN[0]);
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//
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// Generic start-up controller; This is used to turn on the controller
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// before changing the mode. These must be done in this order. The order
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// in which these entries appear in the table is the order in which the
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// values are written to the h/w.
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//
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MODE_FORMAT mDISPLAY_STARTUP[] = {
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{
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PIPEACONF,
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0x80000000,
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FALSE
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},
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//
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// Turn on the display pipe
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//
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{
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VGACNTRL,
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0x80100000,
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FALSE
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},
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//
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// 8-bit DAC, disable VGA
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//
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{
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DSPACNTR,
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0x98000000,
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FALSE
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},
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//
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// Enable plane A & set x:8:8:8 format
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//
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{
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DSPABASE,
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0x00000000,
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FALSE
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},
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//
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// Display starts at base address of GTT
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//
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};
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UINT16 mNUM_STARTUP_ENTRIES = sizeof (mDISPLAY_STARTUP) / sizeof (mDISPLAY_STARTUP[0]);
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MODE_FORMAT LVDS_SHUTDOWN[] = {
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{PP_CONTROL , 0xabcd0000, FALSE},
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{PIPEBSTAT , 0 , FALSE},
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{BLC_PWM_CTL , 0 , FALSE},
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{PFIT_CONTROL , 0 , FALSE},
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{LVDSPC , 0 , FALSE},
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{DSPBCNTR , 0 , TRUE},
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{DSPBLINOFFSET , 0 , TRUE},
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{DSPBSTRIDE , 0 , TRUE},
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{DSPBSIZE , 0 , TRUE},
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{VGACNTRL , 0 , FALSE},
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{PIPEBCONF , 0 , TRUE},
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{CRCCtrlColorBB, 0 , FALSE},
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{CRCCtrlColorBG, 0 , FALSE},
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{CRCCtrlColorBR, 0 , FALSE},
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{BCLRPAT_B , 0 , FALSE},
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{PIPEBSRC , 0 , FALSE},
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{DPLLB_CTRL , 0 , FALSE},
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{FPB0 , 0 , FALSE},
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{VSYNC_B , 0 , FALSE},
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{VBLANK_B , 0 , FALSE},
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{VTOTAL_B , 0 , FALSE},
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{HSYNC_B , 0 , FALSE},
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{HBLANK_B , 0 , FALSE},
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{HTOTAL_B , 0 , FALSE},
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{PP_DIVISOR , 0 , FALSE},
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{PP_OFF_DELAYS , 0 , FALSE},
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{PP_ON_DELAYS , 0 , TRUE},
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{PP_CONTROL , 0 , FALSE},
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{0,0,0}
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};
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MODE_FORMAT LVDS_MODE_DATA_640_480[] = {
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{PP_CONTROL , 0xabcd0000, FALSE},
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{PP_ON_DELAYS , 0x25807d0 , TRUE},
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{PP_OFF_DELAYS , 0x1f407d0 , FALSE},
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{PP_DIVISOR , 0x209d05 , FALSE},
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{HTOTAL_B , 0x4af03ff , FALSE},
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{HBLANK_B , 0x4af03ff , FALSE},
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{HSYNC_B , 0x44f042f , FALSE},
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{VTOTAL_B , 0x26e0257 , FALSE},
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{VBLANK_B , 0x26e0257 , FALSE},
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{VSYNC_B , 0x260025a , FALSE},
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{FPB0 , 0x100067 , FALSE},
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{DPLLB_CTRL , 0x98040000, FALSE},
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{PIPEBSRC , 0x27f01df , FALSE},
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{BCLRPAT_B , 0x0 , FALSE},
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{CRCCtrlColorBR, 0x0 , FALSE},
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{CRCCtrlColorBG, 0x0 , FALSE},
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{CRCCtrlColorBB, 0x0 , FALSE},
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{PIPEBCONF , 0x80000000, TRUE },
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{VGACNTRL , 0xa2c4008e, FALSE},
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{DSPBSIZE , 0x1df027f , TRUE },
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{DSPBSTRIDE , 0xa00 , TRUE },
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{DSPBLINOFFSET , 0x0 , TRUE },
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{DSPBCNTR , 0x99000000, TRUE },
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{LVDSPC , 0xc0300300, FALSE},
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{PFIT_CONTROL , 0x80002668, FALSE},
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{BLC_PWM_CTL , 0x65ed65ed, FALSE},
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{PIPEBSTAT , 0x00020202, FALSE},
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{PP_CONTROL , 0x00000001, FALSE},
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{0,0,0}
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};
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MODE_FORMAT LVDS_MODE_DATA_800_600[] = {
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{PP_CONTROL , 0xabcd0000, FALSE},
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{PP_ON_DELAYS , 0x25807d0 , TRUE },
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{PP_OFF_DELAYS , 0x1f407d0 , FALSE},
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{PP_DIVISOR , 0x209d05 , FALSE},
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{HTOTAL_B , 0x4af03ff , FALSE},
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{HBLANK_B , 0x4af03ff , FALSE},
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{HSYNC_B , 0x44f042f , FALSE},
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{VTOTAL_B , 0x26e0257 , FALSE},
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{VBLANK_B , 0x26e0257 , FALSE},
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{VSYNC_B , 0x260025a , FALSE},
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{FPB0 , 0x100067 , FALSE},
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{DPLLB_CTRL , 0x98040000, FALSE},
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{PIPEBSRC , 0x31f0257 , FALSE},
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{BCLRPAT_B , 0x0 , FALSE},
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{CRCCtrlColorBR, 0x0 , FALSE},
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{CRCCtrlColorBG, 0x0 , FALSE},
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{CRCCtrlColorBB, 0x0 , FALSE},
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{PIPEBCONF , 0x80000000, TRUE },
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{VGACNTRL , 0xa2c4008e, FALSE},
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{DSPBSIZE , 0x257031f , TRUE },
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{DSPBSTRIDE , 0xc80 , TRUE },
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{DSPBLINOFFSET , 0x0 , TRUE },
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{DSPBCNTR , 0x99000000, TRUE },
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{LVDSPC , 0xc0300300, FALSE},
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{PFIT_CONTROL , 0x80002668, FALSE},
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{BLC_PWM_CTL , 0x65ed65ed, FALSE},
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{PIPEBSTAT , 0x00020202, FALSE},
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{PP_CONTROL , 0x00000001, FALSE},
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{0,0,0}
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};
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MODE_FORMAT LVDS_MODE_DATA_1024_768[] = {
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{PP_CONTROL , 0xabcd0000, FALSE},
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{PP_ON_DELAYS , 0x25807d0 , TRUE},
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{PP_OFF_DELAYS , 0x1f407d0 , FALSE},
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{PP_DIVISOR , 0x209d05 , FALSE},
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{HTOTAL_B , 0x4af03ff , FALSE},
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{HBLANK_B , 0x4af03ff , FALSE},
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{HSYNC_B , 0x44f042f , FALSE},
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{VTOTAL_B , 0x26e0257 , FALSE},
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{VBLANK_B , 0x26e0257 , FALSE},
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{VSYNC_B , 0x260025a , FALSE},
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{FPB0 , 0x100067 , FALSE},
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{DPLLB_CTRL , 0x98040000, FALSE},
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{PIPEBSRC , 0x3ff02fF , FALSE},
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{BCLRPAT_B , 0x0 , FALSE},
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{CRCCtrlColorBR, 0x0 , FALSE},
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{CRCCtrlColorBG, 0x0 , FALSE},
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{CRCCtrlColorBB, 0x0 , FALSE},
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{PIPEBCONF , 0x80000000, TRUE },
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{VGACNTRL , 0xa2c4008e, FALSE},
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{DSPBSIZE , 0x25f03ff , TRUE },
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{DSPBSTRIDE , 0x1000 , TRUE },
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{DSPBLINOFFSET , 0x0 , TRUE },
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{DSPBCNTR , 0x99000000, TRUE },
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{LVDSPC , 0xc0300300, FALSE},
|
|
{PFIT_CONTROL , 0x80002668, FALSE},
|
|
{BLC_PWM_CTL , 0x65ed65ed, FALSE},
|
|
{PIPEBSTAT , 0x00020202, FALSE},
|
|
{PP_CONTROL , 0x00000001, FALSE},
|
|
{0,0,0}
|
|
|
|
};
|
|
|
|
MODE_FORMAT LVDS_MODE_DATA_0_0[] = {
|
|
{PP_CONTROL , 0xabcd0000, FALSE},
|
|
{PP_ON_DELAYS , 0, FALSE},
|
|
{PP_OFF_DELAYS , 0, FALSE},
|
|
{PP_DIVISOR , 0, FALSE},
|
|
{HTOTAL_B , 0, FALSE},
|
|
{HBLANK_B , 0, FALSE},
|
|
{HSYNC_B , 0, FALSE},
|
|
{VTOTAL_B , 0, FALSE},
|
|
{VBLANK_B , 0, FALSE},
|
|
{VSYNC_B , 0, FALSE},
|
|
{FPB0 , 0, FALSE},
|
|
{DPLLB_CTRL , 0, FALSE},
|
|
{PIPEBSRC , 0, FALSE},
|
|
{BCLRPAT_B , 0, FALSE},
|
|
{CRCCtrlColorBR, 0, FALSE},
|
|
{CRCCtrlColorBG, 0, FALSE},
|
|
{CRCCtrlColorBB, 0, FALSE},
|
|
{PIPEBCONF , 0, FALSE},
|
|
{VGACNTRL , 0, FALSE},
|
|
{DSPBSIZE , 0, FALSE},
|
|
{DSPBSTRIDE , 0, FALSE},
|
|
{DSPBLINOFFSET , 0, FALSE},
|
|
{DSPBCNTR , 0, FALSE},
|
|
{LVDSPC , 0, FALSE},
|
|
{PFIT_CONTROL , 0, FALSE},
|
|
{BLC_PWM_CTL , 0, FALSE},
|
|
{PIPEBSTAT , 0, FALSE},
|
|
{PP_CONTROL , 0, FALSE},
|
|
{0,0,0}
|
|
|
|
};
|
|
|
|
INTEL_VIDEO_MODES mVideoModes[] = {
|
|
{
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
&DS_0_0_0_0[0],
|
|
&LVDS_MODE_DATA_0_0[0]
|
|
},
|
|
//
|
|
// Mode #0: turns off monitor
|
|
//
|
|
{
|
|
640,
|
|
480,
|
|
32,
|
|
60,
|
|
&DS_640_480_32_60[0],
|
|
&LVDS_MODE_DATA_640_480[0]
|
|
},
|
|
//
|
|
// Mode #1: sets 640x480x32x60
|
|
//
|
|
{
|
|
800,
|
|
600,
|
|
32,
|
|
60,
|
|
&DS_800_600_32_60[0],
|
|
&LVDS_MODE_DATA_800_600[0]
|
|
},
|
|
//
|
|
// Mode #2: sets 800x600x32x60
|
|
//
|
|
{
|
|
1024,
|
|
768,
|
|
32,
|
|
60,
|
|
&DS_1024_768_32_60[0],
|
|
&LVDS_MODE_DATA_1024_768[0]
|
|
},
|
|
//
|
|
// Mode #3: sets 1024x768x32x60
|
|
//
|
|
};
|