mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-11-27 12:15:19 +01:00
606 lines
11 KiB
C
606 lines
11 KiB
C
/** @file
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Copyright (C) 2016 - 2017, The HermitCrabs Lab. All rights reserved.
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All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Uefi.h>
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#include <IndustryStandard/Pci.h>
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#include <Protocol/PciIo.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#define XHC_HCCPARAMS_OFFSET 0x10
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#define XHC_NEXT_CAPABILITY_MASK 0xFF00
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#define XHC_CAPABILITY_ID_MASK 0xFF
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#define XHC_USBCMD_OFFSET 0x0 ///< USB Command Register Offset
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#define XHC_USBSTS_OFFSET 0x4 ///< USB Status Register Offset
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#define XHC_POLL_DELAY 1000
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#define EHC_BAR_INDEX 0x0
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#define EHC_HCCPARAMS_OFFSET 0x8
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#define EHC_USBCMD_OFFSET 0x0 ///< USB Command Register Offset
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#define EHC_USBSTS_OFFSET 0x4 ///< USB Status Register Offset
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#define EHC_USBINT_OFFSET 0x8 ///< USB Interrupt Enable Register
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/**
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Release XHCI USB controllers ownership.
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@param[in] PciIo PCI I/O protocol for the device.
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@retval EFI_NOT_FOUND No XHCI controllers had ownership incorrectly set.
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@retval EFI_SUCCESS Corrected XHCI controllers ownership to OS.
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**/
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STATIC
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EFI_STATUS
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XhciReleaseOwnership (
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IN EFI_PCI_IO_PROTOCOL *PciIo
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)
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{
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EFI_STATUS Status;
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UINT32 HcCapParams;
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UINT32 ExtendCap;
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UINT32 Value;
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INT32 TimeOut;
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//
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// XHCI controller, then disable legacy support, if enabled.
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//
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Status = PciIo->Mem.Read (
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PciIo,
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EfiPciIoWidthUint32,
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XHC_USBCMD_OFFSET,
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XHC_HCCPARAMS_OFFSET,
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1,
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&HcCapParams
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);
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ExtendCap = EFI_ERROR(Status) ? 0 : ((HcCapParams >> 14U) & 0x3FFFCU);
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while (ExtendCap) {
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Status = PciIo->Mem.Read (
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PciIo,
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EfiPciIoWidthUint32,
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XHC_USBCMD_OFFSET,
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ExtendCap,
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1,
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&Value
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);
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if (EFI_ERROR(Status)) {
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break;
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}
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if ((Value & XHC_CAPABILITY_ID_MASK) == 1) {
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//
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// Do nothing if BIOS ownership is cleared.
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//
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if (!(Value & BIT16)) {
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break;
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}
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Value |= BIT24;
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PciIo->Mem.Write (
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PciIo,
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EfiPciIoWidthUint32,
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XHC_USBCMD_OFFSET,
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ExtendCap,
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1,
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&Value
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);
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TimeOut = 40;
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while (TimeOut--) {
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gBS->Stall (500);
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Status = PciIo->Mem.Read (
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PciIo,
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EfiPciIoWidthUint32,
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XHC_USBCMD_OFFSET,
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ExtendCap,
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1,
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&Value
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);
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if (EFI_ERROR(Status) || !(Value & BIT16)) {
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break;
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}
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}
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//
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// Disable all SMI in USBLEGCTLSTS
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//
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Status = PciIo->Mem.Read (
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PciIo,
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EfiPciIoWidthUint32,
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XHC_USBCMD_OFFSET,
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ExtendCap + 4,
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1,
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&Value
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);
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if (EFI_ERROR(Status)) {
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break;
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}
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Value &= 0x1F1FEEU;
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Value |= 0xE0000000U;
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PciIo->Mem.Write (
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PciIo,
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EfiPciIoWidthUint32,
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XHC_USBCMD_OFFSET,
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ExtendCap + 4,
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1,
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&Value
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);
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//
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// Clear all ownership
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//
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Status = PciIo->Mem.Read (
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PciIo,
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EfiPciIoWidthUint32,
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XHC_USBCMD_OFFSET,
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ExtendCap,
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1,
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&Value
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);
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if (EFI_ERROR(Status)) {
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break;
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}
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Value &= ~(BIT24 | BIT16);
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PciIo->Mem.Write (
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PciIo,
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EfiPciIoWidthUint32,
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XHC_USBCMD_OFFSET,
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ExtendCap,
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1,
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&Value
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);
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break;
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}
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if (!(Value & XHC_NEXT_CAPABILITY_MASK)) {
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break;
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}
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ExtendCap += ((Value >> 6U) & 0x3FCU);
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}
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return Status;
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}
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/**
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Release EHCI USB controllers ownership.
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@param[in] PciIo PCI I/O protocol for the device.
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@retval EFI_NOT_FOUND No EHCI controllers had ownership incorrectly set.
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@retval EFI_SUCCESS Corrected EHCI controllers ownership to OS.
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**/
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STATIC
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EFI_STATUS
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EhciReleaseOwnership (
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IN EFI_PCI_IO_PROTOCOL *PciIo
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)
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{
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EFI_STATUS Status;
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UINT32 Value;
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UINT32 Base;
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UINT32 OpAddr;
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UINT32 ExtendCap;
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UINT32 UsbCmd;
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UINT32 UsbLegSup;
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UINT32 UsbLegCtlSts;
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UINTN IsOsOwned;
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UINTN IsBiosOwned;
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BOOLEAN IsOwnershipConflict;
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UINT32 HcCapParams;
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INT32 TimeOut;
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Value = 0x0002;
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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0x04,
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1,
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&Value
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);
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Base = 0;
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Status = PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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0x10,
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1,
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&Base
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);
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if (MmioRead8 (Base) < 0x0C) {
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//
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// Config space too small: no legacy implementation.
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//
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return EFI_NOT_FOUND;
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}
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//
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// Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0).
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//
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OpAddr = Base + MmioRead8 (Base);
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Status = PciIo->Mem.Read (
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PciIo,
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EfiPciIoWidthUint32,
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EHC_BAR_INDEX,
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EHC_HCCPARAMS_OFFSET,
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1,
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&HcCapParams
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);
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ExtendCap = (HcCapParams >> 8U) & 0xFFU;
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//
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// Read PCI Config 32bit USBLEGSUP (eecp+0).
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//
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Status = PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap,
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1,
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&UsbLegSup
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);
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IsBiosOwned = (UsbLegSup & BIT16) != 0;
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if (!IsBiosOwned) {
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//
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// No BIOS ownership, ignore.
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//
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return EFI_NOT_FOUND;
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}
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//
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// Read PCI Config 32bit USBLEGCTLSTS (eecp+4).
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//
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap + 0x4,
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1,
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&UsbLegCtlSts
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);
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//
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// Disable the SMI in USBLEGCTLSTS firstly.
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//
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UsbLegCtlSts &= 0xFFFF0000U;
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap + 0x4,
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1,
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&UsbLegCtlSts
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);
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UsbCmd = MmioRead32 (OpAddr + EHC_USBCMD_OFFSET);
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//
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// Clear registers to default.
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//
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UsbCmd = UsbCmd & 0xFFFFFF00U;
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MmioWrite32 (OpAddr + EHC_USBCMD_OFFSET, UsbCmd);
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MmioWrite32 (OpAddr + EHC_USBINT_OFFSET, 0);
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MmioWrite32 (OpAddr + EHC_USBSTS_OFFSET, 0x1000);
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Value = 1;
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap,
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1,
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&Value
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);
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//
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// Read 32bit USBLEGSUP (eecp+0).
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//
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap,
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1,
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&UsbLegSup
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);
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IsBiosOwned = (UsbLegSup & BIT16) != 0;
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IsOsOwned = (UsbLegSup & BIT24) != 0;
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//
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// Read 32bit USBLEGCTLSTS (eecp+4).
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//
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap + 0x4,
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1,
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&UsbLegCtlSts
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);
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//
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// Get EHCI Ownership from legacy bios.
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//
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap,
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1,
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&UsbLegSup
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);
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IsOwnershipConflict = IsBiosOwned && IsOsOwned;
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if (IsOwnershipConflict) {
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//
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// EHCI - Ownership conflict - attempting soft reset.
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//
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Value = 0;
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint8,
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ExtendCap + 3,
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1,
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&Value
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);
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TimeOut = 40;
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while (TimeOut--) {
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gBS->Stall (500);
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap,
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1,
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&Value
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);
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if ((Value & BIT24) == 0x0) {
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break;
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}
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}
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}
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap,
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1,
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&Value
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);
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Value |= BIT24;
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap,
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1,
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&Value
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);
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TimeOut = 40;
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while (TimeOut--) {
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gBS->Stall (500);
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap,
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1,
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&Value
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);
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if ((Value & BIT16) == 0x0) {
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break;
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}
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}
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IsOwnershipConflict = (Value & BIT16) != 0x0;
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if (IsOwnershipConflict) {
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//
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// Soft reset has failed. Assume SMI being ignored and do hard reset.
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//
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Value = 0;
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint8,
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ExtendCap + 2,
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1,
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&Value
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);
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TimeOut = 40;
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while (TimeOut--) {
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gBS->Stall (500);
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap,
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1,
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&Value
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);
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if ((Value & BIT16) == 0x0) {
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break;
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}
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}
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//
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// Disable further SMI events.
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//
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PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap + 0x4,
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1,
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&UsbLegCtlSts
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);
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UsbLegCtlSts &= 0xFFFF0000U;
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PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint32,
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ExtendCap + 0x4,
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1,
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&UsbLegCtlSts
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);
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}
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if (Value & BIT16) {
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//
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// EHCI controller unable to take control from BIOS.
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//
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Status = EFI_NOT_FOUND;
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}
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return Status;
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}
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/**
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Release UHCI USB controllers ownership.
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@param[in] PciIo PCI I/O protocol for the device.
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@retval EFI_NOT_FOUND No UHCI controllers had ownership incorrectly set.
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@retval EFI_SUCCESS Corrected UHCI controllers ownership to OS.
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**/
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STATIC
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EFI_STATUS
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UhciReleaseOwnership (
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IN EFI_PCI_IO_PROTOCOL *PciIo
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)
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{
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EFI_STATUS Status;
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UINT32 Base;
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UINT32 PortBase;
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UINT16 Command;
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Base = 0;
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Status = PciIo->Pci.Read(
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PciIo,
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EfiPciIoWidthUint32,
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0x20,
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1,
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&Base
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);
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PortBase = (Base >> 5) & 0x07ff;
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Command = 0x8f00;
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Status = PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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0xC0,
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1,
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&Command
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);
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if (PortBase != 0 && (PortBase & BIT0) == 0) {
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IoWrite16 (PortBase, 0x0002);
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gBS->Stall (500);
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IoWrite16 (PortBase + 4, 0);
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gBS->Stall (500);
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IoWrite16 (PortBase, 0);
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}
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return Status;
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}
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|
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EFI_STATUS
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ReleaseUsbOwnership (
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VOID
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)
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{
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EFI_STATUS Result;
|
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EFI_STATUS Status;
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EFI_HANDLE *HandleArray;
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UINTN HandleArrayCount;
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UINTN Index;
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EFI_PCI_IO_PROTOCOL *PciIo;
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PCI_TYPE00 Pci;
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Status = gBS->LocateHandleBuffer (
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ByProtocol,
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&gEfiPciIoProtocolGuid,
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NULL,
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&HandleArrayCount,
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&HandleArray
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);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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Result = EFI_UNSUPPORTED;
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for (Index = 0; Index < HandleArrayCount; ++Index) {
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Status = gBS->HandleProtocol (
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HandleArray[Index],
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&gEfiPciIoProtocolGuid,
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(VOID **) &PciIo
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);
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if (EFI_ERROR(Status)) {
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continue;
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}
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Status = PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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0,
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sizeof (Pci) / sizeof (UINT32),
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&Pci
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);
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if (EFI_ERROR(Status)
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|| Pci.Hdr.ClassCode[1] != PCI_CLASS_SERIAL_USB
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|| Pci.Hdr.ClassCode[2] != PCI_CLASS_SERIAL) {
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continue;
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}
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if (Pci.Hdr.ClassCode[0] == PCI_IF_XHCI) {
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Result = XhciReleaseOwnership (PciIo);
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} else if (Pci.Hdr.ClassCode[0] == PCI_IF_EHCI) {
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Result = EhciReleaseOwnership (PciIo);
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} else if (Pci.Hdr.ClassCode[0] == PCI_IF_UHCI) {
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Result = UhciReleaseOwnership (PciIo);
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}
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}
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gBS->FreePool (HandleArray);
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return Result;
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}
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