241 lines
10 KiB
C
Executable File
241 lines
10 KiB
C
Executable File
/** @file
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Copyright (C) 2016 - 2018, The HermitCrabs Lab. All rights reserved.
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All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef OC_PROCESSOR_INFO_H
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#define OC_PROCESSOR_INFO_H
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// SandyBridge/IvyBridge bus clock is fixed at 100MHz
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#define BRIDGE_BCLK 100
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#define BASE_NHM_CLOCK_SOURCE 133333333ULL
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//
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// Skylake bus clock is fixed at 100MHz
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// This constant is also known as BASE_ART_CLOCK_SOURCE in XNU
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//
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#define CLIENT_ART_CLOCK_SOURCE 24000000ULL
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#define SERVER_ART_CLOCK_SOURCE 25000000ULL
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#define ATOM_ART_CLOCK_SOURCE 19200000ULL
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#define DEFAULT_ART_CLOCK_SOURCE CLIENT_ART_CLOCK_SOURCE
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#define MSR_PIC_MSG_CONTROL 0x2E
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#define MSR_CORE_THREAD_COUNT 0x35
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#define EFI_PLATFORM_INFORMATION 0x000000CE
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#define N_EFI_PLATFORM_INFO_MIN_RATIO 40
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#define B_EFI_PLATFORM_INFO_RATIO_MASK 0xFF
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#define N_EFI_PLATFORM_INFO_MAX_RATIO 8
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#define B_EFI_PLATFORM_INFO_TDC_TDP_LIMIT (1 << 29)
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#define N_EFI_PLATFORM_INFO_RATIO_LIMIT 28
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#define B_EFI_PLATFORM_INFO_RATIO_LIMIT (1 << 28)
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#define B_EFI_PLATFORM_INFO_SMM_SAVE_CONTROL (1 << 16)
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#define N_EFI_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET 30
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#define B_EFI_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET (1 << 30)
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//#define PLATFORM_INFO_SET_TDP
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#define MSR_PMG_IO_CAPTURE_BASE 0xE4
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#define MSR_IA32_EXT_CONFIG 0xEE
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#define MSR_FEATURE_CONFIG 0x13C
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#define MSR_FLEX_RATIO 0x194
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#define FLEX_RATIO_LOCK (1U << 20U)
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#define FLEX_RATIO_EN (1U << 16U)
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#define MSR_IA32_PERF_CONTROL 0x199
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#define MSR_THERM2_CTL 0x19D
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#define MSR_IA32_MISC_ENABLES 0x1A0
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#define TURBO_DISABLE_MASK ((UINT64)1 << 38)
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#define TURBO_MODE_DISABLE_BIT 38
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#define MSR_TEMPERATURE_TARGET 0x1A2
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#define MSR_MISC_PWR_MGMT 0x1AA
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#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
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#define MISC_PWR_MGMT_LOCK (1 << 13)
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#define MAX_RATIO_LIMIT_8C_OFFSET 56
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#define MAX_RATIO_LIMIT_7C_OFFSET 48
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#define MAX_RATIO_LIMIT_6C_OFFSET 40
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#define MAX_RATIO_LIMIT_5C_OFFSET 32
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#define MAX_RATIO_LIMIT_4C_OFFSET 24
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#define MAX_RATIO_LIMIT_3C_OFFSET 16
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#define MAX_RATIO_LIMIT_2C_OFFSET 8
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#define MAX_RATIO_LIMIT_1C_OFFSET 0
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#define MAX_RATIO_LIMIT_MASK 0xff
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#define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1B0
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#define ENERGY_POLICY_PERFORMANCE 0
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#define ENERGY_POLICY_NORMAL 6
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#define ENERGY_POLICY_POWERSAVE 15
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#define MSR_POWER_CTL 0x1FC
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#define MSR_LT_LOCK_MEMORY 0x2E7
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#define MSR_IA32_CR_PAT 0x277
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// Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.
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#define MSR_PP0_CURRENT_CONFIG 0x601
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#define PP0_CURRENT_LIMIT (112 << 3) ///< 112 A
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#define MSR_PP1_CURRENT_CONFIG 0x602
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#define PP1_CURRENT_LIMIT (35 << 3) ///< 35 A
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#define MSR_PKG_POWER_SKU_UNIT 0x606
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#define MSR_PKGC3_IRTL 0x60A
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#define MSR_PKGC6_IRTL 0x60B
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#define MSR_PKGC7_IRTL 0x60C
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#define IRTL_VALID (1 << 15)
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#define IRTL_1_NS (0 << 10)
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#define IRTL_32_NS (1 << 10)
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#define IRTL_1024_NS (2 << 10)
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#define IRTL_32768_NS (3 << 10)
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#define IRTL_1048576_NS (4 << 10)
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#define IRTL_33554432_NS (5 << 10)
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#define IRTL_RESPONSE_MASK (0x3ff)
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// long duration in low dword, short duration in high dword
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#define MSR_PKG_POWER_LIMIT 0x610
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#define PKG_POWER_LIMIT_MASK 0x7fff
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#define PKG_POWER_LIMIT_EN (1 << 15)
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#define PKG_POWER_LIMIT_CLAMP (1 << 16)
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#define PKG_POWER_LIMIT_TIME_SHIFT 17
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#define PKG_POWER_LIMIT_TIME_MASK 0x7f
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#define MSR_PKG_ENERGY_STATUS 0x611
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#define MSR_PKG_PERF_STATUS 0x613
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#define MSR_PKG_POWER_SKU 0x614
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// Sandy Bridge IA (Core) domain MSR's.
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#define MSR_PP0_POWER_LIMIT 0x638
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#define MSR_PP0_ENERGY_STATUS 0x639
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#define MSR_PP0_POLICY 0x63A
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#define MSR_PP0_PERF_STATUS 0x63B
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// Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).
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#define MSR_PP1_POWER_LIMIT 0x640
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#define MSR_PP1_ENERGY_STATUS 0x641
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#define MSR_PP1_POLICY 0x642
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// JakeTown only Memory MSR's.
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#define MSR_DRAM_POWER_LIMIT 0x618
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#define MSR_DRAM_ENERGY_STATUS 0x619
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#define MSR_DRAM_PERF_STATUS 0x61B
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#define MSR_DRAM_POWER_INFO 0x61C
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/// x86 Page Address Translation
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enum {
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PageAddressTranslationUncached = 0,
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PageAddressTranslationWriteCombining = 1,
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PageAddressTranslationWriteThrough = 4,
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PageAddressTranslationWriteProtected = 5,
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PageAddressTranslationWriteBack = 6,
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/// Uncached, but can be overriden by MTRR
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PageAddressTranslationOverridableUncached = 7,
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};
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#define K8_FIDVID_STATUS 0xC0010042
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#define K10_COFVID_STATUS 0xC0010071
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#define K10_PSTATE_STATUS 0xC0010064
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#define CPU_MODEL_DOTHAN 0x0D ///< Dothan
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#define CPU_MODEL_YONAH 0x0E ///< Sossaman, Yonah
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#define CPU_MODEL_MEROM 0x0F ///< Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom
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#define CPU_MODEL_PENRYN 0x17 ///< Wolfdale, Yorkfield, Harpertown, Penryn
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#define CPU_MODEL_NEHALEM 0x1A ///< Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown
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#define CPU_MODEL_ATOM 0x1C ///< Atom
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#define CPU_MODEL_FIELDS 0x1E ///< Lynnfield, Clarksfield, Jasper Forest
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#define CPU_MODEL_DALES 0x1F ///< Havendale, Auburndale
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#define CPU_MODEL_NEHALEM_EX 0x2E ///< Beckton
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#define CPU_MODEL_DALES_32NM 0x25 ///< Clarkdale, Arrandale
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#define CPU_MODEL_WESTMERE 0x2C ///< Gulftown, Westmere-EP, Westmere-WS
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#define CPU_MODEL_WESTMERE_EX 0x2F
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#define CPU_MODEL_SANDYBRIDGE 0x2A ///< Sandy Bridge
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#define CPU_MODEL_JAKETOWN 0x2D ///< Sandy Bridge Xeon E5, Core i7 Extreme
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#define CPU_MODEL_IVYBRIDGE 0x3A ///< Ivy Bridge
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#define CPU_MODEL_IVYBRIDGE_EP 0x3E
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#define CPU_MODEL_CRYSTALWELL 0x46
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#define CPU_MODEL_HASWELL 0x3C
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#define CPU_MODEL_HASWELL_EP 0x3F ///< Haswell MB
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#define CPU_MODEL_HASWELL_ULT 0x45 ///< Haswell ULT
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#define CPU_MODEL_BROADWELL 0x3D ///< Broadwell
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#define CPU_MODEL_BROADWELL_EP 0x4F ///< Broadwell_EP
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#define CPU_MODEL_BROADWELL_ULX 0x3D
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#define CPU_MODEL_BROADWELL_ULT 0x3D
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#define CPU_MODEL_BRYSTALWELL 0x47
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#define CPU_MODEL_AIRMONT 0x4C ///< CherryTrail / Braswell
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#define CPU_MODEL_AVOTON 0x4D ///< Avaton/Rangely
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#define CPU_MODEL_SKYLAKE 0x4E ///< Skylake-S
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#define CPU_MODEL_SKYLAKE_ULT 0x4E
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#define CPU_MODEL_SKYLAKE_ULX 0x4E
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#define CPU_MODEL_SKYLAKE_DT 0x5E
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#define CPU_MODEL_SKYLAKE_W 0x55
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#define CPU_MODEL_GOLDMONT 0x5C ///< Apollo Lake
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#define CPU_MODEL_DENVERTON 0x5F ///< Goldmont Microserver
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#define CPU_MODEL_CANNONLAKE 0x66
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#define CPU_MODEL_XEON_MILL 0x85 ///< Knights Mill
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#define CPU_MODEL_KABYLAKE 0x8E ///< Kabylake Dektop
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#define CPU_MODEL_KABYLAKE_ULT 0x8E
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#define CPU_MODEL_KABYLAKE_ULX 0x8E
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#define CPU_MODEL_KABYLAKE_DT 0x9E
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#define CPU_MODEL_COFFEELAKE 0x9E
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#define CPU_MODEL_COFFEELAKE_ULT 0x9E
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#define CPU_MODEL_COFFEELAKE_ULX 0x9E
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#define CPU_MODEL_COFFEELAKE_DT 0x9E
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#define CPU_MODEL_ICELAKE_Y 0x7D
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#define CPU_MODEL_ICELAKE_U 0x7E
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#define CPU_MODEL_ICELAKE_SP 0x9F /* Some variation of Ice Lake */
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//#define CPU_MODEL_COMETLAKE_S 0xA5 /* desktop CometLake */
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#define CPU_MODEL_COMETLAKE_Y 0xA5 /* aka 10th generation Amber Lake Y */
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#define CPU_MODEL_COMETLAKE_U 0xA6
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//From Clover collection
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#define CPU_MODEL_ATOM_TM 0x86 /* Tremont */
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#define CPU_MODEL_TIGERLAKE_C 0x8C /* 11h generation Tiger Lake */
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#define CPU_MODEL_TIGERLAKE_D 0x8D /* 11h generation Tiger Lake */
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#define CPU_MODEL_ALDERLAKE 0x97 /* 12h generation Alder Lake */
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#define CPU_MODEL_ALDERLAKE_ULT 0x9A /* 12h generation Alder Lake, i5-12500h */
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#define CPU_MODEL_ROCKETLAKE 0xA7 /* 11h Rocket Lake */
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#define CPU_MODEL_RAPTORLAKE 0xB7 /* 13h Raptor Lake */
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#define CPU_MODEL_RAPTORLAKE_B 0xBF /* 13h Raptor Lake, i5-13400h */
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#define CPU_MODEL_METEORLAKE 0xAA /* 14h Meteor Lake */
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#define CPU_SOCKET_UNKNOWN 0x02
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#define CPU_SOCKET_PGA478 0x0F
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#define CPU_SOCKET_LGA771 0x14
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#define CPU_SOCKET_LGA775 0x15
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#define CPU_SOCKET_LGA1156 0x1D
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#define CPU_SOCKET_LGA1366 0x19
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#define AMD_CPU_FAMILY 0xF
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#define AMD_CPU_EXT_FAMILY_0FH 0x0
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#define AMD_CPU_EXT_FAMILY_10H 0x1
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#define AMD_CPU_EXT_FAMILY_15H 0x6
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#define AMD_CPU_EXT_FAMILY_16H 0x7
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#define AMD_CPU_EXT_FAMILY_17H 0x8
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#define AMD_CPU_EXT_FAMILY_19H 0xA
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// CPU_P_STATE_COORDINATION
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/// P-State Coordination
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typedef enum {
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/// The OS Power Manager is responsible for coordinating the P-state among logical
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/// processors with dependencies and must initiate the transition on all of those Logical Processors.
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CpuPStateCoordinationSoftwareAll = 0xFC,
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/// The OS Power Manager is responsible for coordinating the P-state among logical
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/// processors with dependencies and may initiate the transition on any of those Logical Processors.
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CpuPStateCoordinationSoftwareAny = 0xFD,
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/// The processor hardware is responsible for coordinating the P-state among logical
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/// processors dependencies. The OS is responsible for keeping the P-state request up to date on all
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/// logical processors.
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CpuPStateCoordinationHardwareAll = 0xFE
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} CPU_P_STATE_COORDINATION;
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#endif // OC_PROCESSOR_INFO_H
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