mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
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385 lines
15 KiB
C
385 lines
15 KiB
C
/** @file
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Header file for AHCI mode of ATA host controller.
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Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __ATA_HC_AHCI_MODE_H__
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#define __ATA_HC_AHCI_MODE_H__
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#define EFI_AHCI_BAR_INDEX 0x05
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#define EFI_AHCI_CAPABILITY_OFFSET 0x0000
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#define EFI_AHCI_CAP_SAM BIT18
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#define EFI_AHCI_CAP_SSS BIT27
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#define EFI_AHCI_CAP_S64A BIT31
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#define EFI_AHCI_GHC_OFFSET 0x0004
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#define EFI_AHCI_GHC_RESET BIT0
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#define EFI_AHCI_GHC_IE BIT1
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#define EFI_AHCI_GHC_ENABLE BIT31
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#define EFI_AHCI_IS_OFFSET 0x0008
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#define EFI_AHCI_PI_OFFSET 0x000C
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#define EFI_AHCI_MAX_PORTS 32
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#define AHCI_CAPABILITY2_OFFSET 0x0024
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#define AHCI_CAP2_SDS BIT3
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#define AHCI_CAP2_SADM BIT4
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typedef struct {
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UINT32 Lower32;
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UINT32 Upper32;
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} DATA_32;
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typedef union {
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DATA_32 Uint32;
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UINT64 Uint64;
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} DATA_64;
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//
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// Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
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// Add a bit of margin for robustness.
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//
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#define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 15
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//
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// Refer SATA1.0a spec, the FIS enable time should be less than 500ms.
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//
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#define EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT EFI_TIMER_PERIOD_MILLISECONDS(500)
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//
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// Refer SATA1.0a spec, the bus reset time should be less than 1s.
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//
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#define EFI_AHCI_BUS_RESET_TIMEOUT EFI_TIMER_PERIOD_SECONDS(1)
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#define EFI_AHCI_ATAPI_DEVICE_SIG 0xEB140000
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#define EFI_AHCI_ATA_DEVICE_SIG 0x00000000
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#define EFI_AHCI_PORT_MULTIPLIER_SIG 0x96690000
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#define EFI_AHCI_ATAPI_SIG_MASK 0xFFFF0000
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//
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// Each PRDT entry can point to a memory block up to 4M byte
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//
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#define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000
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#define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device
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#define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20
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#define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host
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#define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20
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#define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host
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#define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4
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#define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional
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#define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28
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#define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional
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#define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional
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#define EFI_AHCI_FIS_BIST_LENGTH 12
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#define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host
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#define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20
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#define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host
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#define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8
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#define EFI_AHCI_D2H_FIS_OFFSET 0x40
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#define EFI_AHCI_DMA_FIS_OFFSET 0x00
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#define EFI_AHCI_PIO_FIS_OFFSET 0x20
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#define EFI_AHCI_SDB_FIS_OFFSET 0x58
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#define EFI_AHCI_FIS_TYPE_MASK 0xFF
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#define EFI_AHCI_U_FIS_OFFSET 0x60
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//
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// Port register
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//
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#define EFI_AHCI_PORT_START 0x0100
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#define EFI_AHCI_PORT_REG_WIDTH 0x0080
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#define EFI_AHCI_PORT_CLB 0x0000
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#define EFI_AHCI_PORT_CLBU 0x0004
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#define EFI_AHCI_PORT_FB 0x0008
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#define EFI_AHCI_PORT_FBU 0x000C
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#define EFI_AHCI_PORT_IS 0x0010
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#define EFI_AHCI_PORT_IS_DHRS BIT0
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#define EFI_AHCI_PORT_IS_PSS BIT1
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#define EFI_AHCI_PORT_IS_SSS BIT2
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#define EFI_AHCI_PORT_IS_SDBS BIT3
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#define EFI_AHCI_PORT_IS_UFS BIT4
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#define EFI_AHCI_PORT_IS_DPS BIT5
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#define EFI_AHCI_PORT_IS_PCS BIT6
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#define EFI_AHCI_PORT_IS_DIS BIT7
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#define EFI_AHCI_PORT_IS_PRCS BIT22
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#define EFI_AHCI_PORT_IS_IPMS BIT23
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#define EFI_AHCI_PORT_IS_OFS BIT24
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#define EFI_AHCI_PORT_IS_INFS BIT26
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#define EFI_AHCI_PORT_IS_IFS BIT27
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#define EFI_AHCI_PORT_IS_HBDS BIT28
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#define EFI_AHCI_PORT_IS_HBFS BIT29
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#define EFI_AHCI_PORT_IS_TFES BIT30
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#define EFI_AHCI_PORT_IS_CPDS BIT31
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#define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF
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#define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F
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#define EFI_AHCI_PORT_IE 0x0014
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#define EFI_AHCI_PORT_CMD 0x0018
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#define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE
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#define EFI_AHCI_PORT_CMD_ST BIT0
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#define EFI_AHCI_PORT_CMD_SUD BIT1
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#define EFI_AHCI_PORT_CMD_POD BIT2
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#define EFI_AHCI_PORT_CMD_CLO BIT3
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#define EFI_AHCI_PORT_CMD_CR BIT15
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#define EFI_AHCI_PORT_CMD_FRE BIT4
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#define EFI_AHCI_PORT_CMD_FR BIT14
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#define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
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#define EFI_AHCI_PORT_CMD_PMA BIT17
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#define EFI_AHCI_PORT_CMD_HPCP BIT18
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#define EFI_AHCI_PORT_CMD_MPSP BIT19
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#define EFI_AHCI_PORT_CMD_CPD BIT20
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#define EFI_AHCI_PORT_CMD_ESP BIT21
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#define EFI_AHCI_PORT_CMD_ATAPI BIT24
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#define EFI_AHCI_PORT_CMD_DLAE BIT25
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#define EFI_AHCI_PORT_CMD_ALPE BIT26
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#define EFI_AHCI_PORT_CMD_ASP BIT27
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#define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
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#define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )
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#define EFI_AHCI_PORT_TFD 0x0020
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#define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)
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#define EFI_AHCI_PORT_TFD_BSY BIT7
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#define EFI_AHCI_PORT_TFD_DRQ BIT3
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#define EFI_AHCI_PORT_TFD_ERR BIT0
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#define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00
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#define EFI_AHCI_PORT_SIG 0x0024
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#define EFI_AHCI_PORT_SSTS 0x0028
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#define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F
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#define EFI_AHCI_PORT_SSTS_DET 0x0001
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#define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003
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#define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0
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#define EFI_AHCI_PORT_SCTL 0x002C
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#define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F
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#define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)
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#define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001
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#define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003
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#define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0
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#define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00
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#define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300
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#define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100
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#define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200
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#define EFI_AHCI_PORT_SERR 0x0030
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#define EFI_AHCI_PORT_SERR_RDIE BIT0
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#define EFI_AHCI_PORT_SERR_RCE BIT1
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#define EFI_AHCI_PORT_SERR_TDIE BIT8
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#define EFI_AHCI_PORT_SERR_PCDIE BIT9
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#define EFI_AHCI_PORT_SERR_PE BIT10
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#define EFI_AHCI_PORT_SERR_IE BIT11
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#define EFI_AHCI_PORT_SERR_PRC BIT16
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#define EFI_AHCI_PORT_SERR_PIE BIT17
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#define EFI_AHCI_PORT_SERR_CW BIT18
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#define EFI_AHCI_PORT_SERR_BDE BIT19
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#define EFI_AHCI_PORT_SERR_DE BIT20
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#define EFI_AHCI_PORT_SERR_CRCE BIT21
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#define EFI_AHCI_PORT_SERR_HE BIT22
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#define EFI_AHCI_PORT_SERR_LSE BIT23
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#define EFI_AHCI_PORT_SERR_TSTE BIT24
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#define EFI_AHCI_PORT_SERR_UFT BIT25
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#define EFI_AHCI_PORT_SERR_EX BIT26
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#define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF
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#define EFI_AHCI_PORT_SACT 0x0034
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#define EFI_AHCI_PORT_CI 0x0038
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#define EFI_AHCI_PORT_SNTF 0x003C
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#define AHCI_PORT_DEVSLP 0x0044
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#define AHCI_PORT_DEVSLP_ADSE BIT0
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#define AHCI_PORT_DEVSLP_DSP BIT1
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#define AHCI_PORT_DEVSLP_DETO_MASK 0x000003FC
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#define AHCI_PORT_DEVSLP_MDAT_MASK 0x00007C00
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#define AHCI_PORT_DEVSLP_DITO_MASK 0x01FF8000
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#define AHCI_PORT_DEVSLP_DM_MASK 0x1E000000
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#pragma pack(1)
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//
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// Command List structure includes total 32 entries.
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// The entry data structure is listed at the following.
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//
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typedef struct {
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UINT32 AhciCmdCfl:5; //Command FIS Length
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UINT32 AhciCmdA:1; //ATAPI
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UINT32 AhciCmdW:1; //Write
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UINT32 AhciCmdP:1; //Prefetchable
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UINT32 AhciCmdR:1; //Reset
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UINT32 AhciCmdB:1; //BIST
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UINT32 AhciCmdC:1; //Clear Busy upon R_OK
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UINT32 AhciCmdRsvd:1;
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UINT32 AhciCmdPmp:4; //Port Multiplier Port
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UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length
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UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count
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UINT32 AhciCmdCtba; //Command Table Descriptor Base Address
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UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs
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UINT32 AhciCmdRsvd1[4];
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} EFI_AHCI_COMMAND_LIST;
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//
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// This is a software constructed FIS.
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// For data transfer operations, this is the H2D Register FIS format as
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// specified in the Serial ATA Revision 2.6 specification.
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//
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typedef struct {
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UINT8 AhciCFisType;
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UINT8 AhciCFisPmNum:4;
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UINT8 AhciCFisRsvd:1;
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UINT8 AhciCFisRsvd1:1;
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UINT8 AhciCFisRsvd2:1;
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UINT8 AhciCFisCmdInd:1;
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UINT8 AhciCFisCmd;
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UINT8 AhciCFisFeature;
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UINT8 AhciCFisSecNum;
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UINT8 AhciCFisClyLow;
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UINT8 AhciCFisClyHigh;
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UINT8 AhciCFisDevHead;
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UINT8 AhciCFisSecNumExp;
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UINT8 AhciCFisClyLowExp;
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UINT8 AhciCFisClyHighExp;
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UINT8 AhciCFisFeatureExp;
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UINT8 AhciCFisSecCount;
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UINT8 AhciCFisSecCountExp;
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UINT8 AhciCFisRsvd3;
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UINT8 AhciCFisControl;
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UINT8 AhciCFisRsvd4[4];
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UINT8 AhciCFisRsvd5[44];
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} EFI_AHCI_COMMAND_FIS;
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//
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// ACMD: ATAPI command (12 or 16 bytes)
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//
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typedef struct {
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UINT8 AtapiCmd[0x10];
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} EFI_AHCI_ATAPI_COMMAND;
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//
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// Physical Region Descriptor Table includes up to 65535 entries
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// The entry data structure is listed at the following.
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// the actual entry number comes from the PRDTL field in the command
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// list entry for this command slot.
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//
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typedef struct {
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UINT32 AhciPrdtDba; //Data Base Address
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UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs
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UINT32 AhciPrdtRsvd;
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UINT32 AhciPrdtDbc:22; //Data Byte Count
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UINT32 AhciPrdtRsvd1:9;
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UINT32 AhciPrdtIoc:1; //Interrupt on Completion
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} EFI_AHCI_COMMAND_PRDT;
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//
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// Command table data strucute which is pointed to by the entry in the command list
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//
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typedef struct {
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EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.
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EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd.
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UINT8 Reserved[0x30];
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EFI_AHCI_COMMAND_PRDT PrdtTable[65535]; // The scatter/gather list for data transfer
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} EFI_AHCI_COMMAND_TABLE;
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//
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// Received FIS structure
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//
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typedef struct {
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UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00
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UINT8 AhciDmaSetupFisRsvd[0x04];
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UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20
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UINT8 AhciPioSetupFisRsvd[0x0C];
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UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40
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UINT8 AhciD2HRegisterFisRsvd[0x04];
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UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58
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UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60
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UINT8 AhciUnknownFisRsvd[0x60];
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} EFI_AHCI_RECEIVED_FIS;
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typedef struct {
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UINT8 Madt : 5;
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UINT8 Reserved_5 : 3;
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UINT8 Deto;
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UINT16 Reserved_16;
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UINT32 Reserved_32 : 31;
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UINT32 Supported : 1;
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} DEVSLP_TIMING_VARIABLES;
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#pragma pack()
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typedef struct {
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EFI_AHCI_RECEIVED_FIS *AhciRFis;
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EFI_AHCI_COMMAND_LIST *AhciCmdList;
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EFI_AHCI_COMMAND_TABLE *AhciCommandTable;
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EFI_AHCI_RECEIVED_FIS *AhciRFisPciAddr;
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EFI_AHCI_COMMAND_LIST *AhciCmdListPciAddr;
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EFI_AHCI_COMMAND_TABLE *AhciCommandTablePciAddr;
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UINT64 MaxCommandListSize;
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UINT64 MaxCommandTableSize;
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UINT64 MaxReceiveFisSize;
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VOID *MapRFis;
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VOID *MapCmdList;
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VOID *MapCommandTable;
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} EFI_AHCI_REGISTERS;
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/**
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This function is used to send out ATAPI commands conforms to the Packet Command
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with PIO Protocol.
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@param PciIo The PCI IO protocol instance.
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@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
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@param Port The number of port.
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@param PortMultiplier The number of port multiplier.
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@param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
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@retval EFI_SUCCESS send out the ATAPI packet command successfully
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and device sends data successfully.
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@retval EFI_DEVICE_ERROR the device failed to send data.
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**/
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EFI_STATUS
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EFIAPI
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AhciPacketCommandExecute (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN EFI_AHCI_REGISTERS *AhciRegisters,
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IN UINT8 Port,
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IN UINT8 PortMultiplier,
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IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
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);
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/**
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Start command for give slot on specific port.
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@param PciIo The PCI IO protocol instance.
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@param Port The number of port.
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@param CommandSlot The number of CommandSlot.
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@param Timeout The timeout value of start, uses 100ns as a unit.
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@retval EFI_DEVICE_ERROR The command start unsuccessfully.
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@retval EFI_TIMEOUT The operation is time out.
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@retval EFI_SUCCESS The command start successfully.
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**/
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EFI_STATUS
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EFIAPI
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AhciStartCommand (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 Port,
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IN UINT8 CommandSlot,
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IN UINT64 Timeout
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);
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/**
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Stop command running for giving port
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@param PciIo The PCI IO protocol instance.
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@param Port The number of port.
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@param Timeout The timeout value of stop, uses 100ns as a unit.
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@retval EFI_DEVICE_ERROR The command stop unsuccessfully.
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@retval EFI_TIMEOUT The operation is time out.
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@retval EFI_SUCCESS The command stop successfully.
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**/
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EFI_STATUS
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EFIAPI
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AhciStopCommand (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 Port,
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IN UINT64 Timeout
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);
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#endif
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