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https://github.com/CloverHackyColor/CloverBootloader.git
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243 lines
5.7 KiB
C
243 lines
5.7 KiB
C
/** @file
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The definition for UHCI register operation routines.
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Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _EFI_UHCI_REG_H_
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#define _EFI_UHCI_REG_H_
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//
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// UHCI register offset
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//
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#define UHCI_FRAME_NUM 1024
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//
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// Register offset and PCI related staff
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//
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#define USB_BAR_INDEX 4
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#define USBCMD_OFFSET 0
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#define USBSTS_OFFSET 2
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#define USBINTR_OFFSET 4
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#define USBPORTSC_OFFSET 0x10
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#define USB_FRAME_NO_OFFSET 6
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#define USB_FRAME_BASE_OFFSET 8
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#define USB_EMULATION_OFFSET 0xC0
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//
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// Packet IDs
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//
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#define SETUP_PACKET_ID 0x2D
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#define INPUT_PACKET_ID 0x69
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#define OUTPUT_PACKET_ID 0xE1
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#define ERROR_PACKET_ID 0x55
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//
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// USB port status and control bit definition.
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//
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#define USBPORTSC_CCS BIT0 // Current Connect Status
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#define USBPORTSC_CSC BIT1 // Connect Status Change
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#define USBPORTSC_PED BIT2 // Port Enable / Disable
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#define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change
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#define USBPORTSC_LSL BIT4 // Line Status Low BIT
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#define USBPORTSC_LSH BIT5 // Line Status High BIT
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#define USBPORTSC_RD BIT6 // Resume Detect
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#define USBPORTSC_LSDA BIT8 // Low Speed Device Attached
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#define USBPORTSC_PR BIT9 // Port Reset
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#define USBPORTSC_SUSP BIT12 // Suspend
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//
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// UHCI Spec said it must implement 2 ports each host at least,
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// and if more, check whether the bit7 of PORTSC is always 1.
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// So here assume the max of port number each host is 16.
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//
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#define USB_MAX_ROOTHUB_PORT 0x0F
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//
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// Command register bit definitions
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//
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#define USBCMD_RS BIT0 // Run/Stop
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#define USBCMD_HCRESET BIT1 // Host reset
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#define USBCMD_GRESET BIT2 // Global reset
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#define USBCMD_EGSM BIT3 // Global Suspend Mode
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#define USBCMD_FGR BIT4 // Force Global Resume
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#define USBCMD_SWDBG BIT5 // SW Debug mode
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#define USBCMD_CF BIT6 // Config Flag (sw only)
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#define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)
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//
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// USB Status register bit definitions
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//
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#define USBSTS_USBINT BIT0 // Interrupt due to IOC
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#define USBSTS_ERROR BIT1 // Interrupt due to error
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#define USBSTS_RD BIT2 // Resume Detect
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#define USBSTS_HSE BIT3 // Host System Error
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#define USBSTS_HCPE BIT4 // Host Controller Process Error
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#define USBSTS_HCH BIT5 // HC Halted
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#define USBTD_ACTIVE BIT7 // TD is still active
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#define USBTD_STALLED BIT6 // TD is stalled
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#define USBTD_BUFFERR BIT5 // Buffer underflow or overflow
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#define USBTD_BABBLE BIT4 // Babble condition
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#define USBTD_NAK BIT3 // NAK is received
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#define USBTD_CRC BIT2 // CRC/Time out error
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#define USBTD_BITSTUFF BIT1 // Bit stuff error
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/**
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Read a UHCI register.
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@param PciIo The EFI_PCI_IO_PROTOCOL to use.
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@param Offset Register offset to USB_BAR_INDEX.
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@return Content of register.
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**/
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UINT16
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UhciReadReg (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT32 Offset
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);
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/**
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Write data to UHCI register.
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@param PciIo The EFI_PCI_IO_PROTOCOL to use.
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@param Offset Register offset to USB_BAR_INDEX.
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@param Data Data to write.
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@return None.
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**/
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VOID
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UhciWriteReg (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT32 Offset,
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IN UINT16 Data
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);
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/**
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Set a bit of the UHCI Register.
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@param PciIo The EFI_PCI_IO_PROTOCOL to use.
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@param Offset Register offset to USB_BAR_INDEX.
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@param Bit The bit to set.
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@return None.
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**/
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VOID
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UhciSetRegBit (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT32 Offset,
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IN UINT16 Bit
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);
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/**
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Clear a bit of the UHCI Register.
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@param PciIo The PCI_IO protocol to access the PCI.
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@param Offset Register offset to USB_BAR_INDEX.
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@param Bit The bit to clear.
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@return None.
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**/
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VOID
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UhciClearRegBit (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT32 Offset,
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IN UINT16 Bit
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);
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/**
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Clear all the interrutp status bits, these bits
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are Write-Clean.
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@param Uhc The UHCI device.
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@return None.
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**/
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VOID
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UhciAckAllInterrupt (
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IN USB_HC_DEV *Uhc
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);
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/**
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Stop the host controller.
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@param Uhc The UHCI device.
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@param Timeout Max time allowed.
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@retval EFI_SUCCESS The host controller is stopped.
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@retval EFI_TIMEOUT Failed to stop the host controller.
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**/
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EFI_STATUS
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UhciStopHc (
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IN USB_HC_DEV *Uhc,
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IN UINTN Timeout
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);
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/**
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Check whether the host controller operates well.
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@param PciIo The PCI_IO protocol to use.
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@retval TRUE Host controller is working.
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@retval FALSE Host controller is halted or system error.
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**/
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BOOLEAN
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UhciIsHcWorking (
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IN EFI_PCI_IO_PROTOCOL *PciIo
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);
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/**
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Set the UHCI frame list base address. It can't use
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UhciWriteReg which access memory in UINT16.
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@param PciIo The EFI_PCI_IO_PROTOCOL to use.
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@param Addr Address to set.
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@return None.
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**/
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VOID
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UhciSetFrameListBaseAddr (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN VOID *Addr
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);
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/**
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Disable USB Emulation.
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@param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.
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@return None.
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**/
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VOID
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UhciTurnOffUsbEmulation (
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IN EFI_PCI_IO_PROTOCOL *PciIo
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);
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#endif
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