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https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-11-24 11:45:27 +01:00
155 lines
2.9 KiB
ArmAsm
155 lines
2.9 KiB
ArmAsm
#include "arm_arch.h"
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.text
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.code 32
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.align 5
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.global _armv7_neon_probe
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.type _armv7_neon_probe,%function
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_armv7_neon_probe:
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.word 0xf26ee1fe @ vorr q15,q15,q15
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.word 0xe12fff1e @ bx lr
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.size _armv7_neon_probe,.-_armv7_neon_probe
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.global _armv7_tick
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.type _armv7_tick,%function
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_armv7_tick:
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mrc p15,0,r0,c9,c13,0
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.word 0xe12fff1e @ bx lr
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.size _armv7_tick,.-_armv7_tick
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.global OPENSSL_atomic_add
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.type OPENSSL_atomic_add,%function
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OPENSSL_atomic_add:
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#if __ARM_ARCH__>=6
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.Ladd: ldrex r2,[r0]
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add r3,r2,r1
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strex r2,r3,[r0]
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cmp r2,#0
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bne .Ladd
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mov r0,r3
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.word 0xe12fff1e @ bx lr
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#else
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stmdb sp!,{r4-r6,lr}
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ldr r2,.Lspinlock
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adr r3,.Lspinlock
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mov r4,r0
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mov r5,r1
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add r6,r3,r2 @ &spinlock
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b .+8
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.Lspin: bl sched_yield
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mov r0,#-1
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swp r0,r0,[r6]
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cmp r0,#0
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bne .Lspin
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ldr r2,[r4]
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add r2,r2,r5
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str r2,[r4]
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str r0,[r6] @ release spinlock
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ldmia sp!,{r4-r6,lr}
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.size OPENSSL_atomic_add,.-OPENSSL_atomic_add
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.global OPENSSL_cleanse
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.type OPENSSL_cleanse,%function
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OPENSSL_cleanse:
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eor ip,ip,ip
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cmp r1,#7
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subhs r1,r1,#4
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bhs .Lot
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cmp r1,#0
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beq .Lcleanse_done
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.Little:
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strb ip,[r0],#1
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subs r1,r1,#1
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bhi .Little
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b .Lcleanse_done
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.Lot: tst r0,#3
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beq .Laligned
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strb ip,[r0],#1
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sub r1,r1,#1
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b .Lot
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.Laligned:
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str ip,[r0],#4
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subs r1,r1,#4
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bhs .Laligned
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adds r1,r1,#4
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bne .Little
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.Lcleanse_done:
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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.size OPENSSL_cleanse,.-OPENSSL_cleanse
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.global OPENSSL_wipe_cpu
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.type OPENSSL_wipe_cpu,%function
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OPENSSL_wipe_cpu:
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ldr r0,.LOPENSSL_armcap
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adr r1,.LOPENSSL_armcap
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ldr r0,[r1,r0]
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eor r2,r2,r2
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eor r3,r3,r3
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eor ip,ip,ip
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tst r0,#1
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beq .Lwipe_done
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.word 0xf3000150 @ veor q0, q0, q0
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.word 0xf3022152 @ veor q1, q1, q1
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.word 0xf3044154 @ veor q2, q2, q2
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.word 0xf3066156 @ veor q3, q3, q3
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.word 0xf34001f0 @ veor q8, q8, q8
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.word 0xf34221f2 @ veor q9, q9, q9
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.word 0xf34441f4 @ veor q10, q10, q10
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.word 0xf34661f6 @ veor q11, q11, q11
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.word 0xf34881f8 @ veor q12, q12, q12
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.word 0xf34aa1fa @ veor q13, q13, q13
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.word 0xf34cc1fc @ veor q14, q14, q14
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.word 0xf34ee1fe @ veor q15, q15, q15
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.Lwipe_done:
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mov r0,sp
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
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.global OPENSSL_instrument_bus
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.type OPENSSL_instrument_bus,%function
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OPENSSL_instrument_bus:
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eor r0,r0,r0
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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.size OPENSSL_instrument_bus,.-OPENSSL_instrument_bus
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.global OPENSSL_instrument_bus2
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.type OPENSSL_instrument_bus2,%function
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OPENSSL_instrument_bus2:
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eor r0,r0,r0
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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.size OPENSSL_instrument_bus2,.-OPENSSL_instrument_bus2
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.align 5
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.LOPENSSL_armcap:
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.word OPENSSL_armcap_P-.LOPENSSL_armcap
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#if __ARM_ARCH__>=6
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.align 5
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#else
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.Lspinlock:
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.word atomic_add_spinlock-.Lspinlock
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.align 5
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.data
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.align 2
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atomic_add_spinlock:
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.word 0
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#endif
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.comm OPENSSL_armcap_P,4,4
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.hidden OPENSSL_armcap_P
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