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81 lines
1.9 KiB
C
81 lines
1.9 KiB
C
/** @file
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I/O APIC Register Definitions from 82093AA I/O Advanced Programmable Interrupt
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Controller (IOAPIC), 1996.
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Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __IO_APIC_H__
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#define __IO_APIC_H__
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///
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/// I/O APIC Register Offsets
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///
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#define IOAPIC_INDEX_OFFSET 0x00
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#define IOAPIC_DATA_OFFSET 0x10
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///
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/// I/O APIC Indirect Register Indexes
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///
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#define IO_APIC_IDENTIFICATION_REGISTER_INDEX 0x00
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#define IO_APIC_VERSION_REGISTER_INDEX 0x01
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#define IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX 0x10
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///
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/// I/O APIC Interrupt Deliver Modes
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///
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#define IO_APIC_DELIVERY_MODE_FIXED 0
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#define IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
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#define IO_APIC_DELIVERY_MODE_SMI 2
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#define IO_APIC_DELIVERY_MODE_NMI 4
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#define IO_APIC_DELIVERY_MODE_INIT 5
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#define IO_APIC_DELIVERY_MODE_EXTINT 7
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#pragma pack(1)
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typedef union {
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struct {
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UINT32 Reserved0:24;
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UINT32 Identification:4;
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UINT32 Reserved1:4;
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} Bits;
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UINT32 Uint32;
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} IO_APIC_IDENTIFICATION_REGISTER;
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typedef union {
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struct {
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UINT32 Version:8;
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UINT32 Reserved0:8;
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UINT32 MaximumRedirectionEntry:8;
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UINT32 Reserved1:8;
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} Bits;
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UINT32 Uint32;
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} IO_APIC_VERSION_REGISTER;
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typedef union {
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struct {
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UINT32 Vector: 8;
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UINT32 DeliveryMode: 3;
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UINT32 DestinationMode: 1;
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UINT32 DeliveryStatus: 1;
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UINT32 Polarity: 1;
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UINT32 RemoteIRR: 1;
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UINT32 TriggerMode: 1;
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UINT32 Mask: 1;
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UINT32 Reserved0: 15;
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UINT32 Reserved1: 24;
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UINT32 DestinationID: 8;
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} Bits;
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struct {
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UINT32 Low;
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UINT32 High;
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} Uint32;
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UINT64 Uint64;
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} IO_APIC_REDIRECTION_TABLE_ENTRY;
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#pragma pack()
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#endif
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