mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-11-13 10:04:04 +01:00
254 lines
8.5 KiB
C
254 lines
8.5 KiB
C
/*
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* File: HdaRegisters.h
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*
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* Copyright (c) 2018 John Davis
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _EFI_HDA_REGS_H__
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#define _EFI_HDA_REGS_H__
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#include <Uefi.h>
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//
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// Global Capabilities, Status, and Control.
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//
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// Global Capabilities; 2 bytes.
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#define HDA_REG_GCAP 0x00
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#define HDA_REG_GCAP_64OK BIT0
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#define HDA_REG_GCAP_NSDO(a) ((UINT8)((a >> 1) & 0x3))
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#define HDA_REG_GCAP_BSS(a) ((UINT8)((a >> 3) & 0x1F))
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#define HDA_REG_GCAP_ISS(a) ((UINT8)((a >> 8) & 0xF))
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#define HDA_REG_GCAP_OSS(a) ((UINT8)((a >> 12) & 0xF))
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// Minor Version; 1 byte.
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#define HDA_REG_VMIN 0x02
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// Major Version; 1 byte.
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#define HDA_REG_VMAJ 0x03
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// Output Payload Capability; 2 bytes.
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#define HDA_REG_OUTPAY 0x04
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// Input Payload Capability; 2 bytes.
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#define HDA_REG_INPAY 0x06
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// Global Control; 4 bytes.
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#define HDA_REG_GCTL 0x08
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#define HDA_REG_GCTL_CRST BIT0
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#define HDA_REG_GCTL_FCNTRL BIT1
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#define HDA_REG_GCTL_UNSOL BIT8
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// Wake Enable; 2 bytes.
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#define HDA_REG_WAKEEN 0x0C
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// State Change Status; 2 bytes.
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#define HDA_REG_STATESTS 0x0E
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#define HDA_REG_STATESTS_INDEX(i) ((UINT16)(1 << (i)))
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#define HDA_REG_STATESTS_CLEAR 0xEFFF
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// Global Status; 2 bytes
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#define HDA_REG_GSTS 0x10
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#define HDA_REG_GSTS_FSTS BIT1
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// Output Stream Payload Capability; 2 bytes.
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#define HDA_REG_OUTSTRMPAY 0x18
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// Input Stream Payload Capability; 2 bytes.
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#define HDA_REG_INSTRMPAY 0x1A
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//
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// Interrupt Status and Control.
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//
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// Interrupt Control; 4 bytes.
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#define HDA_REG_INTCTL 0x20
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// Interrupt Status; 4 bytes.
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#define HDA_REG_INTSTS 0x24
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// Wall Clock Counter; 4 bytes.
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#define HDA_REG_WALLCLOCK 0x30
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// Stream Synchronization; 4 bytes.
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#define HDA_REG_SSYNC 0x38
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// CORB Lower Base Address; 4 bytes.
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#define HDA_REG_CORBLBASE 0x40
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// CORB Upper Base Address; 4 bytes.
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#define HDA_REG_CORBUBASE 0x44
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// CORB Write Pointer; 2 bytes.
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#define HDA_REG_CORBWP 0x48
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// CORB Read Pointer; 2 bytes.
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#define HDA_REG_CORBRP 0x4A
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#define HDA_REG_CORBRP_RP(a) ((UINT8)a)
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#define HDA_REG_CORBRP_RST BIT15
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// CORB Control; 1 byte.
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#define HDA_REG_CORBCTL 0x4C
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#define HDA_REG_CORBCTL_CMEIE BIT0
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#define HDA_REG_CORBCTL_CORBRUN BIT1
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// CORB Status; 1 byte.
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#define HDA_REG_CORBSTS 0x4D
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#define HDA_REG_CORBSTS_CMEI BIT0
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// CORB Size; 1 byte.
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#define HDA_REG_CORBSIZE 0x4E
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#define HDA_REG_CORBSIZE_MASK (BIT0 | BIT1)
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#define HDA_REG_CORBSIZE_ENT2 0 // 8 B = 2 entries.
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#define HDA_REG_CORBSIZE_ENT16 BIT0 // 64 B = 16 entries.
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#define HDA_REG_CORBSIZE_ENT256 BIT1 // 1 KB = 256 entries.
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#define HDA_REG_CORBSIZE_CORBSZCAP_2 BIT4 // 8 B = 2 entries.
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#define HDA_REG_CORBSIZE_CORBSZCAP_16 BIT5 // 64 B = 16 entries.
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#define HDA_REG_CORBSIZE_CORBSZCAP_256 BIT6 // 1 KB = 256 entries.
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// RIRB Lower Base Address; 4 bytes.
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#define HDA_REG_RIRBLBASE 0x50
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// RIRB Upper Base Address; 4 bytes.
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#define HDA_REG_RIRBUBASE 0x54
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// RIRB Write Pointer; 2 bytes.
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#define HDA_REG_RIRBWP 0x58
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#define HDA_REG_RIRBWP_WP(a) ((UINT8)a)
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#define HDA_REG_RIRBWP_RST BIT15
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// Response Interrupt Count; 2 bytes.
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#define HDA_REG_RINTCNT 0x5A
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// RIRB Control; 1 byte.
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#define HDA_REG_RIRBCTL 0x5C
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#define HDA_REG_RIRBCTL_RINTCTL BIT0
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#define HDA_REG_RIRBCTL_RIRBDMAEN BIT1
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#define HDA_REG_RIRBCTL_RIRBOIC BIT2
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// RIRB Status; 1 byte.
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#define HDA_REG_RIRBSTS 0x5D
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#define HDA_REG_RIRBSTS_RINTFL BIT0
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#define HDA_REG_RIRBSTS_RIRBOIS BIT2
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// RIRB Size; 1 byte.
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#define HDA_REG_RIRBSIZE 0x5E
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#define HDA_REG_RIRBSIZE_MASK (BIT0 | BIT1)
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#define HDA_REG_RIRBSIZE_ENT2 0 // 16 B = 2 entries.
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#define HDA_REG_RIRBSIZE_ENT16 BIT0 // 128 B = 16 entries.
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#define HDA_REG_RIRBSIZE_ENT256 BIT1 // 2 KB = 256 entries.
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#define HDA_REG_RIRBSIZE_RIRBSZCAP_2 BIT4 // 16 B = 2 entries.
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#define HDA_REG_RIRBSIZE_RIRBSZCAP_16 BIT5 // 128 B = 16 entries.
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#define HDA_REG_RIRBSIZE_RIRBSZCAP_256 BIT6 // 2 KB = 256 entries.
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// DMA Position Lower Base Address; 4 bytes.
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#define HDA_REG_DPLBASE 0x70
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#define HDA_REG_DPLBASE_EN BIT0
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// DMA Position Upper Base Address; 4 bytes.
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#define HDA_REG_DPUBASE 0x74
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//
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// Immediate Command Input and Output Registers.
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//
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// Immediate Command Output Interface; 4 bytes.
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#define HDA_REG_ICOI 0x60
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// Immediate Command Input Interface; 4 bytes.
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#define HDA_REG_ICII 0x64
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// Immediate Command Status; 2 bytes.
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#define HDA_REG_ICIS 0x68
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#define HDA_REG_ICIS_ICB BIT0
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#define HDA_REG_ICIS_IRV BIT1
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#define HDA_REG_ICIS_ICV BIT2
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#define HDA_REG_ICIS_IRRUNSOL BIT3
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#define HDA_REG_ICIS_IRRADD(a) ((UINT8)((a >> 4) & 0xF))
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//
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// Stream Descriptors.
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//
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// Input/Output/Bidirectional Stream Descriptor n Control; 3 bytes.
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// Byte 1.
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#define HDA_REG_SDNCTL1(n) (0x80 + (0x20 * (n)))
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#define HDA_REG_SDNCTL1_SRST BIT0
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#define HDA_REG_SDNCTL1_RUN BIT1
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#define HDA_REG_SDNCTL1_IOCE BIT2
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#define HDA_REG_SDNCTL1_FEIE BIT3
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#define HDA_REG_SDNCTL1_DEIE BIT4
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// Byte 2.
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#define HDA_REG_SDNCTL2(n) (0x81 + (0x20 * (n)))
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// Byte 3.
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#define HDA_REG_SDNCTL3(n) (0x82 + (0x20 * (n)))
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#define HDA_REG_SDNCTL3_TP BIT2
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#define HDA_REG_SDNCTL3_DIR BIT3
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#define HDA_REG_SDNCTL3_STRM_GET(a) ((UINT8)((a >> 4) & 0xF))
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#define HDA_REG_SDNCTL3_STRM_SET(a, s) ((UINT8)(((a) & 0x0F) | (((s) & 0xF)) << 4))
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// Input/Output/Bidirectional Stream Descriptor n Status; 1 byte.
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#define HDA_REG_SDNSTS(n) (0x83 + (0x20 * (n)))
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#define HDA_REG_SDNSTS_BCIS BIT2
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#define HDA_REG_SDNSTS_FIFOE BIT3
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#define HDA_REG_SDNSTS_DESE BIT4
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#define HDA_REG_SDNSTS_FIFORDY BIT5
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// Input/Output/Bidirectional Stream Descriptor n Link Position in Buffer; 4 bytes.
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#define HDA_REG_SDNLPIB(n) (0x84 + (0x20 * (n)))
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// Input/Output/Bidirectional Stream Descriptor n Cyclic Buffer Length; 4 bytes.
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#define HDA_REG_SDNCBL(n) (0x88 + (0x20 * (n)))
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// Input/Output/Bidirectional Stream Descriptor n Last Valid Index; 2 bytes.
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#define HDA_REG_SDNLVI(n) (0x8C + (0x20 * (n)))
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// Input/Output/Bidirectional Stream Descriptor n FIFO Size; 2 bytes.
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#define HDA_REG_SDNFIFOS(n) (0x90 + (0x20 * (n)))
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// Input/Output/Bidirectional Stream Descriptor n Format; 2 bytes.
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#define HDA_REG_SDNFMT(n) (0x92 + (0x20 * (n)))
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#define HDA_REG_SDNFMT_CHAN(a) ((UINT8)((a) & 0xF))
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#define HDA_REG_SDNFMT_BITS(a) ((UINT8)(((a) >> 4) & 0x3))
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#define HDA_REG_SDNFMT_BITS_8 0x0
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#define HDA_REG_SDNFMT_BITS_16 0x1
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#define HDA_REG_SDNFMT_BITS_20 0x2
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#define HDA_REG_SDNFMT_BITS_24 0x3
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#define HDA_REG_SDNFMT_BITS_32 0x4
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#define HDA_REG_SDNFMT_DIV(a) ((UINT8)(((a) >> 8) & 0x3))
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#define HDA_REG_SDNFMT_MULT(a) ((UINT8)(((a) >> 11) & 0x3))
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#define HDA_REG_SDNFMT_BASE_44KHZ BIT14
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#define HDA_REG_SDNFMT_SET(chan, bits, div, mult, base) \
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((UINT16)(((chan) & 0xF) | (((bits) & 0x3) << 4) | (((div) & 0x3) << 8) | \
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(((mult) & 0x3) << 11) | ((base) ? HDA_REG_SDNFMT_BASE_44KHZ : 0)))
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// Input/Output/Bidirectional Stream Descriptor n BDL Pointer Lower Base Address; 4 bytes.
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#define HDA_REG_SDNBDPL(n) (0x98 + (0x20 * (n)))
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// Input/Output/Bidirectional Stream Descriptor n BDL Pointer Upper Base Address; 4 bytes.
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#define HDA_REG_SDNBDPU(n) (0x9C + (0x20 * (n)))
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// Wall Clock Counter Alias; 4 bytes.
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#define HDA_REG_WALCLKA 0x2030
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// Input/Output/Bidirectional Stream Descriptor n Link Position in Buffer Alias; 4 bytes.
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#define HDA_REG_SDNLPIBA(n) (0x2084 + (0x20 * (n)))
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#endif
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