85 lines
3.1 KiB
C
Executable File
85 lines
3.1 KiB
C
Executable File
/** @file
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Copyright (C) 2016, The HermitCrabs Lab. All rights reserved.
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All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef GENERIC_ICH_H
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#define GENERIC_ICH_H
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// GenericIchDefs Generic ICH Definitions.
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//
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// Definitions beginning with "R_" are registers.
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// Definitions beginning with "B_" are bits within registers.
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// Definitions beginning with "V_" are meaningful values of bits within the registers.
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// IchPciAddressing PCI Bus Address for ICH.
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#define PCI_BUS_NUMBER_ICH 0x00 ///< ICH is on PCI Bus 0.
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#define PCI_DEVICE_NUMBER_ICH 31 ///< ICH is Device 31.
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#define PCI_FUNCTION_NUMBER_ICH_LPC 0 ///< LPC is Function 0.
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#define PCI_FUNCTION_NUMBER_ICH_PMC 2 ///< PMC is Function 2.
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#define V_ICH_PCI_VENDOR_ID 0x8086 ///< Intel vendor-id
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// IchAcpiCntr Control for the ICH's ACPI Counter.
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#define R_ICH_ACPI_BASE 0x40
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#define B_ICH_ACPI_BASE_BAR 0x0000FF80
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#define R_ICH_ACPI_CNTL 0x44 ///< See ACPI_CNTL
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#define B_ICH_ACPI_CNTL_ACPI_EN 0x80
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#define R_ICH_BAR2_BASE 0x20
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#define B_ICH_BAR2_BASE_BAR 0x0000FFC0
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#define B_ICH_BAR2_BASE_BAR_EN 0x1
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// Pre Intel Sunrisepoint
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#define R_ICH_LPC_ACPI_BASE R_ICH_ACPI_BASE
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#define B_ICH_LPC_ACPI_BASE_BAR B_ICH_ACPI_BASE_BAR
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#define R_ICH_LPC_ACPI_CNTL R_ICH_ACPI_CNTL
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#define B_ICH_LPC_ACPI_CNTL_ACPI_EN B_ICH_ACPI_CNTL_ACPI_EN
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// Intel Sunrisepoint
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#define R_ICH_PMC_ACPI_BASE R_ICH_ACPI_BASE
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#define B_ICH_PMC_ACPI_BASE_BAR B_ICH_ACPI_BASE_BAR
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#define R_ICH_PMC_ACPI_CNTL R_ICH_ACPI_CNTL
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#define B_ICH_PMC_ACPI_CNTL_ACPI_EN B_ICH_ACPI_CNTL_ACPI_EN
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// Intel Coffee Lake
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#define R_ICH_PMC_BAR2_BASE R_ICH_BAR2_BASE
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#define B_ICH_PMC_BAR2_BASE_BAR B_ICH_BAR2_BASE_BAR
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#define B_ICH_PMC_BAR2_BASE_BAR_EN B_ICH_BAR2_BASE_BAR_EN
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// AMD Bolton (AMD Bolton Register Reference Guide 3.03)
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#define R_AMD_ACPI_MMIO_BASE 0xFED80000 ///< AcpiMMioAddr (3-268)
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#define R_AMD_ACPI_MMIO_PMIO_BASE 0x300 ///< PMIO (3-268)
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#define R_AMD_ACPI_PM_TMR_BLOCK 0x64 ///< AcpiPmTmrBlk (3-289)
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// IchAcpiTimer The ICH's ACPI Timer.
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#define R_ACPI_PM1_TMR 0x08
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#define V_ACPI_TMR_FREQUENCY 3579545
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#define V_ACPI_PM1_TMR_MAX_VAL 0x01000000 ///< The timer is 24 bit overflow.
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/// Macro to generate the PCI address of any given ICH LPC Register.
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#define PCI_ICH_LPC_ADDRESS(Register) \
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((UINTN)(PCI_LIB_ADDRESS (PCI_BUS_NUMBER_ICH, PCI_DEVICE_NUMBER_ICH, PCI_FUNCTION_NUMBER_ICH_LPC, (Register))))
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/// Macro to generate the PCI address of any given ICH PMC Register.
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#define PCI_ICH_PMC_ADDRESS(Register) \
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((UINTN)(PCI_LIB_ADDRESS (PCI_BUS_NUMBER_ICH, PCI_DEVICE_NUMBER_ICH, PCI_FUNCTION_NUMBER_ICH_PMC, (Register))))
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#endif // GENERIC_ICH_H
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