mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-12-20 15:48:18 +01:00
862 lines
30 KiB
C
862 lines
30 KiB
C
/*
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* File: HdaControllerMem.c
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*
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* Copyright (c) 2018 John Davis
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "HdaController.h"
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#include <Library/HdaRegisters.h>
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EFI_STATUS
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EFIAPI
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HdaControllerInitCorb(
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IN HDA_CONTROLLER_DEV *HdaDev)
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{
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// DEBUG((DEBUG_INFO, "HdaControllerInitCorb(): start\n"));
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// Status and PCI I/O protocol.
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EFI_STATUS Status;
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EFI_PCI_IO_PROTOCOL *PciIo = HdaDev->PciIo;
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// HDA register values.
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UINT8 HdaCorbSize;
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UINT32 HdaLowerCorbBaseAddr;
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UINT32 HdaUpperCorbBaseAddr;
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UINT16 HdaCorbWp;
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UINT16 HdaCorbRp;
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UINT64 HdaCorbRpPollResult;
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// CORB buffer.
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VOID *CorbBuffer = NULL;
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UINTN CorbLength;
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UINTN CorbLengthActual;
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VOID *CorbMapping = NULL;
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EFI_PHYSICAL_ADDRESS CorbPhysAddr;
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// Get value of CORBSIZE register.
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Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_CORBSIZE, 1, &HdaCorbSize);
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if (EFI_ERROR(Status))
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return Status;
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// Determine size of CORB.
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if (HdaCorbSize & HDA_REG_CORBSIZE_CORBSZCAP_256) {
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CorbLength = 256 * HDA_CORB_ENTRY_SIZE;
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HdaCorbSize = (HdaCorbSize & ~HDA_REG_CORBSIZE_MASK) | HDA_REG_CORBSIZE_ENT256;
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} else if (HdaCorbSize & HDA_REG_CORBSIZE_CORBSZCAP_16) {
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CorbLength = 16 * HDA_CORB_ENTRY_SIZE;
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HdaCorbSize = (HdaCorbSize & ~HDA_REG_CORBSIZE_MASK) | HDA_REG_CORBSIZE_ENT16;
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} else if (HdaCorbSize & HDA_REG_CORBSIZE_CORBSZCAP_2) {
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CorbLength = 2 * HDA_CORB_ENTRY_SIZE;
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HdaCorbSize = (HdaCorbSize & ~HDA_REG_CORBSIZE_MASK) | HDA_REG_CORBSIZE_ENT2;
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} else {
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// Unsupported size.
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return EFI_UNSUPPORTED;
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}
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// Allocate outbound buffer.
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Status = PciIo->AllocateBuffer(PciIo, AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(CorbLength), &CorbBuffer, 0);
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if (EFI_ERROR(Status))
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return Status;
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SetMem(CorbBuffer, CorbLength, 0);
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// Map outbound buffer.
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CorbLengthActual = CorbLength;
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Status = PciIo->Map(PciIo, EfiPciIoOperationBusMasterCommonBuffer, CorbBuffer, &CorbLengthActual, &CorbPhysAddr, &CorbMapping);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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if (CorbLengthActual != CorbLength) {
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Status = EFI_OUT_OF_RESOURCES;
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goto FREE_BUFFER;
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}
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// Disable CORB.
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Status = HdaControllerSetCorb(HdaDev, FALSE);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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// Set outbound buffer lower base address.
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HdaLowerCorbBaseAddr = (UINT32)CorbPhysAddr;
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Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, PCI_HDA_BAR, HDA_REG_CORBLBASE, 1, &HdaLowerCorbBaseAddr);
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// ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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// If 64-bit supported, set upper base address.
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if (HdaDev->Capabilities & HDA_REG_GCAP_64OK) {
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HdaUpperCorbBaseAddr = (UINT32)RShiftU64(CorbPhysAddr, 32);
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Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, PCI_HDA_BAR, HDA_REG_CORBUBASE, 1, &HdaUpperCorbBaseAddr);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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}
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// Reset write pointer to zero.
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HdaCorbWp = 0;
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Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint16, PCI_HDA_BAR, HDA_REG_CORBWP, 1, &HdaCorbWp);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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// Reset read pointer by setting bit.
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HdaCorbRp = HDA_REG_CORBRP_RST;
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Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint16, PCI_HDA_BAR, HDA_REG_CORBRP, 1, &HdaCorbRp);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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// Docs state we need to clear the bit and wait for it to clear.
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HdaCorbRp = 0;
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Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint16, PCI_HDA_BAR, HDA_REG_CORBRP, 1, &HdaCorbRp);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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Status = PciIo->PollMem(PciIo, EfiPciIoWidthUint16, PCI_HDA_BAR, HDA_REG_CORBRP, HDA_REG_CORBRP_RST, 0, 50000000, &HdaCorbRpPollResult);
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ASSERT_EFI_ERROR(Status);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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// Populate device object properties.
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HdaDev->CorbBuffer = CorbBuffer;
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HdaDev->CorbEntryCount = (UINT32)(CorbLength / HDA_CORB_ENTRY_SIZE);
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HdaDev->CorbMapping = CorbMapping;
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HdaDev->CorbPhysAddr = CorbPhysAddr;
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HdaDev->CorbWritePointer = HdaCorbWp;
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// Buffer allocation successful.
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DEBUG((DEBUG_INFO, "HDA controller CORB allocated @ 0x%p (0x%p) (%u entries)\n",
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HdaDev->CorbBuffer, HdaDev->CorbPhysAddr, HdaDev->CorbEntryCount));
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return EFI_SUCCESS;
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FREE_BUFFER:
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// Unmap if needed.
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if (CorbMapping)
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PciIo->Unmap(PciIo, CorbMapping);
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// Free buffer.
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PciIo->FreeBuffer(PciIo, EFI_SIZE_TO_PAGES(CorbLength), CorbBuffer);
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return Status;
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}
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EFI_STATUS
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EFIAPI
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HdaControllerCleanupCorb(
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IN HDA_CONTROLLER_DEV *HdaDev)
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{
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// DEBUG((DEBUG_INFO, "HdaControllerCleanupCorb(): start\n"));
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// Create variables.
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EFI_STATUS Status;
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EFI_PCI_IO_PROTOCOL *PciIo = HdaDev->PciIo;
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// Stop CORB.
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Status = HdaControllerSetCorb(HdaDev, FALSE);
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if (EFI_ERROR(Status))
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return Status;
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// Unmap CORB and free buffer.
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if (HdaDev->CorbMapping)
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PciIo->Unmap(PciIo, HdaDev->CorbMapping);
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PciIo->FreeBuffer(PciIo, EFI_SIZE_TO_PAGES(HdaDev->CorbEntryCount * HDA_CORB_ENTRY_SIZE), HdaDev->CorbBuffer);
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// Clear device object properties.
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HdaDev->CorbBuffer = NULL;
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HdaDev->CorbEntryCount = 0;
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HdaDev->CorbMapping = NULL;
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HdaDev->CorbPhysAddr = 0;
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HdaDev->CorbWritePointer = 0;
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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HdaControllerSetCorb(
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IN HDA_CONTROLLER_DEV *HdaDev,
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IN BOOLEAN Enable)
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{
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// DEBUG((DEBUG_INFO, "HdaControllerSetCorb(): start\n"));
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// Create variables.
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EFI_STATUS Status;
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EFI_PCI_IO_PROTOCOL *PciIo = HdaDev->PciIo;
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UINT8 HdaCorbCtl;
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UINT64 Tmp;
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// Get current value of CORBCTL.
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Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_CORBCTL, 1, &HdaCorbCtl);
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if (EFI_ERROR(Status))
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return Status;
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// Change CORB operation.
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if (Enable)
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HdaCorbCtl |= HDA_REG_CORBCTL_CORBRUN;
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else
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HdaCorbCtl &= ~HDA_REG_CORBCTL_CORBRUN;
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Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_CORBCTL, 1, &HdaCorbCtl);
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if (EFI_ERROR(Status))
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return Status;
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// Wait for bit to cycle.
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return PciIo->PollMem(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_CORBCTL, HDA_REG_CORBCTL_CORBRUN,
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Enable ? HDA_REG_CORBCTL_CORBRUN : 0, MS_TO_NANOSECOND(50), &Tmp);
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}
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EFI_STATUS
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EFIAPI
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HdaControllerInitRirb(
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IN HDA_CONTROLLER_DEV *HdaDev)
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{
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// DEBUG((DEBUG_INFO, "HdaControllerInitRirb(): start\n"));
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// Status and PCI I/O protocol.
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EFI_STATUS Status;
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EFI_PCI_IO_PROTOCOL *PciIo = HdaDev->PciIo;
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// HDA register values.
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UINT8 HdaRirbSize;
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UINT32 HdaLowerRirbBaseAddr;
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UINT32 HdaUpperRirbBaseAddr;
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UINT16 HdaRirbWp;
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// RIRB buffer.
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VOID *RirbBuffer = NULL;
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UINTN RirbLength;
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UINTN RirbLengthActual;
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VOID *RirbMapping = NULL;
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EFI_PHYSICAL_ADDRESS RirbPhysAddr;
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// Get value of RIRBSIZE register.
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Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_RIRBSIZE, 1, &HdaRirbSize);
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if (EFI_ERROR(Status))
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return Status;
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// Determine size of RIRB.
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if (HdaRirbSize & HDA_REG_RIRBSIZE_RIRBSZCAP_256) {
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RirbLength = 256 * HDA_RIRB_ENTRY_SIZE;
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HdaRirbSize = (HdaRirbSize & ~HDA_REG_RIRBSIZE_MASK) | HDA_REG_RIRBSIZE_ENT256;
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} else if (HdaRirbSize & HDA_REG_RIRBSIZE_RIRBSZCAP_16) {
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RirbLength = 16 * HDA_RIRB_ENTRY_SIZE;
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HdaRirbSize = (HdaRirbSize & ~HDA_REG_RIRBSIZE_MASK) | HDA_REG_RIRBSIZE_ENT16;
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} else if (HdaRirbSize & HDA_REG_RIRBSIZE_RIRBSZCAP_2) {
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RirbLength = 2 * HDA_RIRB_ENTRY_SIZE;
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HdaRirbSize = (HdaRirbSize & ~HDA_REG_RIRBSIZE_MASK) | HDA_REG_RIRBSIZE_ENT2;
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} else {
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// Unsupported size.
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return EFI_UNSUPPORTED;
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}
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// Allocate outbound buffer.
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Status = PciIo->AllocateBuffer(PciIo, AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(RirbLength), &RirbBuffer, 0);
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if (EFI_ERROR(Status))
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return Status;
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ZeroMem(RirbBuffer, RirbLength);
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// Map outbound buffer.
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RirbLengthActual = RirbLength;
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Status = PciIo->Map(PciIo, EfiPciIoOperationBusMasterCommonBuffer, RirbBuffer, &RirbLengthActual, &RirbPhysAddr, &RirbMapping);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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if (RirbLengthActual != RirbLength) {
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Status = EFI_OUT_OF_RESOURCES;
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goto FREE_BUFFER;
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}
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// Disable RIRB.
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Status = HdaControllerSetRirb(HdaDev, FALSE);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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// Set outbound buffer lower base address.
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HdaLowerRirbBaseAddr = (UINT32)RirbPhysAddr;
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Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, PCI_HDA_BAR, HDA_REG_RIRBLBASE, 1, &HdaLowerRirbBaseAddr);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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// If 64-bit supported, set upper base address.
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if (HdaDev->Capabilities & HDA_REG_GCAP_64OK) {
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HdaUpperRirbBaseAddr = (UINT32)(RirbPhysAddr >> 32);
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Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, PCI_HDA_BAR, HDA_REG_RIRBUBASE, 1, &HdaUpperRirbBaseAddr);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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}
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// Reset write pointer by setting reset bit.
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Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint16, PCI_HDA_BAR, HDA_REG_RIRBWP, 1, &HdaRirbWp);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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HdaRirbWp |= HDA_REG_RIRBWP_RST;
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Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint16, PCI_HDA_BAR, HDA_REG_RIRBWP, 1, &HdaRirbWp);
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if (EFI_ERROR(Status))
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goto FREE_BUFFER;
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// Populate device object properties.
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HdaDev->RirbBuffer = RirbBuffer;
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HdaDev->RirbEntryCount = (UINT32)(RirbLength / HDA_RIRB_ENTRY_SIZE);
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HdaDev->RirbMapping = RirbMapping;
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HdaDev->RirbPhysAddr = RirbPhysAddr;
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HdaDev->RirbReadPointer = 0;
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// Buffer allocation successful.
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DEBUG((DEBUG_INFO, "HDA controller RIRB allocated @ 0x%p (0x%p) (%u entries)\n",
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HdaDev->RirbBuffer, HdaDev->RirbPhysAddr, HdaDev->RirbEntryCount));
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return EFI_SUCCESS;
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FREE_BUFFER:
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// Unmap if needed.
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if (RirbMapping)
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PciIo->Unmap(PciIo, RirbMapping);
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// Free buffer.
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PciIo->FreeBuffer(PciIo, EFI_SIZE_TO_PAGES(RirbLength), RirbBuffer);
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return Status;
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}
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EFI_STATUS
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EFIAPI
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HdaControllerCleanupRirb(
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IN HDA_CONTROLLER_DEV *HdaDev)
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{
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// DEBUG((DEBUG_INFO, "HdaControllerCleanupRirb(): start\n"));
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// Create variables.
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EFI_STATUS Status;
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EFI_PCI_IO_PROTOCOL *PciIo = HdaDev->PciIo;
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// Stop RIRB.
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Status = HdaControllerSetRirb(HdaDev, FALSE);
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if (EFI_ERROR(Status))
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return Status;
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// Unmap RIRB and free buffer.
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if (HdaDev->RirbMapping)
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PciIo->Unmap(PciIo, HdaDev->RirbMapping);
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PciIo->FreeBuffer(PciIo, EFI_SIZE_TO_PAGES(HdaDev->RirbEntryCount * HDA_RIRB_ENTRY_SIZE), HdaDev->RirbBuffer);
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// Clear device object properties.
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HdaDev->RirbBuffer = NULL;
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HdaDev->RirbEntryCount = 0;
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HdaDev->RirbMapping = NULL;
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HdaDev->RirbPhysAddr = 0;
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HdaDev->RirbReadPointer = 0;
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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HdaControllerSetRirb(
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IN HDA_CONTROLLER_DEV *HdaDev,
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IN BOOLEAN Enable)
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{
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// DEBUG((DEBUG_INFO, "HdaControllerSetRirb(): start\n"));
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// Create variables.
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EFI_STATUS Status;
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EFI_PCI_IO_PROTOCOL *PciIo = HdaDev->PciIo;
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UINT8 HdaRirbCtl;
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UINT64 Tmp;
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// Get current value of RIRBCTL.
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Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_RIRBCTL, 1, &HdaRirbCtl);
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if (EFI_ERROR(Status))
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return Status;
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// Change RIRB operation.
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if (Enable)
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HdaRirbCtl |= HDA_REG_RIRBCTL_RIRBDMAEN;
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else
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HdaRirbCtl &= ~HDA_REG_RIRBCTL_RIRBDMAEN;
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Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_RIRBCTL, 1, &HdaRirbCtl);
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if (EFI_ERROR(Status))
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return Status;
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// Wait for bit to cycle.
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return PciIo->PollMem(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_RIRBCTL, HDA_REG_RIRBCTL_RIRBDMAEN,
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Enable ? HDA_REG_RIRBCTL_RIRBDMAEN : 0, MS_TO_NANOSECOND(50), &Tmp);
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}
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EFI_STATUS
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EFIAPI
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HdaControllerInitStreams(
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IN HDA_CONTROLLER_DEV *HdaControllerDev)
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{
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// DEBUG((DEBUG_INFO, "HdaControllerInitStreams(): start\n"));
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// Status and PCI I/O protocol.
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EFI_STATUS Status;
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EFI_PCI_IO_PROTOCOL *PciIo = HdaControllerDev->PciIo;
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UINT32 LowerBaseAddr;
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UINT32 UpperBaseAddr;
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EFI_PHYSICAL_ADDRESS DataBlockAddr;
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HDA_STREAM *HdaStream;
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UINT8 i;
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UINT8 InputStreamsOffset;
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UINT8 OutputStreamsOffset;
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// Buffers.
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UINTN BdlLengthActual;
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UINTN DataLengthActual;
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UINTN DmaPositionsLengthActual;
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// Reset stream ID bitmap so stream 0 is allocated (reserved).
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HdaControllerDev->StreamIdMapping = BIT0;
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// Determine number of streams.
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HdaControllerDev->BidirStreamsCount = HDA_REG_GCAP_BSS(HdaControllerDev->Capabilities);
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HdaControllerDev->InputStreamsCount = HDA_REG_GCAP_ISS(HdaControllerDev->Capabilities);
|
|
HdaControllerDev->OutputStreamsCount = HDA_REG_GCAP_OSS(HdaControllerDev->Capabilities);
|
|
HdaControllerDev->TotalStreamsCount = HdaControllerDev->BidirStreamsCount +
|
|
HdaControllerDev->InputStreamsCount + HdaControllerDev->OutputStreamsCount;
|
|
|
|
// Initialize stream arrays.
|
|
HdaControllerDev->BidirStreams = AllocateZeroPool(sizeof(HDA_STREAM) * HdaControllerDev->BidirStreamsCount);
|
|
HdaControllerDev->InputStreams = AllocateZeroPool(sizeof(HDA_STREAM) * HdaControllerDev->InputStreamsCount);
|
|
HdaControllerDev->OutputStreams = AllocateZeroPool(sizeof(HDA_STREAM) * HdaControllerDev->OutputStreamsCount);
|
|
|
|
// Initialize streams.
|
|
InputStreamsOffset = HdaControllerDev->BidirStreamsCount;
|
|
OutputStreamsOffset = InputStreamsOffset + HdaControllerDev->InputStreamsCount;
|
|
// DEBUG((DEBUG_INFO, "HdaControllerInitStreams(): in offset %u, out offset %u\n", InputStreamsOffset, OutputStreamsOffset));
|
|
for (i = 0; i < HdaControllerDev->TotalStreamsCount; i++) {
|
|
// Get pointer to stream and set type.
|
|
if (i < InputStreamsOffset) {
|
|
HdaStream = HdaControllerDev->BidirStreams + i;
|
|
HdaStream->Type = HDA_STREAM_TYPE_BIDIR;
|
|
} else if (i < OutputStreamsOffset) {
|
|
HdaStream = HdaControllerDev->InputStreams + (i - InputStreamsOffset);
|
|
HdaStream->Type = HDA_STREAM_TYPE_IN;
|
|
} else {
|
|
HdaStream = HdaControllerDev->OutputStreams + (i - OutputStreamsOffset);
|
|
HdaStream->Type = HDA_STREAM_TYPE_OUT;
|
|
}
|
|
|
|
// Set parent controller and index.
|
|
HdaStream->HdaControllerDev = HdaControllerDev;
|
|
HdaStream->Index = i;
|
|
HdaStream->Output = (HdaStream->Type == HDA_STREAM_TYPE_OUT);
|
|
|
|
// Initialize polling timer.
|
|
Status = gBS->CreateEvent(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_NOTIFY,
|
|
(EFI_EVENT_NOTIFY)HdaControllerStreamPollTimerHandler, HdaStream, &HdaStream->PollTimer);
|
|
if (EFI_ERROR(Status))
|
|
goto FREE_BUFFER;
|
|
|
|
// Allocate buffer descriptor list.
|
|
Status = PciIo->AllocateBuffer(PciIo, AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(HDA_BDL_SIZE),
|
|
(VOID**)&HdaStream->BufferList, 0);
|
|
if (EFI_ERROR(Status))
|
|
goto FREE_BUFFER;
|
|
SetMem(HdaStream->BufferList, HDA_BDL_SIZE, 0);
|
|
|
|
// Map buffer descriptor list.
|
|
BdlLengthActual = HDA_BDL_SIZE;
|
|
Status = PciIo->Map(PciIo, EfiPciIoOperationBusMasterCommonBuffer, HdaStream->BufferList, &BdlLengthActual,
|
|
&HdaStream->BufferListPhysAddr, &HdaStream->BufferListMapping);
|
|
if (EFI_ERROR(Status))
|
|
goto FREE_BUFFER;
|
|
if (BdlLengthActual != HDA_BDL_SIZE) {
|
|
Status = EFI_OUT_OF_RESOURCES;
|
|
goto FREE_BUFFER;
|
|
}
|
|
|
|
// Reset stream.
|
|
Status = HdaControllerResetStream(HdaStream);
|
|
if (EFI_ERROR(Status))
|
|
goto FREE_BUFFER;
|
|
|
|
// Allocate buffer for data.
|
|
Status = PciIo->AllocateBuffer(PciIo, AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(HDA_STREAM_BUF_SIZE),
|
|
(VOID**)&HdaStream->BufferData, 0);
|
|
if (EFI_ERROR(Status))
|
|
goto FREE_BUFFER;
|
|
SetMem(HdaStream->BufferData, HDA_STREAM_BUF_SIZE, 0);
|
|
|
|
// Map buffer descriptor list.
|
|
DataLengthActual = HDA_STREAM_BUF_SIZE;
|
|
Status = PciIo->Map(PciIo, EfiPciIoOperationBusMasterCommonBuffer, HdaStream->BufferData, &DataLengthActual,
|
|
&HdaStream->BufferDataPhysAddr, &HdaStream->BufferDataMapping);
|
|
if (EFI_ERROR(Status))
|
|
goto FREE_BUFFER;
|
|
if (DataLengthActual != HDA_STREAM_BUF_SIZE) {
|
|
Status = EFI_OUT_OF_RESOURCES;
|
|
goto FREE_BUFFER;
|
|
}
|
|
|
|
// Fill buffer list.
|
|
for (UINTN b = 0; b < HDA_BDL_ENTRY_COUNT; b++) {
|
|
// Set address and length of entry.
|
|
DataBlockAddr = HdaStream->BufferDataPhysAddr + (b * HDA_BDL_BLOCKSIZE);
|
|
HdaStream->BufferList[b].Address = (UINT32)DataBlockAddr;
|
|
HdaStream->BufferList[b].AddressHigh = (UINT32)(DataBlockAddr >> 32);
|
|
HdaStream->BufferList[b].Length = HDA_BDL_BLOCKSIZE;
|
|
HdaStream->BufferList[b].InterruptOnCompletion = TRUE;
|
|
}
|
|
}
|
|
|
|
// Allocate space for DMA positions structure.
|
|
HdaControllerDev->DmaPositionsSize = sizeof(HDA_DMA_POS_ENTRY) * HdaControllerDev->TotalStreamsCount;
|
|
Status = PciIo->AllocateBuffer(PciIo, AllocateAnyPages, EfiBootServicesData,
|
|
EFI_SIZE_TO_PAGES(HdaControllerDev->DmaPositionsSize), (VOID**)&HdaControllerDev->DmaPositions, 0);
|
|
if (EFI_ERROR(Status))
|
|
goto FREE_BUFFER;
|
|
SetMem(HdaControllerDev->DmaPositions, HdaControllerDev->DmaPositionsSize, 0);
|
|
|
|
// Map buffer descriptor list.
|
|
DmaPositionsLengthActual = HdaControllerDev->DmaPositionsSize;
|
|
Status = PciIo->Map(PciIo, EfiPciIoOperationBusMasterCommonBuffer, HdaControllerDev->DmaPositions,
|
|
&DmaPositionsLengthActual, &HdaControllerDev->DmaPositionsPhysAddr, &HdaControllerDev->DmaPositionsMapping);
|
|
if (EFI_ERROR(Status))
|
|
goto FREE_BUFFER;
|
|
if (DmaPositionsLengthActual != HdaControllerDev->DmaPositionsSize) {
|
|
Status = EFI_OUT_OF_RESOURCES;
|
|
goto FREE_BUFFER;
|
|
}
|
|
|
|
// Set DMA positions lower base address.
|
|
LowerBaseAddr = ((UINT32)HdaControllerDev->DmaPositionsPhysAddr) | HDA_REG_DPLBASE_EN;
|
|
Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, PCI_HDA_BAR, HDA_REG_DPLBASE, 1, &LowerBaseAddr);
|
|
if (EFI_ERROR(Status))
|
|
goto FREE_BUFFER;
|
|
|
|
// If 64-bit supported, set DMA positions upper base address.
|
|
if (HdaControllerDev->Capabilities & HDA_REG_GCAP_64OK) {
|
|
UpperBaseAddr = (UINT32)RShiftU64(HdaControllerDev->DmaPositionsPhysAddr, 32);
|
|
Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, PCI_HDA_BAR, HDA_REG_DPUBASE, 1, &UpperBaseAddr);
|
|
if (EFI_ERROR(Status))
|
|
goto FREE_BUFFER;
|
|
}
|
|
|
|
// Success.
|
|
return EFI_SUCCESS;
|
|
|
|
FREE_BUFFER:
|
|
// Free stream arrays. TODO
|
|
FreePool(HdaControllerDev->BidirStreams);
|
|
FreePool(HdaControllerDev->InputStreams);
|
|
FreePool(HdaControllerDev->OutputStreams);
|
|
return Status;
|
|
}
|
|
|
|
EFI_STATUS
|
|
EFIAPI
|
|
HdaControllerResetStream(
|
|
IN HDA_STREAM *HdaStream)
|
|
{
|
|
// Create variables.
|
|
EFI_STATUS Status;
|
|
EFI_PCI_IO_PROTOCOL *PciIo;
|
|
UINT32 LowerBaseAddr;
|
|
UINT32 UpperBaseAddr;
|
|
UINT64 Tmp;
|
|
|
|
// Stream regs.
|
|
UINT8 HdaStreamCtl1 = 0;
|
|
UINT16 StreamLvi;
|
|
UINT32 StreamCbl;
|
|
|
|
if (!HdaStream || !HdaStream->HdaControllerDev)
|
|
return EFI_INVALID_PARAMETER;
|
|
|
|
PciIo = HdaStream->HdaControllerDev->PciIo;
|
|
|
|
// Disable stream.
|
|
Status = HdaControllerSetStreamId(HdaStream, 0);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
|
|
// Get value of control register.
|
|
Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_SDNCTL1(HdaStream->Index), 1, &HdaStreamCtl1);
|
|
// ASSERT_EFI_ERROR(Status);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
|
|
// Reset stream and wait for bit to be set.
|
|
HdaStreamCtl1 |= HDA_REG_SDNCTL1_SRST;
|
|
Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_SDNCTL1(HdaStream->Index), 1, &HdaStreamCtl1);
|
|
// ASSERT_EFI_ERROR(Status);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
Status = PciIo->PollMem(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_SDNCTL1(HdaStream->Index),
|
|
HDA_REG_SDNCTL1_SRST, HDA_REG_SDNCTL1_SRST, MS_TO_NANOSECOND(100), &Tmp);
|
|
// ASSERT_EFI_ERROR(Status);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
|
|
// Get value of control register.
|
|
Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_SDNCTL1(HdaStream->Index), 1, &HdaStreamCtl1);
|
|
// ASSERT_EFI_ERROR(Status);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
|
|
// Docs state we need to clear the bit and wait for it to clear.
|
|
HdaStreamCtl1 &= ~HDA_REG_SDNCTL1_SRST;
|
|
Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_SDNCTL1(HdaStream->Index), 1, &HdaStreamCtl1);
|
|
// ASSERT_EFI_ERROR(Status);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
Status = PciIo->PollMem(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_SDNCTL1(HdaStream->Index),
|
|
HDA_REG_SDNCTL1_SRST, 0, MS_TO_NANOSECOND(100), &Tmp);
|
|
// ASSERT_EFI_ERROR(Status);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
|
|
// Set buffer list lower base address.
|
|
LowerBaseAddr = (UINT32)HdaStream->BufferListPhysAddr;
|
|
Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, PCI_HDA_BAR, HDA_REG_SDNBDPL(HdaStream->Index), 1, &LowerBaseAddr);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
|
|
// If 64-bit supported, set buffer list upper base address.
|
|
if (HdaStream->HdaControllerDev->Capabilities & HDA_REG_GCAP_64OK) {
|
|
UpperBaseAddr = (UINT32)RShiftU64(HdaStream->BufferListPhysAddr, 32);
|
|
Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, PCI_HDA_BAR, HDA_REG_SDNBDPU(HdaStream->Index), 1, &UpperBaseAddr);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
}
|
|
|
|
// Set last valid index (LVI).
|
|
StreamLvi = HDA_BDL_ENTRY_LAST;
|
|
Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint16, PCI_HDA_BAR, HDA_REG_SDNLVI(HdaStream->Index), 1, &StreamLvi);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
|
|
// Set total buffer length.
|
|
StreamCbl = HDA_STREAM_BUF_SIZE;
|
|
Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, PCI_HDA_BAR, HDA_REG_SDNCBL(HdaStream->Index), 1, &StreamCbl);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
VOID
|
|
EFIAPI
|
|
HdaControllerCleanupStreams(
|
|
IN HDA_CONTROLLER_DEV *HdaControllerDev)
|
|
{
|
|
// DEBUG((DEBUG_INFO, "HdaControllerInitStreams(): start\n"));
|
|
|
|
// Status and PCI I/O protocol.
|
|
EFI_PCI_IO_PROTOCOL *PciIo = HdaControllerDev->PciIo;
|
|
UINT8 InputStreamsOffset = HdaControllerDev->BidirStreamsCount;
|
|
UINT8 OutputStreamsOffset = InputStreamsOffset + HdaControllerDev->InputStreamsCount;
|
|
HDA_STREAM *HdaStream;
|
|
UINT32 Tmp;
|
|
UINT8 i;
|
|
|
|
// Clean streams.
|
|
for (i = 0; i < HdaControllerDev->TotalStreamsCount; i++) {
|
|
// Get pointer to stream and set type.
|
|
if (i < InputStreamsOffset) {
|
|
HdaStream = HdaControllerDev->BidirStreams + i;
|
|
HdaStream->Type = HDA_STREAM_TYPE_BIDIR;
|
|
} else if (i < OutputStreamsOffset) {
|
|
HdaStream = HdaControllerDev->InputStreams + (i - InputStreamsOffset);
|
|
HdaStream->Type = HDA_STREAM_TYPE_IN;
|
|
} else {
|
|
HdaStream = HdaControllerDev->OutputStreams + (i - OutputStreamsOffset);
|
|
HdaStream->Type = HDA_STREAM_TYPE_OUT;
|
|
}
|
|
|
|
// Close polling timer.
|
|
gBS->CloseEvent(HdaStream->PollTimer);
|
|
|
|
// Stop stream.
|
|
HdaControllerSetStreamId(HdaStream, 0);
|
|
|
|
// Unmap and free buffer descriptor list.
|
|
if (HdaStream->BufferListMapping != NULL)
|
|
PciIo->Unmap(PciIo, HdaStream->BufferListMapping);
|
|
if (HdaStream->BufferList != NULL)
|
|
PciIo->FreeBuffer(PciIo, EFI_SIZE_TO_PAGES(HDA_BDL_SIZE), HdaStream->BufferList);
|
|
|
|
// Unmap and free data buffer.
|
|
if (HdaStream->BufferDataMapping != NULL)
|
|
PciIo->Unmap(PciIo, HdaStream->BufferDataMapping);
|
|
if (HdaStream->BufferData != NULL)
|
|
PciIo->FreeBuffer(PciIo, EFI_SIZE_TO_PAGES(HDA_STREAM_BUF_SIZE), HdaStream->BufferData);
|
|
}
|
|
|
|
// Clear DMA positions structure base address.
|
|
Tmp = 0;
|
|
PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, PCI_HDA_BAR, HDA_REG_DPLBASE, 1, &Tmp);
|
|
if (HdaControllerDev->Capabilities & HDA_REG_GCAP_64OK) {
|
|
Tmp = 0;
|
|
PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, PCI_HDA_BAR, HDA_REG_DPUBASE, 1, &Tmp);
|
|
}
|
|
|
|
// Unmap and free DMA positions structure.
|
|
if (HdaControllerDev->DmaPositionsMapping != NULL)
|
|
PciIo->Unmap(PciIo, HdaControllerDev->DmaPositionsMapping);
|
|
if (HdaControllerDev->DmaPositions != NULL)
|
|
PciIo->FreeBuffer(PciIo, EFI_SIZE_TO_PAGES(HdaControllerDev->DmaPositionsSize), HdaControllerDev->DmaPositions);
|
|
}
|
|
|
|
EFI_STATUS
|
|
EFIAPI
|
|
HdaControllerGetStream(
|
|
IN HDA_STREAM *HdaStream,
|
|
OUT BOOLEAN *Run)
|
|
{
|
|
//DEBUG((DEBUG_INFO, "HdaControllerGetStream(%u): start\n", HdaStream->Index));
|
|
|
|
// Create variables.
|
|
EFI_STATUS Status;
|
|
EFI_PCI_IO_PROTOCOL *PciIo;
|
|
UINT8 HdaStreamCtl1 = 0;
|
|
|
|
if (!Run || !HdaStream || !HdaStream->HdaControllerDev)
|
|
return EFI_INVALID_PARAMETER;
|
|
|
|
PciIo = HdaStream->HdaControllerDev->PciIo;
|
|
|
|
// Get current value of register.
|
|
Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_SDNCTL1(HdaStream->Index), 1, &HdaStreamCtl1);
|
|
// if (EFI_ERROR(Status))
|
|
// return Status;
|
|
|
|
// Success.
|
|
*Run = (HdaStreamCtl1 & HDA_REG_SDNCTL1_RUN) != 0;
|
|
return Status;
|
|
}
|
|
|
|
EFI_STATUS
|
|
EFIAPI
|
|
HdaControllerSetStream(
|
|
IN HDA_STREAM *HdaStream,
|
|
IN BOOLEAN Run)
|
|
{
|
|
// DEBUG((DEBUG_INFO, "HdaControllerSetStream(%u, %u): start\n", HdaStream->Index, Run));
|
|
|
|
// Create variables.
|
|
EFI_STATUS Status;
|
|
EFI_PCI_IO_PROTOCOL *PciIo;
|
|
UINT8 HdaStreamCtl1 = 0;
|
|
UINT64 Tmp = 0;
|
|
|
|
if (!HdaStream || !HdaStream->HdaControllerDev)
|
|
return EFI_INVALID_PARAMETER;
|
|
|
|
PciIo = HdaStream->HdaControllerDev->PciIo;
|
|
|
|
// Get current value of register.
|
|
Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_SDNCTL1(HdaStream->Index), 1, &HdaStreamCtl1);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
|
|
// Update stream operation.
|
|
if (Run)
|
|
HdaStreamCtl1 |= HDA_REG_SDNCTL1_RUN;
|
|
else
|
|
HdaStreamCtl1 &= ~HDA_REG_SDNCTL1_RUN;
|
|
|
|
// Write register.
|
|
Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_SDNCTL1(HdaStream->Index), 1, &HdaStreamCtl1);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
|
|
// Wait for bit to be set or cleared.
|
|
Status = PciIo->PollMem(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_SDNCTL1(HdaStream->Index),
|
|
HDA_REG_SDNCTL1_RUN, HdaStreamCtl1 & HDA_REG_SDNCTL1_RUN, MS_TO_NANOSECOND(10), &Tmp);
|
|
return Status;
|
|
}
|
|
|
|
EFI_STATUS
|
|
EFIAPI
|
|
HdaControllerGetStreamLinkPos(
|
|
IN HDA_STREAM *HdaStream,
|
|
OUT UINT32 *Position)
|
|
{
|
|
EFI_PCI_IO_PROTOCOL *PciIo;
|
|
|
|
if (!Position || !HdaStream || !HdaStream->HdaControllerDev)
|
|
return EFI_INVALID_PARAMETER;
|
|
//DEBUG((DEBUG_INFO, "HdaControllerGetStreamLinkPos(%u): start\n", HdaStream->Index));
|
|
|
|
// Get current value of register.
|
|
PciIo = HdaStream->HdaControllerDev->PciIo;
|
|
return PciIo->Mem.Read(PciIo, EfiPciIoWidthUint32, PCI_HDA_BAR, HDA_REG_SDNLPIB(HdaStream->Index), 1, Position);
|
|
}
|
|
|
|
EFI_STATUS
|
|
EFIAPI
|
|
HdaControllerGetStreamId(
|
|
IN HDA_STREAM *HdaStream,
|
|
OUT UINT8 *Index)
|
|
{
|
|
// Create variables.
|
|
EFI_STATUS Status;
|
|
EFI_PCI_IO_PROTOCOL *PciIo;
|
|
UINT8 HdaStreamCtl3 = 0;
|
|
|
|
if (!Index || !HdaStream || !HdaStream->HdaControllerDev)
|
|
return EFI_INVALID_PARAMETER;
|
|
//DEBUG((DEBUG_INFO, "HdaControllerGetStreamId(%u): start\n", HdaStream->Index));
|
|
PciIo = HdaStream->HdaControllerDev->PciIo;
|
|
|
|
// Get current value of register.
|
|
Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_SDNCTL3(HdaStream->Index), 1, &HdaStreamCtl3);
|
|
// if (EFI_ERROR(Status))
|
|
// return Status;
|
|
|
|
// Update stream index.
|
|
*Index = HDA_REG_SDNCTL3_STRM_GET(HdaStreamCtl3);
|
|
return Status;
|
|
}
|
|
|
|
EFI_STATUS
|
|
EFIAPI
|
|
HdaControllerSetStreamId(
|
|
IN HDA_STREAM *HdaStream,
|
|
IN UINT8 Index)
|
|
{
|
|
EFI_STATUS Status;
|
|
EFI_PCI_IO_PROTOCOL *PciIo;
|
|
UINT8 HdaStreamCtl3;
|
|
|
|
if (!HdaStream || !HdaStream->HdaControllerDev)
|
|
return EFI_INVALID_PARAMETER;
|
|
//DEBUG((DEBUG_INFO, "HdaControllerSetStreamId(%u, %u): start\n", HdaStream->Index, Index));
|
|
|
|
PciIo = HdaStream->HdaControllerDev->PciIo;
|
|
|
|
// Stop stream.
|
|
Status = HdaControllerSetStream(HdaStream, FALSE);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
|
|
// Get current value of register.
|
|
Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_SDNCTL3(HdaStream->Index), 1, &HdaStreamCtl3);
|
|
if (EFI_ERROR(Status))
|
|
return Status;
|
|
|
|
// Update stream index.
|
|
HdaStreamCtl3 = HDA_REG_SDNCTL3_STRM_SET(HdaStreamCtl3, Index);
|
|
|
|
// Write register.
|
|
Status = PciIo->Mem.Write(PciIo, EfiPciIoWidthUint8, PCI_HDA_BAR, HDA_REG_SDNCTL3(HdaStream->Index), 1, &HdaStreamCtl3);
|
|
// if (EFI_ERROR(Status))
|
|
// return Status;
|
|
|
|
// Success.
|
|
return Status;
|
|
}
|