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518 lines
15 KiB
C
518 lines
15 KiB
C
/** @file
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Platform TPM Profile Specification definition for TPM2.0.
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It covers both FIFO and CRB interface.
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Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _TPM_PTP_H_
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#define _TPM_PTP_H_
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//
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// PTP FIFO definition
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//
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//
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// Set structure alignment to 1-byte
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//
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#pragma pack (1)
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//
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// Register set map as specified in PTP specification Chapter 5
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//
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typedef struct {
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///
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/// Used to gain ownership for this particular port.
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///
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UINT8 Access; // 0
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UINT8 Reserved1[7]; // 1
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///
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/// Controls interrupts.
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///
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UINT32 IntEnable; // 8
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///
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/// SIRQ vector to be used by the TPM.
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///
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UINT8 IntVector; // 0ch
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UINT8 Reserved2[3]; // 0dh
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///
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/// What caused interrupt.
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///
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UINT32 IntSts; // 10h
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///
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/// Shows which interrupts are supported by that particular TPM.
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///
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UINT32 InterfaceCapability;// 14h
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///
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/// Status Register. Provides status of the TPM.
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///
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UINT8 Status; // 18h
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///
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/// Number of consecutive writes that can be done to the TPM.
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///
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UINT16 BurstCount; // 19h
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///
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/// Additional Status Register.
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///
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UINT8 StatusEx; // 1Bh
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UINT8 Reserved3[8];
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///
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/// Read or write FIFO, depending on transaction.
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///
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UINT32 DataFifo; // 24h
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UINT8 Reserved4[8]; // 28h
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///
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/// Used to identify the Interface types supported by the TPM.
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///
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UINT32 InterfaceId; // 30h
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UINT8 Reserved5[0x4c]; // 34h
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///
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/// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)
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///
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UINT32 XDataFifo; // 80h
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UINT8 Reserved6[0xe7c]; // 84h
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///
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/// Vendor ID
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///
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UINT16 Vid; // 0f00h
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///
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/// Device ID
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///
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UINT16 Did; // 0f02h
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///
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/// Revision ID
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///
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UINT8 Rid; // 0f04h
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UINT8 Reserved[0xfb]; // 0f05h
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} PTP_FIFO_REGISTERS;
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//
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// Restore original structure alignment
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//
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#pragma pack ()
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//
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// Define pointer types used to access TIS registers on PC
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//
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typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR;
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//
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// Define bits of FIFO Interface Identifier Register
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//
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typedef union {
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struct {
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UINT32 InterfaceType:4;
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UINT32 InterfaceVersion:4;
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UINT32 CapLocality:1;
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UINT32 Reserved1:2;
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UINT32 CapDataXferSizeSupport:2;
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UINT32 CapFIFO:1;
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UINT32 CapCRB:1;
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UINT32 CapIFRes:2;
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UINT32 InterfaceSelector:2;
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UINT32 IntfSelLock:1;
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UINT32 Reserved2:4;
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UINT32 Reserved3:8;
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} Bits;
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UINT32 Uint32;
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} PTP_FIFO_INTERFACE_IDENTIFIER;
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//
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// Define bits of FIFO Interface Capability Register
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//
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typedef union {
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struct {
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UINT32 DataAvailIntSupport:1;
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UINT32 StsValidIntSupport:1;
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UINT32 LocalityChangeIntSupport:1;
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UINT32 InterruptLevelHigh:1;
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UINT32 InterruptLevelLow:1;
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UINT32 InterruptEdgeRising:1;
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UINT32 InterruptEdgeFalling:1;
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UINT32 CommandReadyIntSupport:1;
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UINT32 BurstCountStatic:1;
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UINT32 DataTransferSizeSupport:2;
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UINT32 Reserved:17;
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UINT32 InterfaceVersion:3;
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UINT32 Reserved2:1;
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} Bits;
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UINT32 Uint32;
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} PTP_FIFO_INTERFACE_CAPABILITY;
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///
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/// InterfaceVersion
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///
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#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12 0x0
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#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13 0x2
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#define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP 0x3
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//
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// Define bits of ACCESS and STATUS registers
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//
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///
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/// This bit is a 1 to indicate that the other bits in this register are valid.
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///
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#define PTP_FIFO_VALID BIT7
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///
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/// Indicate that this locality is active.
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///
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#define PTP_FIFO_ACC_ACTIVE BIT5
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///
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/// Set to 1 to indicate that this locality had the TPM taken away while
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/// this locality had the TIS_PC_ACC_ACTIVE bit set.
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///
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#define PTP_FIFO_ACC_SEIZED BIT4
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///
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/// Set to 1 to indicate that TPM MUST reset the
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/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
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/// locality that is writing this bit.
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///
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#define PTP_FIFO_ACC_SEIZE BIT3
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///
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/// When this bit is 1, another locality is requesting usage of the TPM.
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///
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#define PTP_FIFO_ACC_PENDIND BIT2
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///
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/// Set to 1 to indicate that this locality is requesting to use TPM.
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///
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#define PTP_FIFO_ACC_RQUUSE BIT1
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///
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/// A value of 1 indicates that a T/OS has not been established on the platform
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///
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#define PTP_FIFO_ACC_ESTABLISH BIT0
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///
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/// This field indicates that STS_DATA and STS_EXPECT are valid
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///
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#define PTP_FIFO_STS_VALID BIT7
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///
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/// When this bit is 1, TPM is in the Ready state,
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/// indicating it is ready to receive a new command.
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///
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#define PTP_FIFO_STS_READY BIT6
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///
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/// Write a 1 to this bit to cause the TPM to execute that command.
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///
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#define PTP_FIFO_STS_GO BIT5
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///
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/// This bit indicates that the TPM has data available as a response.
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///
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#define PTP_FIFO_STS_DATA BIT4
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///
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/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
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///
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#define PTP_FIFO_STS_EXPECT BIT3
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///
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/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
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///
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#define PTP_FIFO_STS_SELFTEST_DONE BIT2
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///
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/// Writes a 1 to this bit to force the TPM to re-send the response.
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///
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#define PTP_FIFO_STS_RETRY BIT1
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///
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/// TPM Family Identifier.
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/// 00: TPM 1.2 Family
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/// 01: TPM 2.0 Family
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///
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#define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3)
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#define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2)
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#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0)
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#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2)
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///
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/// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED.
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/// A write of 1 after dataAvail and before tpmGo is ignored by the TPM.
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///
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#define PTP_FIFO_STS_EX_CANCEL BIT0
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//
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// PTP CRB definition
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//
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//
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// Set structure alignment to 1-byte
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//
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#pragma pack (1)
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//
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// Register set map as specified in PTP specification Chapter 5
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//
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typedef struct {
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///
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/// Used to determine current state of Locality of the TPM.
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///
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UINT32 LocalityState; // 0
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UINT8 Reserved1[4]; // 4
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///
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/// Used to gain control of the TPM by this Locality.
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///
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UINT32 LocalityControl; // 8
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///
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/// Used to determine whether Locality has been granted or Seized.
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///
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UINT32 LocalityStatus; // 0ch
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UINT8 Reserved2[0x20]; // 10h
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///
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/// Used to identify the Interface types supported by the TPM.
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///
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UINT32 InterfaceId; // 30h
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///
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/// Vendor ID
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///
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UINT16 Vid; // 34h
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///
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/// Device ID
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///
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UINT16 Did; // 36h
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///
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/// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability.
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///
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UINT64 CrbControlExtension; // 38h
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///
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/// Register used to initiate transactions for the CRB interface.
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///
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UINT32 CrbControlRequest; // 40h
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///
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/// Register used by the TPM to provide status of the CRB interface.
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///
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UINT32 CrbControlStatus; // 44h
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///
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/// Register used by software to cancel command processing.
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///
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UINT32 CrbControlCancel; // 48h
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///
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/// Register used to indicate presence of command or response data in the CRB buffer.
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///
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UINT32 CrbControlStart; // 4Ch
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///
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/// Register used to configure and respond to interrupts.
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///
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UINT32 CrbInterruptEnable; // 50h
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UINT32 CrbInterruptStatus; // 54h
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///
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/// Size of the Command buffer.
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///
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UINT32 CrbControlCommandSize; // 58h
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///
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/// Command buffer start address
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///
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UINT32 CrbControlCommandAddressLow; // 5Ch
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UINT32 CrbControlCommandAddressHigh; // 60h
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///
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/// Size of the Response buffer
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///
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UINT32 CrbControlResponseSize; // 64h
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///
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/// Address of the start of the Response buffer
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///
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UINT64 CrbControlResponseAddrss; // 68h
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UINT8 Reserved4[0x10]; // 70h
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///
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/// Command/Response Data may be defined as large as 3968 (0xF80).
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///
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UINT8 CrbDataBuffer[0xF80]; // 80h
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} PTP_CRB_REGISTERS;
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//
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// Define pointer types used to access CRB registers on PTP
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//
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typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR;
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//
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// Define bits of CRB Interface Identifier Register
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//
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typedef union {
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struct {
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UINT32 InterfaceType:4;
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UINT32 InterfaceVersion:4;
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UINT32 CapLocality:1;
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UINT32 CapCRBIdleBypass:1;
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UINT32 Reserved1:1;
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UINT32 CapDataXferSizeSupport:2;
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UINT32 CapFIFO:1;
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UINT32 CapCRB:1;
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UINT32 CapIFRes:2;
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UINT32 InterfaceSelector:2;
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UINT32 IntfSelLock:1;
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UINT32 Reserved2:4;
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UINT32 Rid:8;
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} Bits;
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UINT32 Uint32;
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} PTP_CRB_INTERFACE_IDENTIFIER;
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///
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/// InterfaceType
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///
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#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO 0x0
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#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB 0x1
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#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS 0xF
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///
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/// InterfaceVersion
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///
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#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO 0x0
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#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB 0x1
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///
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/// InterfaceSelector
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///
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#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO 0x0
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#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB 0x1
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//
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// Define bits of Locality State Register
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//
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///
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/// This bit indicates whether all other bits of this register contain valid values, if it is a 1.
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///
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#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7
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///
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/// 000 - Locality 0
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/// 001 - Locality 1
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/// 010 - Locality 2
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/// 011 - Locality 3
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/// 100 - Locality 4
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///
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#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4)
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#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0)
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#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2)
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#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3)
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#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3)
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#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4)
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///
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/// A 0 indicates to the host that no locality is assigned.
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/// A 1 indicates a locality has been assigned.
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///
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#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1
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///
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/// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End
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/// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1.
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///
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#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0
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//
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// Define bits of Locality Control Register
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//
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///
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/// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4.
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///
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#define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT BIT3
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///
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/// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality.
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///
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#define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2
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///
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/// Writes (1): The active Locality is done with the TPM.
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///
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#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1
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///
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/// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm.
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///
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#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0
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//
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// Define bits of Locality Status Register
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//
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///
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/// 0: A higher locality has not initiated a Seize arbitration process.
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/// 1: A higher locality has Seized the TPM from this locality.
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///
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#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1
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///
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/// 0: Locality has not been granted to the TPM.
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/// 1: Locality has been granted access to the TPM
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///
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#define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0
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//
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// Define bits of CRB Control Area Request Register
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//
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///
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/// Used by Software to indicate transition the TPM to and from the Idle state
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/// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle
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/// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state.
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/// TPM SHALL complete this transition within TIMEOUT_C.
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///
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#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1
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///
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/// Used by Software to request the TPM transition to the Ready State.
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/// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command.
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/// 0: Cleared to 0 by TPM to acknowledge the request.
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/// TPM SHALL complete this transition within TIMEOUT_C.
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///
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#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0
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//
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// Define bits of CRB Control Area Status Register
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//
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///
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/// Used by TPM to indicate it is in the Idle State
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/// 1: Set by TPM when in the Idle State
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/// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State.
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/// SHALL be cleared by TIMEOUT_C.
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///
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#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1
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///
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/// Used by the TPM to indicate current status.
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/// 1: Set by TPM to indicate a FATAL Error
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/// 0: Indicates TPM is operational
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///
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#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0
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//
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// Define bits of CRB Control Cancel Register
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//
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///
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/// Used by software to cancel command processing Reads return correct value
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/// Writes (0000 0001h): Cancel a command
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/// Writes (0000 0000h): Clears field when command has been cancelled
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///
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#define PTP_CRB_CONTROL_CANCEL BIT0
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//
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// Define bits of CRB Control Start Register
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//
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///
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/// When set by software, indicates a command is ready for processing.
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/// Writes (0000 0001h): TPM transitions to Command Execution
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/// Writes (0000 0000h): TPM clears this field and transitions to Command Completion
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///
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#define PTP_CRB_CONTROL_START BIT0
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//
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// Restore original structure alignment
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//
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#pragma pack ()
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//
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// Default TimeOut value
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//
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#define PTP_TIMEOUT_A (750 * 1000) // 750ms
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#define PTP_TIMEOUT_B (2000 * 1000) // 2s
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#define PTP_TIMEOUT_C (200 * 1000) // 200ms
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#define PTP_TIMEOUT_D (30 * 1000) // 30ms
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#endif
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