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242 lines
9.9 KiB
C
242 lines
9.9 KiB
C
/** @file
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EFI MM CPU Protocol as defined in the PI 1.5 specification.
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This protocol allows MM drivers to access architecture-standard registers from any of the CPU
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save state areas. In some cases, difference processors provide the same information in the save state,
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but not in the same format. These so-called pseudo-registers provide this information in a standard
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format.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _MM_CPU_H_
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#define _MM_CPU_H_
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#define EFI_MM_CPU_PROTOCOL_GUID \
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{ \
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0xeb346b97, 0x975f, 0x4a9f, { 0x8b, 0x22, 0xf8, 0xe9, 0x2b, 0xb3, 0xd5, 0x69 } \
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}
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///
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/// Save State register index
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///
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typedef enum {
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///
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/// x86/X64 standard registers
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///
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EFI_MM_SAVE_STATE_REGISTER_GDTBASE = 4,
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EFI_MM_SAVE_STATE_REGISTER_IDTBASE = 5,
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EFI_MM_SAVE_STATE_REGISTER_LDTBASE = 6,
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EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT = 7,
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EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT = 8,
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EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT = 9,
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EFI_MM_SAVE_STATE_REGISTER_LDTINFO = 10,
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EFI_MM_SAVE_STATE_REGISTER_ES = 20,
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EFI_MM_SAVE_STATE_REGISTER_CS = 21,
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EFI_MM_SAVE_STATE_REGISTER_SS = 22,
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EFI_MM_SAVE_STATE_REGISTER_DS = 23,
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EFI_MM_SAVE_STATE_REGISTER_FS = 24,
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EFI_MM_SAVE_STATE_REGISTER_GS = 25,
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EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL = 26,
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EFI_MM_SAVE_STATE_REGISTER_TR_SEL = 27,
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EFI_MM_SAVE_STATE_REGISTER_DR7 = 28,
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EFI_MM_SAVE_STATE_REGISTER_DR6 = 29,
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EFI_MM_SAVE_STATE_REGISTER_R8 = 30,
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EFI_MM_SAVE_STATE_REGISTER_R9 = 31,
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EFI_MM_SAVE_STATE_REGISTER_R10 = 32,
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EFI_MM_SAVE_STATE_REGISTER_R11 = 33,
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EFI_MM_SAVE_STATE_REGISTER_R12 = 34,
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EFI_MM_SAVE_STATE_REGISTER_R13 = 35,
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EFI_MM_SAVE_STATE_REGISTER_R14 = 36,
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EFI_MM_SAVE_STATE_REGISTER_R15 = 37,
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EFI_MM_SAVE_STATE_REGISTER_RAX = 38,
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EFI_MM_SAVE_STATE_REGISTER_RBX = 39,
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EFI_MM_SAVE_STATE_REGISTER_RCX = 40,
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EFI_MM_SAVE_STATE_REGISTER_RDX = 41,
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EFI_MM_SAVE_STATE_REGISTER_RSP = 42,
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EFI_MM_SAVE_STATE_REGISTER_RBP = 43,
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EFI_MM_SAVE_STATE_REGISTER_RSI = 44,
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EFI_MM_SAVE_STATE_REGISTER_RDI = 45,
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EFI_MM_SAVE_STATE_REGISTER_RIP = 46,
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EFI_MM_SAVE_STATE_REGISTER_RFLAGS = 51,
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EFI_MM_SAVE_STATE_REGISTER_CR0 = 52,
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EFI_MM_SAVE_STATE_REGISTER_CR3 = 53,
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EFI_MM_SAVE_STATE_REGISTER_CR4 = 54,
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EFI_MM_SAVE_STATE_REGISTER_FCW = 256,
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EFI_MM_SAVE_STATE_REGISTER_FSW = 257,
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EFI_MM_SAVE_STATE_REGISTER_FTW = 258,
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EFI_MM_SAVE_STATE_REGISTER_OPCODE = 259,
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EFI_MM_SAVE_STATE_REGISTER_FP_EIP = 260,
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EFI_MM_SAVE_STATE_REGISTER_FP_CS = 261,
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EFI_MM_SAVE_STATE_REGISTER_DATAOFFSET = 262,
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EFI_MM_SAVE_STATE_REGISTER_FP_DS = 263,
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EFI_MM_SAVE_STATE_REGISTER_MM0 = 264,
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EFI_MM_SAVE_STATE_REGISTER_MM1 = 265,
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EFI_MM_SAVE_STATE_REGISTER_MM2 = 266,
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EFI_MM_SAVE_STATE_REGISTER_MM3 = 267,
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EFI_MM_SAVE_STATE_REGISTER_MM4 = 268,
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EFI_MM_SAVE_STATE_REGISTER_MM5 = 269,
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EFI_MM_SAVE_STATE_REGISTER_MM6 = 270,
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EFI_MM_SAVE_STATE_REGISTER_MM7 = 271,
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EFI_MM_SAVE_STATE_REGISTER_XMM0 = 272,
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EFI_MM_SAVE_STATE_REGISTER_XMM1 = 273,
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EFI_MM_SAVE_STATE_REGISTER_XMM2 = 274,
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EFI_MM_SAVE_STATE_REGISTER_XMM3 = 275,
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EFI_MM_SAVE_STATE_REGISTER_XMM4 = 276,
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EFI_MM_SAVE_STATE_REGISTER_XMM5 = 277,
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EFI_MM_SAVE_STATE_REGISTER_XMM6 = 278,
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EFI_MM_SAVE_STATE_REGISTER_XMM7 = 279,
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EFI_MM_SAVE_STATE_REGISTER_XMM8 = 280,
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EFI_MM_SAVE_STATE_REGISTER_XMM9 = 281,
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EFI_MM_SAVE_STATE_REGISTER_XMM10 = 282,
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EFI_MM_SAVE_STATE_REGISTER_XMM11 = 283,
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EFI_MM_SAVE_STATE_REGISTER_XMM12 = 284,
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EFI_MM_SAVE_STATE_REGISTER_XMM13 = 285,
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EFI_MM_SAVE_STATE_REGISTER_XMM14 = 286,
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EFI_MM_SAVE_STATE_REGISTER_XMM15 = 287,
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///
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/// Pseudo-Registers
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///
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EFI_MM_SAVE_STATE_REGISTER_IO = 512,
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EFI_MM_SAVE_STATE_REGISTER_LMA = 513,
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EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID = 514
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} EFI_MM_SAVE_STATE_REGISTER;
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///
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/// The EFI_MM_SAVE_STATE_REGISTER_LMA pseudo-register values
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/// If the processor acts in 32-bit mode at the time the MMI occurred, the pseudo register value
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/// EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT is returned in Buffer. Otherwise,
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/// EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT is returned in Buffer.
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///
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#define EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT 32
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#define EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT 64
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///
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/// Size width of I/O instruction
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///
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typedef enum {
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EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 = 0,
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EFI_MM_SAVE_STATE_IO_WIDTH_UINT16 = 1,
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EFI_MM_SAVE_STATE_IO_WIDTH_UINT32 = 2,
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EFI_MM_SAVE_STATE_IO_WIDTH_UINT64 = 3
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} EFI_MM_SAVE_STATE_IO_WIDTH;
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///
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/// Types of I/O instruction
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///
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typedef enum {
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EFI_MM_SAVE_STATE_IO_TYPE_INPUT = 1,
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EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT = 2,
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EFI_MM_SAVE_STATE_IO_TYPE_STRING = 4,
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EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX = 8
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} EFI_MM_SAVE_STATE_IO_TYPE;
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///
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/// Structure of the data which is returned when ReadSaveState() is called with
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/// EFI_MM_SAVE_STATE_REGISTER_IO. If there was no I/O then ReadSaveState() will
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/// return EFI_NOT_FOUND.
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///
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/// This structure describes the I/O operation which was in process when the MMI was generated.
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///
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typedef struct _EFI_MM_SAVE_STATE_IO_INFO {
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///
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/// For input instruction (IN, INS), this is data read before the MMI occurred. For output
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/// instructions (OUT, OUTS) this is data that was written before the MMI occurred. The
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/// width of the data is specified by IoWidth.
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///
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UINT64 IoData;
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///
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/// The I/O port that was being accessed when the MMI was triggered.
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///
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UINT16 IoPort;
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///
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/// Defines the size width (UINT8, UINT16, UINT32, UINT64) for IoData.
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///
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EFI_MM_SAVE_STATE_IO_WIDTH IoWidth;
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///
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/// Defines type of I/O instruction.
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///
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EFI_MM_SAVE_STATE_IO_TYPE IoType;
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} EFI_MM_SAVE_STATE_IO_INFO;
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typedef struct _EFI_MM_CPU_PROTOCOL EFI_MM_CPU_PROTOCOL;
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/**
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Read data from the CPU save state.
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This function is used to read the specified number of bytes of the specified register from the CPU
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save state of the specified CPU and place the value into the buffer. If the CPU does not support the
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specified register Register, then EFI_NOT_FOUND should be returned. If the CPU does not
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support the specified register width Width, then EFI_INVALID_PARAMETER is returned.
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@param[in] This The EFI_MM_CPU_PROTOCOL instance.
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@param[in] Width The number of bytes to read from the CPU save state.
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@param[in] Register Specifies the CPU register to read form the save state.
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@param[in] CpuIndex Specifies the zero-based index of the CPU save state.
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@param[out] Buffer Upon return, this holds the CPU register value read from the save state.
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@retval EFI_SUCCESS The register was read from Save State.
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@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
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@retval EFI_INVALID_PARAMETER Input parameters are not valid, for example, Processor No or register width
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is not correct.This or Buffer is NULL.
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**/
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typedef
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EFI_STATUS
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(EFIAPI *EFI_MM_READ_SAVE_STATE)(
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IN CONST EFI_MM_CPU_PROTOCOL *This,
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IN UINTN Width,
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IN EFI_MM_SAVE_STATE_REGISTER Register,
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IN UINTN CpuIndex,
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OUT VOID *Buffer
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);
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/**
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Write data to the CPU save state.
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This function is used to write the specified number of bytes of the specified register to the CPU save
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state of the specified CPU and place the value into the buffer. If the CPU does not support the
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specified register Register, then EFI_UNSUPPORTED should be returned. If the CPU does not
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support the specified register width Width, then EFI_INVALID_PARAMETER is returned.
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@param[in] This The EFI_MM_CPU_PROTOCOL instance.
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@param[in] Width The number of bytes to write to the CPU save state.
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@param[in] Register Specifies the CPU register to write to the save state.
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@param[in] CpuIndex Specifies the zero-based index of the CPU save state.
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@param[in] Buffer Upon entry, this holds the new CPU register value.
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@retval EFI_SUCCESS The register was written to Save State.
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@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
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@retval EFI_INVALID_PARAMETER Input parameters are not valid. For example:
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ProcessorIndex or Width is not correct.
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**/
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typedef
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EFI_STATUS
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(EFIAPI *EFI_MM_WRITE_SAVE_STATE)(
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IN CONST EFI_MM_CPU_PROTOCOL *This,
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IN UINTN Width,
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IN EFI_MM_SAVE_STATE_REGISTER Register,
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IN UINTN CpuIndex,
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IN CONST VOID *Buffer
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);
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///
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/// EFI MM CPU Protocol provides access to CPU-related information while in MM.
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///
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/// This protocol allows MM drivers to access architecture-standard registers from any of the CPU
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/// save state areas. In some cases, difference processors provide the same information in the save state,
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/// but not in the same format. These so-called pseudo-registers provide this information in a standard
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/// format.
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///
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struct _EFI_MM_CPU_PROTOCOL {
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EFI_MM_READ_SAVE_STATE ReadSaveState;
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EFI_MM_WRITE_SAVE_STATE WriteSaveState;
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};
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extern EFI_GUID gEfiMmCpuProtocolGuid;
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#endif
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