465 lines
13 KiB
C
465 lines
13 KiB
C
/*++
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Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
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Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
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Portions copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Module Name:
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GicV2/ArmGicV2Dxe.c
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Abstract:
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Driver implementing the GicV2 interrupt controller protocol
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--*/
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#include <Library/ArmGicLib.h>
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#include "ArmGicDxe.h"
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#define ARM_GIC_DEFAULT_PRIORITY 0x80
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extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
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extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;
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STATIC UINT32 mGicInterruptInterfaceBase;
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STATIC UINT32 mGicDistributorBase;
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/**
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Enable interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt enabled.
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@retval EFI_UNSUPPORTED Source interrupt is not supported
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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GicV2EnableInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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if (Source >= mGicNumInterrupts) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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ArmGicEnableInterrupt (mGicDistributorBase, 0, Source);
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return EFI_SUCCESS;
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}
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/**
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Disable interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt disabled.
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@retval EFI_UNSUPPORTED Source interrupt is not supported
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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GicV2DisableInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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if (Source >= mGicNumInterrupts) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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ArmGicDisableInterrupt (mGicDistributorBase, 0, Source);
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return EFI_SUCCESS;
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}
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/**
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Return current state of interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@param InterruptState TRUE: source enabled, FALSE: source disabled.
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@retval EFI_SUCCESS InterruptState is valid
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@retval EFI_UNSUPPORTED Source interrupt is not supported
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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GicV2GetInterruptSourceState (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source,
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IN BOOLEAN *InterruptState
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)
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{
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if (Source >= mGicNumInterrupts) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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*InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, 0, Source);
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return EFI_SUCCESS;
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}
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/**
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Signal to the hardware that the End Of Interrupt state
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has been reached.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt ended successfully.
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@retval EFI_UNSUPPORTED Source interrupt is not supported
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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GicV2EndOfInterrupt (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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if (Source >= mGicNumInterrupts) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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ArmGicV2EndOfInterrupt (mGicInterruptInterfaceBase, Source);
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return EFI_SUCCESS;
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}
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/**
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EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
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@param InterruptType Defines the type of interrupt or exception that
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occurred on the processor.This parameter is
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processor architecture specific.
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@param SystemContext A pointer to the processor context when
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the interrupt occurred on the processor.
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@return None
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**/
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STATIC
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VOID
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EFIAPI
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GicV2IrqInterruptHandler (
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IN EFI_EXCEPTION_TYPE InterruptType,
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IN EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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UINT32 GicInterrupt;
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HARDWARE_INTERRUPT_HANDLER InterruptHandler;
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GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);
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// Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the
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// number of interrupt (ie: Spurious interrupt).
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if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
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// The special interrupts do not need to be acknowledged
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return;
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}
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InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
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if (InterruptHandler != NULL) {
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// Call the registered interrupt handler.
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InterruptHandler (GicInterrupt, SystemContext);
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} else {
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DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
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GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);
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}
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}
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// The protocol instance produced by this driver
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EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
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RegisterInterruptSource,
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GicV2EnableInterruptSource,
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GicV2DisableInterruptSource,
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GicV2GetInterruptSourceState,
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GicV2EndOfInterrupt
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};
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/**
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Get interrupt trigger type of an interrupt
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt.
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@param TriggerType Returns interrupt trigger type.
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@retval EFI_SUCCESS Source interrupt supported.
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@retval EFI_UNSUPPORTED Source interrupt is not supported.
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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GicV2GetTriggerType (
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IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source,
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OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType
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)
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{
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UINTN RegAddress;
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UINTN Config1Bit;
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EFI_STATUS Status;
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Status = GicGetDistributorIcfgBaseAndBit (
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Source,
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&RegAddress,
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&Config1Bit
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
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*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
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} else {
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*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
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}
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return EFI_SUCCESS;
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}
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/**
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Set interrupt trigger type of an interrupt
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt.
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@param TriggerType Interrupt trigger type.
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@retval EFI_SUCCESS Source interrupt supported.
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@retval EFI_UNSUPPORTED Source interrupt is not supported.
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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GicV2SetTriggerType (
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IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source,
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IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType
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)
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{
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UINTN RegAddress;
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UINTN Config1Bit;
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UINT32 Value;
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EFI_STATUS Status;
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BOOLEAN SourceEnabled;
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if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
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&& (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH))
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{
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DEBUG ((
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DEBUG_ERROR,
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"Invalid interrupt trigger type: %d\n", \
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TriggerType
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));
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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Status = GicGetDistributorIcfgBaseAndBit (
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Source,
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&RegAddress,
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&Config1Bit
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = GicV2GetInterruptSourceState (
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(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
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Source,
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&SourceEnabled
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Value = (TriggerType == EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
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? ARM_GIC_ICDICFR_EDGE_TRIGGERED
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: ARM_GIC_ICDICFR_LEVEL_TRIGGERED;
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// Before changing the value, we must disable the interrupt,
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// otherwise GIC behavior is UNPREDICTABLE.
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if (SourceEnabled) {
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GicV2DisableInterruptSource (
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(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
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Source
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);
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}
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MmioAndThenOr32 (
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RegAddress,
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~(0x1 << Config1Bit),
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Value << Config1Bit
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);
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// Restore interrupt state
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if (SourceEnabled) {
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GicV2EnableInterruptSource (
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(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
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Source
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);
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}
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return EFI_SUCCESS;
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}
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EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {
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(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
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(HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource,
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(HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource,
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(HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV2GetInterruptSourceState,
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(HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV2EndOfInterrupt,
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GicV2GetTriggerType,
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GicV2SetTriggerType
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};
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/**
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Shutdown our hardware
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DXE Core will disable interrupts and turn off the timer and disable
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interrupts after all the event handlers have run.
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@param[in] Event The Event that is being processed
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@param[in] Context Event Context
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**/
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STATIC
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VOID
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EFIAPI
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GicV2ExitBootServicesEvent (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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UINTN Index;
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UINT32 GicInterrupt;
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// Disable all the interrupts
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for (Index = 0; Index < mGicNumInterrupts; Index++) {
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GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
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}
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// Acknowledge all pending interrupts
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do {
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GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);
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if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) < mGicNumInterrupts) {
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GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);
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}
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} while (!ARM_GIC_IS_SPECIAL_INTERRUPTS (GicInterrupt));
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// Disable Gic Interface
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ArmGicV2DisableInterruptInterface (mGicInterruptInterfaceBase);
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// Disable Gic Distributor
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ArmGicDisableDistributor (mGicDistributorBase);
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}
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/**
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Initialize the state information for the CPU Architectural Protocol
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@param ImageHandle of the loaded driver
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@param SystemTable Pointer to the System Table
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@retval EFI_SUCCESS Protocol registered
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@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
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@retval EFI_DEVICE_ERROR Hardware problems
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**/
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EFI_STATUS
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GicV2DxeInitialize (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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UINTN Index;
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UINT32 RegOffset;
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UINTN RegShift;
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UINT32 CpuTarget;
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// Make sure the Interrupt Controller Protocol is not already installed in
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// the system.
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ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
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mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase);
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mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);
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mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
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for (Index = 0; Index < mGicNumInterrupts; Index++) {
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GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
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// Set Priority
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RegOffset = Index / 4;
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RegShift = (Index % 4) * 8;
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MmioAndThenOr32 (
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mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
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~(0xff << RegShift),
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ARM_GIC_DEFAULT_PRIORITY << RegShift
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);
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}
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// Targets the interrupts to the Primary Cpu
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// Only Primary CPU will run this code. We can identify our GIC CPU ID by
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// reading the GIC Distributor Target register. The 8 first GICD_ITARGETSRn
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// are banked to each connected CPU. These 8 registers hold the CPU targets
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// fields for interrupts 0-31. More Info in the GIC Specification about
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// "Interrupt Processor Targets Registers"
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// Read the first Interrupt Processor Targets Register (that corresponds to
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// the 4 first SGIs)
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CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);
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// The CPU target is a bit field mapping each CPU to a GIC CPU Interface.
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// This value is 0 when we run on a uniprocessor platform.
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if (CpuTarget != 0) {
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// The 8 first Interrupt Processor Targets Registers are read-only
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for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
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MmioWrite32 (
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mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),
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CpuTarget
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);
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}
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}
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// Set binary point reg to 0x7 (no preemption)
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MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCBPR, 0x7);
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// Set priority mask reg to 0xff to allow all priorities through
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MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0xff);
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// Enable gic cpu interface
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ArmGicEnableInterruptInterface (mGicInterruptInterfaceBase);
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// Enable gic distributor
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ArmGicEnableDistributor (mGicDistributorBase);
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Status = InstallAndRegisterInterruptService (
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&gHardwareInterruptV2Protocol,
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&gHardwareInterrupt2V2Protocol,
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GicV2IrqInterruptHandler,
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GicV2ExitBootServicesEvent
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);
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return Status;
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}
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