123 lines
3.1 KiB
C
123 lines
3.1 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef ARM_V7_H_
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#define ARM_V7_H_
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#include <Chipset/ArmV7Mmu.h>
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// ARM Interrupt ID in Exception Table
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#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ
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// ID_PFR1 - ARM Processor Feature Register 1 definitions
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#define ARM_PFR1_SEC (0xFUL << 4)
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#define ARM_PFR1_TIMER (0xFUL << 16)
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#define ARM_PFR1_GIC (0xFUL << 28)
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// Domain Access Control Register
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#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
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// CPSR - Coprocessor Status Register definitions
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#define CPSR_MODE_USER 0x10
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#define CPSR_MODE_FIQ 0x11
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#define CPSR_MODE_IRQ 0x12
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#define CPSR_MODE_SVC 0x13
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#define CPSR_MODE_ABORT 0x17
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#define CPSR_MODE_HYP 0x1A
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#define CPSR_MODE_UNDEFINED 0x1B
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#define CPSR_MODE_SYSTEM 0x1F
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#define CPSR_MODE_MASK 0x1F
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#define CPSR_ASYNC_ABORT (1 << 8)
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#define CPSR_IRQ (1 << 7)
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#define CPSR_FIQ (1 << 6)
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// CPACR - Coprocessor Access Control Register definitions
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#define CPACR_CP_DENIED(cp) 0x00
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#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
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#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
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#define CPACR_ASEDIS (1 << 31)
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#define CPACR_D32DIS (1 << 30)
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#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
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// NSACR - Non-Secure Access Control Register definitions
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#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
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#define NSACR_NSD32DIS (1 << 14)
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#define NSACR_NSASEDIS (1 << 15)
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#define NSACR_PLE (1 << 16)
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#define NSACR_TL (1 << 17)
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#define NSACR_NS_SMP (1 << 18)
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#define NSACR_RFR (1 << 19)
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// SCR - Secure Configuration Register definitions
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#define SCR_NS (1 << 0)
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#define SCR_IRQ (1 << 1)
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#define SCR_FIQ (1 << 2)
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#define SCR_EA (1 << 3)
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#define SCR_FW (1 << 4)
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#define SCR_AW (1 << 5)
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// MIDR - Main ID Register definitions
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#define ARM_CPU_TYPE_SHIFT 4
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#define ARM_CPU_TYPE_MASK 0xFFF
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#define ARM_CPU_TYPE_AEMV8 0xD0F
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#define ARM_CPU_TYPE_A53 0xD03
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#define ARM_CPU_TYPE_A57 0xD07
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#define ARM_CPU_TYPE_A15 0xC0F
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#define ARM_CPU_TYPE_A12 0xC0D
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#define ARM_CPU_TYPE_A9 0xC09
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#define ARM_CPU_TYPE_A7 0xC07
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#define ARM_CPU_TYPE_A5 0xC05
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#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
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#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
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#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
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VOID
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EFIAPI
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ArmEnableSWPInstruction (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadCbar (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadTpidrurw (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteTpidrurw (
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UINTN Value
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);
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UINT32
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EFIAPI
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ArmReadNsacr (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteNsacr (
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IN UINT32 Nsacr
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);
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#endif // ARM_V7_H_
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