112 lines
4.1 KiB
C
112 lines
4.1 KiB
C
/** @file
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Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef ARM_CACHE_H_
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#define ARM_CACHE_H_
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#include <Uefi/UefiBaseType.h>
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// The ARM Architecture Reference Manual for ARMv8-A defines up
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// to 7 levels of cache, L1 through L7.
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#define MAX_ARM_CACHE_LEVEL 7
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/// Defines the structure of the CSSELR (Cache Size Selection) register
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typedef union {
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struct {
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UINT32 InD : 1; ///< Instruction not Data bit
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UINT32 Level : 3; ///< Cache level (zero based)
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UINT32 TnD : 1; ///< Allocation not Data bit
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UINT32 Reserved : 27; ///< Reserved, RES0
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} Bits; ///< Bitfield definition of the register
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UINT32 Data; ///< The entire 32-bit value
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} CSSELR_DATA;
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/// The cache type values for the InD field of the CSSELR register
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typedef enum {
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/// Select the data or unified cache
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CsselrCacheTypeDataOrUnified = 0,
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/// Select the instruction cache
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CsselrCacheTypeInstruction,
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CsselrCacheTypeMax
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} CSSELR_CACHE_TYPE;
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/// Defines the structure of the CCSIDR (Current Cache Size ID) register
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typedef union {
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struct {
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UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
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UINT64 Associativity : 10; ///< Associativity - 1
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UINT64 NumSets : 15; ///< Number of sets in the cache -1
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UINT64 Unknown : 4; ///< Reserved, UNKNOWN
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UINT64 Reserved : 32; ///< Reserved, RES0
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} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
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struct {
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UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
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UINT64 Associativity : 21; ///< Associativity - 1
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UINT64 Reserved1 : 8; ///< Reserved, RES0
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UINT64 NumSets : 24; ///< Number of sets in the cache -1
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UINT64 Reserved2 : 8; ///< Reserved, RES0
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} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
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struct {
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UINT64 LineSize : 3;
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UINT64 Associativity : 21;
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UINT64 Reserved : 8;
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UINT64 Unallocated : 32;
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} BitsCcidxAA32;
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UINT64 Data; ///< The entire 64-bit value
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} CCSIDR_DATA;
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/// Defines the structure of the AARCH32 CCSIDR2 register.
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typedef union {
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struct {
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UINT32 NumSets : 24; ///< Number of sets in the cache - 1
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UINT32 Reserved : 8; ///< Reserved, RES0
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} Bits; ///< Bitfield definition of the register
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UINT32 Data; ///< The entire 32-bit value
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} CCSIDR2_DATA;
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/** Defines the structure of the CLIDR (Cache Level ID) register.
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*
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* The lower 32 bits are the same for both AARCH32 and AARCH64
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* so we can use the same structure for both.
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**/
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typedef union {
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struct {
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UINT32 Ctype1 : 3; ///< Level 1 cache type
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UINT32 Ctype2 : 3; ///< Level 2 cache type
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UINT32 Ctype3 : 3; ///< Level 3 cache type
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UINT32 Ctype4 : 3; ///< Level 4 cache type
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UINT32 Ctype5 : 3; ///< Level 5 cache type
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UINT32 Ctype6 : 3; ///< Level 6 cache type
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UINT32 Ctype7 : 3; ///< Level 7 cache type
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UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
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UINT32 LoC : 3; ///< Level of Coherency
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UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
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UINT32 Icb : 3; ///< Inner Cache Boundary
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} Bits; ///< Bitfield definition of the register
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UINT32 Data; ///< The entire 32-bit value
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} CLIDR_DATA;
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/// The cache types reported in the CLIDR register.
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typedef enum {
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/// No cache is present
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ClidrCacheTypeNone = 0,
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/// There is only an instruction cache
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ClidrCacheTypeInstructionOnly,
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/// There is only a data cache
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ClidrCacheTypeDataOnly,
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/// There are separate data and instruction caches
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ClidrCacheTypeSeparate,
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/// There is a unified cache
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ClidrCacheTypeUnified,
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ClidrCacheTypeMax
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} CLIDR_CACHE_TYPE;
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#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
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#endif /* ARM_CACHE_H_ */
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