792 lines
11 KiB
C
792 lines
11 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef ARM_LIB_H_
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#define ARM_LIB_H_
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#include <Uefi/UefiBaseType.h>
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#ifdef MDE_CPU_ARM
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#include <Chipset/ArmV7.h>
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#elif defined (MDE_CPU_AARCH64)
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#include <Chipset/AArch64.h>
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#else
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#error "Unknown chipset."
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#endif
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#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
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EFI_MEMORY_WT | EFI_MEMORY_WB | \
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EFI_MEMORY_UCE)
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/**
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* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
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*
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* The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
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* be used in Secure World to distinguished Secure to Non-Secure memory.
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*/
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typedef enum {
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ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
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ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
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ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
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ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
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// On some platforms, memory mapped flash region is designed as not supporting
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// shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
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// need.
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// Do NOT use below two attributes if you are not sure.
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ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
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ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
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ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
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ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
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ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
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ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
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} ARM_MEMORY_REGION_ATTRIBUTES;
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#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
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typedef struct {
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EFI_PHYSICAL_ADDRESS PhysicalBase;
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EFI_VIRTUAL_ADDRESS VirtualBase;
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UINT64 Length;
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ARM_MEMORY_REGION_ATTRIBUTES Attributes;
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} ARM_MEMORY_REGION_DESCRIPTOR;
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typedef VOID (*CACHE_OPERATION)(
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VOID
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);
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typedef VOID (*LINE_OPERATION)(
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UINTN
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);
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//
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// ARM Processor Mode
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//
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typedef enum {
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ARM_PROCESSOR_MODE_USER = 0x10,
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ARM_PROCESSOR_MODE_FIQ = 0x11,
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ARM_PROCESSOR_MODE_IRQ = 0x12,
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ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
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ARM_PROCESSOR_MODE_ABORT = 0x17,
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ARM_PROCESSOR_MODE_HYP = 0x1A,
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ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,
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ARM_PROCESSOR_MODE_SYSTEM = 0x1F,
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ARM_PROCESSOR_MODE_MASK = 0x1F
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} ARM_PROCESSOR_MODE;
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//
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// ARM Cpu IDs
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//
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#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
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#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
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#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
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#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
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#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
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#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
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#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
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#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
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#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
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#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
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#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
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#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
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//
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// ARM MP Core IDs
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//
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#define ARM_CORE_AFF0 0xFF
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#define ARM_CORE_AFF1 (0xFF << 8)
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#define ARM_CORE_AFF2 (0xFF << 16)
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#define ARM_CORE_AFF3 (0xFFULL << 32)
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#define ARM_CORE_MASK ARM_CORE_AFF0
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#define ARM_CLUSTER_MASK ARM_CORE_AFF1
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#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
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#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
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#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
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#define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)
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#define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)
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#define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)
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#define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)
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#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
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/** Reads the CCSIDR register for the specified cache.
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@param CSSELR The CSSELR cache selection register value.
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@return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
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Returns the contents of the CCSIDR register in AARCH32 mode.
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**/
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UINTN
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ReadCCSIDR (
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IN UINT32 CSSELR
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);
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/** Reads the CCSIDR2 for the specified cache.
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@param CSSELR The CSSELR cache selection register value
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@return The contents of the CCSIDR2 register for the specified cache.
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**/
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UINT32
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ReadCCSIDR2 (
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IN UINT32 CSSELR
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);
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/** Reads the Cache Level ID (CLIDR) register.
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@return The contents of the CLIDR_EL1 register.
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**/
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UINT32
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ReadCLIDR (
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VOID
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);
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UINTN
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EFIAPI
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ArmDataCacheLineLength (
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VOID
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);
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UINTN
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EFIAPI
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ArmInstructionCacheLineLength (
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VOID
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);
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UINTN
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EFIAPI
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ArmCacheWritebackGranule (
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VOID
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);
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UINTN
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EFIAPI
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ArmIsArchTimerImplemented (
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VOID
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);
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UINTN
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EFIAPI
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ArmCacheInfo (
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VOID
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);
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BOOLEAN
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EFIAPI
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ArmIsMpCore (
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VOID
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);
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VOID
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EFIAPI
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ArmInvalidateDataCache (
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VOID
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);
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VOID
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EFIAPI
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ArmCleanInvalidateDataCache (
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VOID
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);
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VOID
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EFIAPI
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ArmCleanDataCache (
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VOID
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);
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VOID
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EFIAPI
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ArmInvalidateInstructionCache (
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VOID
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);
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VOID
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EFIAPI
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ArmInvalidateDataCacheEntryByMVA (
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IN UINTN Address
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);
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VOID
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EFIAPI
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ArmCleanDataCacheEntryToPoUByMVA (
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IN UINTN Address
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);
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VOID
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EFIAPI
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ArmInvalidateInstructionCacheEntryToPoUByMVA (
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IN UINTN Address
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);
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VOID
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EFIAPI
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ArmCleanDataCacheEntryByMVA (
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IN UINTN Address
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);
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VOID
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EFIAPI
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ArmCleanInvalidateDataCacheEntryByMVA (
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IN UINTN Address
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);
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VOID
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EFIAPI
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ArmEnableDataCache (
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VOID
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);
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VOID
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EFIAPI
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ArmDisableDataCache (
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VOID
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);
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VOID
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EFIAPI
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ArmEnableInstructionCache (
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VOID
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);
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VOID
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EFIAPI
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ArmDisableInstructionCache (
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VOID
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);
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VOID
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EFIAPI
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ArmEnableMmu (
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VOID
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);
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VOID
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EFIAPI
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ArmDisableMmu (
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VOID
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);
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VOID
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EFIAPI
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ArmEnableCachesAndMmu (
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VOID
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);
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VOID
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EFIAPI
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ArmDisableCachesAndMmu (
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VOID
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);
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VOID
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EFIAPI
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ArmEnableInterrupts (
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VOID
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);
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UINTN
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EFIAPI
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ArmDisableInterrupts (
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VOID
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);
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BOOLEAN
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EFIAPI
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ArmGetInterruptState (
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VOID
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);
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VOID
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EFIAPI
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ArmEnableAsynchronousAbort (
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VOID
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);
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UINTN
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EFIAPI
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ArmDisableAsynchronousAbort (
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VOID
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);
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VOID
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EFIAPI
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ArmEnableIrq (
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VOID
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);
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UINTN
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EFIAPI
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ArmDisableIrq (
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VOID
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);
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VOID
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EFIAPI
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ArmEnableFiq (
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VOID
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);
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UINTN
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EFIAPI
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ArmDisableFiq (
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VOID
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);
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BOOLEAN
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EFIAPI
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ArmGetFiqState (
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VOID
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);
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/**
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* Invalidate Data and Instruction TLBs
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*/
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VOID
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EFIAPI
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ArmInvalidateTlb (
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VOID
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);
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VOID
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EFIAPI
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ArmUpdateTranslationTableEntry (
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IN VOID *TranslationTableEntry,
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IN VOID *Mva
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);
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VOID
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EFIAPI
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ArmSetDomainAccessControl (
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IN UINT32 Domain
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);
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VOID
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EFIAPI
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ArmSetTTBR0 (
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IN VOID *TranslationTableBase
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);
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VOID
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EFIAPI
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ArmSetTTBCR (
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IN UINT32 Bits
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);
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VOID *
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EFIAPI
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ArmGetTTBR0BaseAddress (
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VOID
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);
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BOOLEAN
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EFIAPI
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ArmMmuEnabled (
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VOID
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);
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VOID
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EFIAPI
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ArmEnableBranchPrediction (
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VOID
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);
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VOID
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EFIAPI
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ArmDisableBranchPrediction (
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VOID
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);
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VOID
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EFIAPI
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ArmSetLowVectors (
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VOID
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);
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VOID
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EFIAPI
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ArmSetHighVectors (
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VOID
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);
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VOID
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EFIAPI
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ArmDataMemoryBarrier (
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VOID
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);
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VOID
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EFIAPI
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ArmDataSynchronizationBarrier (
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VOID
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);
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VOID
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EFIAPI
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ArmInstructionSynchronizationBarrier (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteVBar (
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IN UINTN VectorBase
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);
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UINTN
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EFIAPI
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ArmReadVBar (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteAuxCr (
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IN UINT32 Bit
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);
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UINT32
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EFIAPI
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ArmReadAuxCr (
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VOID
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);
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VOID
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EFIAPI
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ArmSetAuxCrBit (
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IN UINT32 Bits
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);
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VOID
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EFIAPI
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ArmUnsetAuxCrBit (
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IN UINT32 Bits
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);
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VOID
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EFIAPI
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ArmCallSEV (
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VOID
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);
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VOID
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EFIAPI
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ArmCallWFE (
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VOID
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);
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VOID
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EFIAPI
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ArmCallWFI (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadMpidr (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadMidr (
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VOID
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);
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UINT32
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EFIAPI
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ArmReadCpacr (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteCpacr (
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IN UINT32 Access
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);
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VOID
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EFIAPI
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ArmEnableVFP (
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VOID
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);
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/**
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Get the Secure Configuration Register value
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@return Value read from the Secure Configuration Register
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**/
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UINT32
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EFIAPI
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ArmReadScr (
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VOID
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);
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/**
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Set the Secure Configuration Register
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@param Value Value to write to the Secure Configuration Register
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**/
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VOID
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EFIAPI
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ArmWriteScr (
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IN UINT32 Value
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);
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UINT32
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EFIAPI
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ArmReadMVBar (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteMVBar (
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IN UINT32 VectorMonitorBase
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);
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UINT32
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EFIAPI
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ArmReadSctlr (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteSctlr (
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IN UINT32 Value
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);
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UINTN
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EFIAPI
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ArmReadHVBar (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteHVBar (
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IN UINTN HypModeVectorBase
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);
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//
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// Helper functions for accessing CPU ACTLR
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//
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UINTN
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EFIAPI
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ArmReadCpuActlr (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteCpuActlr (
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IN UINTN Val
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);
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VOID
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EFIAPI
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ArmSetCpuActlrBit (
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IN UINTN Bits
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);
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VOID
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EFIAPI
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ArmUnsetCpuActlrBit (
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IN UINTN Bits
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);
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//
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// Accessors for the architected generic timer registers
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//
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#define ARM_ARCH_TIMER_ENABLE (1 << 0)
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#define ARM_ARCH_TIMER_IMASK (1 << 1)
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#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
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UINTN
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EFIAPI
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ArmReadCntFrq (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteCntFrq (
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UINTN FreqInHz
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);
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UINT64
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EFIAPI
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ArmReadCntPct (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadCntkCtl (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteCntkCtl (
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UINTN Val
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);
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UINTN
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EFIAPI
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ArmReadCntpTval (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteCntpTval (
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UINTN Val
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);
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UINTN
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EFIAPI
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ArmReadCntpCtl (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteCntpCtl (
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UINTN Val
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);
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UINTN
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EFIAPI
|
|
ArmReadCntvTval (
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
EFIAPI
|
|
ArmWriteCntvTval (
|
|
UINTN Val
|
|
);
|
|
|
|
UINTN
|
|
EFIAPI
|
|
ArmReadCntvCtl (
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
EFIAPI
|
|
ArmWriteCntvCtl (
|
|
UINTN Val
|
|
);
|
|
|
|
UINT64
|
|
EFIAPI
|
|
ArmReadCntvCt (
|
|
VOID
|
|
);
|
|
|
|
UINT64
|
|
EFIAPI
|
|
ArmReadCntpCval (
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
EFIAPI
|
|
ArmWriteCntpCval (
|
|
UINT64 Val
|
|
);
|
|
|
|
UINT64
|
|
EFIAPI
|
|
ArmReadCntvCval (
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
EFIAPI
|
|
ArmWriteCntvCval (
|
|
UINT64 Val
|
|
);
|
|
|
|
UINT64
|
|
EFIAPI
|
|
ArmReadCntvOff (
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
EFIAPI
|
|
ArmWriteCntvOff (
|
|
UINT64 Val
|
|
);
|
|
|
|
UINTN
|
|
EFIAPI
|
|
ArmGetPhysicalAddressBits (
|
|
VOID
|
|
);
|
|
|
|
///
|
|
/// ID Register Helper functions
|
|
///
|
|
|
|
/**
|
|
Check whether the CPU supports the GIC system register interface (any version)
|
|
|
|
@return Whether GIC System Register Interface is supported
|
|
|
|
**/
|
|
BOOLEAN
|
|
EFIAPI
|
|
ArmHasGicSystemRegisters (
|
|
VOID
|
|
);
|
|
|
|
/** Checks if CCIDX is implemented.
|
|
|
|
@retval TRUE CCIDX is implemented.
|
|
@retval FALSE CCIDX is not implemented.
|
|
**/
|
|
BOOLEAN
|
|
EFIAPI
|
|
ArmHasCcidx (
|
|
VOID
|
|
);
|
|
|
|
#ifdef MDE_CPU_ARM
|
|
///
|
|
/// AArch32-only ID Register Helper functions
|
|
///
|
|
|
|
/**
|
|
Check whether the CPU supports the Security extensions
|
|
|
|
@return Whether the Security extensions are implemented
|
|
|
|
**/
|
|
BOOLEAN
|
|
EFIAPI
|
|
ArmHasSecurityExtensions (
|
|
VOID
|
|
);
|
|
|
|
#endif // MDE_CPU_ARM
|
|
|
|
#endif // ARM_LIB_H_
|