mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
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486 lines
15 KiB
ArmAsm
486 lines
15 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.
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# Copyright (c) 2016, Linaro Limited. All rights reserved.
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# Copyright (c) 2020, NUVIA Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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#include <Chipset/AArch64.h>
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#include <AsmMacroIoLibV8.h>
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.set CTRL_M_BIT, (1 << 0)
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.set CTRL_A_BIT, (1 << 1)
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.set CTRL_C_BIT, (1 << 2)
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.set CTRL_SA_BIT, (1 << 3)
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.set CTRL_I_BIT, (1 << 12)
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.set CTRL_V_BIT, (1 << 12)
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.set CPACR_VFP_BITS, (3 << 20)
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ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)
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dc ivac, x0 // Invalidate single data cache line
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ret
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ASM_FUNC(ArmCleanDataCacheEntryByMVA)
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dc cvac, x0 // Clean single data cache line
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ret
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ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)
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dc cvau, x0 // Clean single data cache line to PoU
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ret
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ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)
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ic ivau, x0 // Invalidate single instruction cache line to PoU
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ret
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ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
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dc civac, x0 // Clean and invalidate single data cache line
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ret
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ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)
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dc isw, x0 // Invalidate this line
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ret
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ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)
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dc cisw, x0 // Clean and Invalidate this line
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ret
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ASM_FUNC(ArmCleanDataCacheEntryBySetWay)
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dc csw, x0 // Clean this line
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ret
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ASM_FUNC(ArmInvalidateInstructionCache)
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ic iallu // Invalidate entire instruction cache
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dsb sy
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isb
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ret
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ASM_FUNC(ArmEnableMmu)
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EL1_OR_EL2_OR_EL3(x1)
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1: mrs x0, sctlr_el1 // Read System control register EL1
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b 4f
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2: mrs x0, sctlr_el2 // Read System control register EL2
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b 4f
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3: mrs x0, sctlr_el3 // Read System control register EL3
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4: orr x0, x0, #CTRL_M_BIT // Set MMU enable bit
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EL1_OR_EL2_OR_EL3(x1)
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1: tlbi vmalle1
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dsb nsh
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isb
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msr sctlr_el1, x0 // Write back
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b 4f
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2: tlbi alle2
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dsb nsh
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isb
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msr sctlr_el2, x0 // Write back
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b 4f
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3: tlbi alle3
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dsb nsh
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isb
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msr sctlr_el3, x0 // Write back
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4: isb
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ret
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ASM_FUNC(ArmDisableMmu)
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EL1_OR_EL2_OR_EL3(x1)
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1: mrs x0, sctlr_el1 // Read System Control Register EL1
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b 4f
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2: mrs x0, sctlr_el2 // Read System Control Register EL2
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b 4f
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3: mrs x0, sctlr_el3 // Read System Control Register EL3
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4: and x0, x0, #~CTRL_M_BIT // Clear MMU enable bit
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EL1_OR_EL2_OR_EL3(x1)
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1: msr sctlr_el1, x0 // Write back
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tlbi vmalle1
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b 4f
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2: msr sctlr_el2, x0 // Write back
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tlbi alle2
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b 4f
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3: msr sctlr_el3, x0 // Write back
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tlbi alle3
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4: dsb sy
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isb
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ret
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ASM_FUNC(ArmDisableCachesAndMmu)
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EL1_OR_EL2_OR_EL3(x1)
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1: mrs x0, sctlr_el1 // Get control register EL1
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b 4f
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2: mrs x0, sctlr_el2 // Get control register EL2
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b 4f
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3: mrs x0, sctlr_el3 // Get control register EL3
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4: mov x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT) // Disable MMU, D & I caches
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and x0, x0, x1
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EL1_OR_EL2_OR_EL3(x1)
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1: msr sctlr_el1, x0 // Write back control register
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b 4f
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2: msr sctlr_el2, x0 // Write back control register
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b 4f
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3: msr sctlr_el3, x0 // Write back control register
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4: dsb sy
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isb
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ret
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ASM_FUNC(ArmMmuEnabled)
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EL1_OR_EL2_OR_EL3(x1)
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1: mrs x0, sctlr_el1 // Get control register EL1
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b 4f
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2: mrs x0, sctlr_el2 // Get control register EL2
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b 4f
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3: mrs x0, sctlr_el3 // Get control register EL3
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4: and x0, x0, #CTRL_M_BIT
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ret
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ASM_FUNC(ArmEnableDataCache)
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EL1_OR_EL2_OR_EL3(x1)
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1: mrs x0, sctlr_el1 // Get control register EL1
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b 4f
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2: mrs x0, sctlr_el2 // Get control register EL2
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b 4f
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3: mrs x0, sctlr_el3 // Get control register EL3
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4: orr x0, x0, #CTRL_C_BIT // Set C bit
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EL1_OR_EL2_OR_EL3(x1)
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1: msr sctlr_el1, x0 // Write back control register
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b 4f
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2: msr sctlr_el2, x0 // Write back control register
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b 4f
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3: msr sctlr_el3, x0 // Write back control register
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4: dsb sy
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isb
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ret
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ASM_FUNC(ArmDisableDataCache)
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EL1_OR_EL2_OR_EL3(x1)
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1: mrs x0, sctlr_el1 // Get control register EL1
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b 4f
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2: mrs x0, sctlr_el2 // Get control register EL2
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b 4f
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3: mrs x0, sctlr_el3 // Get control register EL3
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4: and x0, x0, #~CTRL_C_BIT // Clear C bit
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EL1_OR_EL2_OR_EL3(x1)
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1: msr sctlr_el1, x0 // Write back control register
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b 4f
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2: msr sctlr_el2, x0 // Write back control register
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b 4f
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3: msr sctlr_el3, x0 // Write back control register
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4: dsb sy
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isb
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ret
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ASM_FUNC(ArmEnableInstructionCache)
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EL1_OR_EL2_OR_EL3(x1)
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1: mrs x0, sctlr_el1 // Get control register EL1
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b 4f
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2: mrs x0, sctlr_el2 // Get control register EL2
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b 4f
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3: mrs x0, sctlr_el3 // Get control register EL3
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4: orr x0, x0, #CTRL_I_BIT // Set I bit
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EL1_OR_EL2_OR_EL3(x1)
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1: msr sctlr_el1, x0 // Write back control register
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b 4f
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2: msr sctlr_el2, x0 // Write back control register
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b 4f
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3: msr sctlr_el3, x0 // Write back control register
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4: dsb sy
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isb
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ret
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ASM_FUNC(ArmDisableInstructionCache)
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EL1_OR_EL2_OR_EL3(x1)
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1: mrs x0, sctlr_el1 // Get control register EL1
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b 4f
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2: mrs x0, sctlr_el2 // Get control register EL2
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b 4f
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3: mrs x0, sctlr_el3 // Get control register EL3
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4: and x0, x0, #~CTRL_I_BIT // Clear I bit
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EL1_OR_EL2_OR_EL3(x1)
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1: msr sctlr_el1, x0 // Write back control register
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b 4f
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2: msr sctlr_el2, x0 // Write back control register
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b 4f
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3: msr sctlr_el3, x0 // Write back control register
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4: dsb sy
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isb
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ret
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ASM_FUNC(ArmEnableAlignmentCheck)
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EL1_OR_EL2(x1)
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1: mrs x0, sctlr_el1 // Get control register EL1
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b 3f
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2: mrs x0, sctlr_el2 // Get control register EL2
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3: orr x0, x0, #CTRL_A_BIT // Set A (alignment check) bit
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EL1_OR_EL2(x1)
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1: msr sctlr_el1, x0 // Write back control register
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b 3f
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2: msr sctlr_el2, x0 // Write back control register
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3: dsb sy
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isb
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ret
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ASM_FUNC(ArmDisableAlignmentCheck)
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EL1_OR_EL2_OR_EL3(x1)
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1: mrs x0, sctlr_el1 // Get control register EL1
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b 4f
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2: mrs x0, sctlr_el2 // Get control register EL2
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b 4f
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3: mrs x0, sctlr_el3 // Get control register EL3
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4: and x0, x0, #~CTRL_A_BIT // Clear A (alignment check) bit
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EL1_OR_EL2_OR_EL3(x1)
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1: msr sctlr_el1, x0 // Write back control register
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b 4f
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2: msr sctlr_el2, x0 // Write back control register
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b 4f
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3: msr sctlr_el3, x0 // Write back control register
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4: dsb sy
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isb
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ret
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ASM_FUNC(ArmEnableStackAlignmentCheck)
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EL1_OR_EL2(x1)
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1: mrs x0, sctlr_el1 // Get control register EL1
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b 3f
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2: mrs x0, sctlr_el2 // Get control register EL2
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3: orr x0, x0, #CTRL_SA_BIT // Set SA (stack alignment check) bit
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EL1_OR_EL2(x1)
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1: msr sctlr_el1, x0 // Write back control register
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b 3f
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2: msr sctlr_el2, x0 // Write back control register
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3: dsb sy
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isb
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ret
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ASM_FUNC(ArmDisableStackAlignmentCheck)
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EL1_OR_EL2_OR_EL3(x1)
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1: mrs x0, sctlr_el1 // Get control register EL1
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b 4f
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2: mrs x0, sctlr_el2 // Get control register EL2
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b 4f
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3: mrs x0, sctlr_el3 // Get control register EL3
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4: bic x0, x0, #CTRL_SA_BIT // Clear SA (stack alignment check) bit
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EL1_OR_EL2_OR_EL3(x1)
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1: msr sctlr_el1, x0 // Write back control register
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b 4f
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2: msr sctlr_el2, x0 // Write back control register
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b 4f
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3: msr sctlr_el3, x0 // Write back control register
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4: dsb sy
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isb
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ret
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// Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now
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ASM_FUNC(ArmEnableBranchPrediction)
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ret
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// Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.
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ASM_FUNC(ArmDisableBranchPrediction)
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ret
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ASM_FUNC(AArch64AllDataCachesOperation)
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// We can use regs 0-7 and 9-15 without having to save/restore.
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// Save our link register on the stack. - The stack must always be quad-word aligned
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stp x29, x30, [sp, #-16]!
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mov x29, sp
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mov x1, x0 // Save Function call in x1
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mrs x6, clidr_el1 // Read EL1 CLIDR
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and x3, x6, #0x7000000 // Mask out all but Level of Coherency (LoC)
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lsr x3, x3, #23 // Left align cache level value - the level is shifted by 1 to the
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// right to ease the access to CSSELR and the Set/Way operation.
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cbz x3, L_Finished // No need to clean if LoC is 0
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mov x10, #0 // Start clean at cache level 0
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Loop1:
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add x2, x10, x10, lsr #1 // Work out 3x cachelevel for cache info
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lsr x12, x6, x2 // bottom 3 bits are the Cache type for this level
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and x12, x12, #7 // get those 3 bits alone
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cmp x12, #2 // what cache at this level?
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b.lt L_Skip // no cache or only instruction cache at this level
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msr csselr_el1, x10 // write the Cache Size selection register with current level (CSSELR)
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isb // isb to sync the change to the CacheSizeID reg
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mrs x12, ccsidr_el1 // reads current Cache Size ID register (CCSIDR)
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and x2, x12, #0x7 // extract the line length field
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add x2, x2, #4 // add 4 for the line length offset (log2 16 bytes)
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mov x4, #0x400
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sub x4, x4, #1
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and x4, x4, x12, lsr #3 // x4 is the max number on the way size (right aligned)
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clz w5, w4 // w5 is the bit position of the way size increment
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mov x7, #0x00008000
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sub x7, x7, #1
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and x7, x7, x12, lsr #13 // x7 is the max number of the index size (right aligned)
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Loop2:
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mov x9, x4 // x9 working copy of the max way size (right aligned)
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Loop3:
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lsl x11, x9, x5
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orr x0, x10, x11 // factor in the way number and cache number
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lsl x11, x7, x2
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orr x0, x0, x11 // factor in the index number
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blr x1 // Goto requested cache operation
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subs x9, x9, #1 // decrement the way number
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b.ge Loop3
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subs x7, x7, #1 // decrement the index
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b.ge Loop2
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L_Skip:
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add x10, x10, #2 // increment the cache number
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cmp x3, x10
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b.gt Loop1
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L_Finished:
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dsb sy
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isb
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ldp x29, x30, [sp], #0x10
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ret
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ASM_FUNC(ArmDataMemoryBarrier)
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dmb sy
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ret
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ASM_FUNC(ArmDataSynchronizationBarrier)
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dsb sy
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ret
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ASM_FUNC(ArmInstructionSynchronizationBarrier)
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isb
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ret
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ASM_FUNC(ArmWriteVBar)
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EL1_OR_EL2_OR_EL3(x1)
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1: msr vbar_el1, x0 // Set the Address of the EL1 Vector Table in the VBAR register
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b 4f
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2: msr vbar_el2, x0 // Set the Address of the EL2 Vector Table in the VBAR register
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b 4f
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3: msr vbar_el3, x0 // Set the Address of the EL3 Vector Table in the VBAR register
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4: isb
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ret
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ASM_FUNC(ArmReadVBar)
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EL1_OR_EL2_OR_EL3(x1)
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1: mrs x0, vbar_el1 // Set the Address of the EL1 Vector Table in the VBAR register
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ret
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2: mrs x0, vbar_el2 // Set the Address of the EL2 Vector Table in the VBAR register
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ret
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3: mrs x0, vbar_el3 // Set the Address of the EL3 Vector Table in the VBAR register
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ret
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ASM_FUNC(ArmEnableVFP)
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// Check whether floating-point is implemented in the processor.
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mov x1, x30 // Save LR
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bl ArmReadIdAA64Pfr0 // Read EL1 Processor Feature Register (PFR0)
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mov x30, x1 // Restore LR
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ubfx x0, x0, #16, #4 // Extract the FP bits 16:19
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cmp x0, #0xF // Check if FP bits are '1111b',
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// i.e. Floating Point not implemented
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b.eq 4f // Exit when VFP is not implemented.
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// FVP is implemented.
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// Make sure VFP exceptions are not trapped (to any exception level).
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mrs x0, cpacr_el1 // Read EL1 Coprocessor Access Control Register (CPACR)
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orr x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1
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msr cpacr_el1, x0 // Write back EL1 Coprocessor Access Control Register (CPACR)
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mov x1, #AARCH64_CPTR_TFP // TFP Bit for trapping VFP Exceptions
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EL1_OR_EL2_OR_EL3(x2)
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1:ret // Not configurable in EL1
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2:mrs x0, cptr_el2 // Disable VFP traps to EL2
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bic x0, x0, x1
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msr cptr_el2, x0
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ret
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3:mrs x0, cptr_el3 // Disable VFP traps to EL3
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bic x0, x0, x1
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msr cptr_el3, x0
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4:ret
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ASM_FUNC(ArmCallWFI)
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wfi
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ret
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ASM_FUNC(ArmReadIdAA64Mmfr2)
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mrs x0, ID_AA64MMFR2_EL1 // read EL1 MMFR2
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ret
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ASM_FUNC(ArmReadMpidr)
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mrs x0, mpidr_el1 // read EL1 MPIDR
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ret
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// Keep old function names for C compatibility for now. Change later?
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ASM_FUNC(ArmReadTpidrurw)
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mrs x0, tpidr_el0 // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
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ret
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// Keep old function names for C compatibility for now. Change later?
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ASM_FUNC(ArmWriteTpidrurw)
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msr tpidr_el0, x0 // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
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ret
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// Arch timers are mandatory on AArch64
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ASM_FUNC(ArmIsArchTimerImplemented)
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mov x0, #1
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ret
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ASM_FUNC(ArmReadIdAA64Pfr0)
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mrs x0, id_aa64pfr0_el1 // Read ID_AA64PFR0 Register
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ret
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// VOID ArmWriteHcr(UINTN Hcr)
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ASM_FUNC(ArmWriteHcr)
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msr hcr_el2, x0 // Write the passed HCR value
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ret
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// UINTN ArmReadHcr(VOID)
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ASM_FUNC(ArmReadHcr)
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mrs x0, hcr_el2
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ret
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// UINTN ArmReadCurrentEL(VOID)
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ASM_FUNC(ArmReadCurrentEL)
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mrs x0, CurrentEL
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ret
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// UINT32 ArmReadCntHctl(VOID)
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ASM_FUNC(ArmReadCntHctl)
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mrs x0, cnthctl_el2
|
|
ret
|
|
|
|
// VOID ArmWriteCntHctl(UINT32 CntHctl)
|
|
ASM_FUNC(ArmWriteCntHctl)
|
|
msr cnthctl_el2, x0
|
|
ret
|
|
|
|
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|