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116 lines
5.5 KiB
C
116 lines
5.5 KiB
C
/** @file
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PCI Host Bridge Library consumed by PciHostBridgeDxe driver returning
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the platform specific information about the PCI Host Bridge.
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __PCI_HOST_BRIDGE_LIB_H__
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#define __PCI_HOST_BRIDGE_LIB_H__
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//
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// (Base > Limit) indicates an aperture is not available.
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//
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typedef struct {
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//
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// Base and Limit are the device address instead of host address when
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// Translation is not zero
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//
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UINT64 Base;
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UINT64 Limit;
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//
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// According to UEFI 2.7, Device Address = Host Address + Translation,
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// so Translation = Device Address - Host Address.
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// On platforms where Translation is not zero, the subtraction is probably to
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// be performed with UINT64 wrap-around semantics, for we may translate an
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// above-4G host address into a below-4G device address for legacy PCIe device
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// compatibility.
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//
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// NOTE: The alignment of Translation is required to be larger than any BAR
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// alignment in the same root bridge, so that the same alignment can be
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// applied to both device address and host address, which simplifies the
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// situation and makes the current resource allocation code in generic PCI
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// host bridge driver still work.
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//
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UINT64 Translation;
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} PCI_ROOT_BRIDGE_APERTURE;
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typedef struct {
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UINT32 Segment; ///< Segment number.
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UINT64 Supports; ///< Supported attributes.
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///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
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///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
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UINT64 Attributes; ///< Initial attributes.
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///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
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///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
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BOOLEAN DmaAbove4G; ///< DMA above 4GB memory.
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///< Set to TRUE when root bridge supports DMA above 4GB memory.
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BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the root bridge supports
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///< Extended (4096-byte) Configuration Space.
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///< When TRUE, the root bridge supports
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///< 256-byte Configuration Space only.
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BOOLEAN ResourceAssigned; ///< Resource assignment status of the root bridge.
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///< Set to TRUE if Bus/IO/MMIO resources for root bridge have been assigned.
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UINT64 AllocationAttributes; ///< Allocation attributes.
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///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and
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///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()
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///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
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PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which can be used by the root bridge.
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PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which can be used by the root bridge.
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PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below 4GB which can be used by the root bridge.
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PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture above 4GB which can be used by the root bridge.
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PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.
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PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.
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EFI_DEVICE_PATH_PROTOCOL *DevicePath; ///< Device path.
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} PCI_ROOT_BRIDGE;
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/**
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Return all the root bridge instances in an array.
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@param Count Return the count of root bridge instances.
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@return All the root bridge instances in an array.
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The array should be passed into PciHostBridgeFreeRootBridges()
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when it's not used.
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**/
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PCI_ROOT_BRIDGE *
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EFIAPI
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PciHostBridgeGetRootBridges (
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UINTN *Count
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);
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/**
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Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
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@param Bridges The root bridge instances array.
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@param Count The count of the array.
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**/
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VOID
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EFIAPI
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PciHostBridgeFreeRootBridges (
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PCI_ROOT_BRIDGE *Bridges,
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UINTN Count
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);
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/**
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Inform the platform that the resource conflict happens.
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@param HostBridgeHandle Handle of the Host Bridge.
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@param Configuration Pointer to PCI I/O and PCI memory resource descriptors.
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The Configuration contains the resources for all the
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root bridges. The resource for each root bridge is
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terminated with END descriptor and an additional END
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is appended indicating the end of the entire resources.
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The resource descriptor field values follow the description
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in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.SubmitResources().
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**/
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VOID
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EFIAPI
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PciHostBridgeResourceConflict (
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EFI_HANDLE HostBridgeHandle,
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VOID *Configuration
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);
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#endif
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