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89 lines
3.7 KiB
C
89 lines
3.7 KiB
C
/** @file
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Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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VirtualMemory.h
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Abstract:
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Revision History:
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**/
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#ifndef _VIRTUAL_MEMORY_H_
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#define _VIRTUAL_MEMORY_H_
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#pragma pack(1)
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//
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// Page Directory Entry 4K
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//
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typedef union {
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struct {
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UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT32 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT32 MustBeZero:3; // Must Be Zero
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UINT32 Available:3; // Available for use by system software
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UINT32 PageTableBaseAddress:20; // Page Table Base Address
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} Bits;
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UINT32 Uint32;
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} IA32_PAGE_DIRECTORY_ENTRY_4K;
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//
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// Page Table Entry 4K
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//
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typedef union {
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struct {
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UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT32 Accessed:1; // 0 = Not accessed (cleared by software), 1 = Accessed (set by CPU)
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UINT32 Dirty:1; // 0 = Not written to (cleared by software), 1 = Written to (set by CPU)
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UINT32 PAT:1; // 0 = Disable PAT, 1 = Enable PAT
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UINT32 Global:1; // Ignored
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UINT32 Available:3; // Available for use by system software
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UINT32 PageTableBaseAddress:20; // Page Table Base Address
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} Bits;
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UINT32 Uint32;
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} IA32_PAGE_TABLE_ENTRY_4K;
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//
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// Page Table Entry 4M
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//
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typedef union {
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struct {
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UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT32 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT32 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT32 MustBe1:1; // Must be 1
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UINT32 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT32 Available:3; // Available for use by system software
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UINT32 PAT:1; //
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UINT32 MustBeZero:9; // Must be zero;
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UINT32 PageTableBaseAddress:10; // Page Table Base Address
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} Bits;
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UINT32 Uint32;
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} IA32_PAGE_TABLE_ENTRY_4M;
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#pragma pack()
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#endif
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