mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-11-27 12:15:19 +01:00
350 lines
14 KiB
C
350 lines
14 KiB
C
/*
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* usbfix.c
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*
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* Created by Slice on 21.09.11.
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*
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* based on works by mackerintel 2008, orByte 2006, Signal64, THeKiNG
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*/
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#include "Platform.h"
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#ifndef DEBUG_ALL
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#define DEBUG_USB 0
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#else
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#define DEBUG_USB DEBUG_ALL
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#endif
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#if DEBUG_USB == 0
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#define DBG(...)
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#else
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#define DBG(...) DebugLog(DEBUG_USB, __VA_ARGS__)
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#endif
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#define PCI_IF_OHCI 0x10
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#define PCI_IF_XHCI 0x30
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#define OHCI_CTRL_MASK (1 << 9)
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#define OHCI_CONTROL 0x04
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#define OHCI_INTRDISABLE 0x14
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#define OHCI_INTRSTATUS 0x0c
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EFI_STATUS
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FixOwnership(VOID)
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/*++
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Routine Description:
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Disable the USB legacy Support in all Ehci and Uhci.
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This function assume all PciIo handles have been created in system.
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Slice - added also OHCI and more advanced algo. Better then known to Intel and Apple :)
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Arguments:
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None
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Returns:
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EFI_SUCCESS
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EFI_NOT_FOUND
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--*/
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{
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EFI_STATUS Status;
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EFI_HANDLE *HandleArray = NULL;
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UINTN HandleArrayCount = 0;
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UINTN Index;
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EFI_PCI_IO_PROTOCOL *PciIo;
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PCI_TYPE00 Pci;
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UINT16 Command;
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UINT32 HcCapParams;
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UINT32 ExtendCap;
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UINT32 Value;
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INT32 TimeOut;
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UINT32 Base;
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UINT32 PortBase;
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volatile UINT32 opaddr;
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// UINT8 eecp;
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UINT32 usbcmd, usbsts, usbintr;
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UINT32 usblegsup, usblegctlsts;
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UINTN isOSowned;
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UINTN isBIOSowned;
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BOOLEAN isOwnershipConflict;
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//
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// Find the usb host controller
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//
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Status = gBS->LocateHandleBuffer (
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ByProtocol,
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&gEfiPciIoProtocolGuid,
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NULL,
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&HandleArrayCount,
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&HandleArray
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);
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if (!EFI_ERROR (Status)) {
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for (Index = 0; Index < HandleArrayCount; Index++) {
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Status = gBS->HandleProtocol (
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HandleArray[Index],
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&gEfiPciIoProtocolGuid,
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(VOID **)&PciIo
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);
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if (!EFI_ERROR (Status)) {
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//
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// Find the USB host controller
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//
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Status = PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint32,
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0,
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sizeof (Pci) / sizeof (UINT32),
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&Pci
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);
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if (!EFI_ERROR (Status)) {
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if ((PCI_CLASS_SERIAL == Pci.Hdr.ClassCode[2]) &&
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(PCI_CLASS_SERIAL_USB == Pci.Hdr.ClassCode[1])) {
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switch (Pci.Hdr.ClassCode[0]) {
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case PCI_IF_UHCI:
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//
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// Found the UHCI, then disable the legacy support
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//
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Base = 0;
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Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, 0x20, 1, &Base);
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PortBase = (Base >> 5) & 0x07ff;
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DBG("USB UHCI Base=%x PortBase=%x\n", Base, PortBase);
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Command = 0x8f00;
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Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0xC0, 1, &Command);
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if (PortBase) {
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IoWrite16 (PortBase, 0x0002);
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gBS->Stall (500);
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IoWrite16 (PortBase+4, 0);
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gBS->Stall (500);
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IoWrite16 (PortBase, 0);
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}
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MsgLog("USB UHCI reset for device %04x\n", Pci.Hdr.DeviceId);
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break;
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/* case PCI_IF_OHCI:
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Base = 0;
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Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, 0x10, 1, &Base);
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Command = *(UINT32 *)(UINTN)(Base + OHCI_CONTROL);
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*(UINT32 *)(UINTN)(Base + OHCI_CONTROL) = Command & OHCI_CTRL_MASK;
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Command = *(UINT32 *)(UINTN)(Base + OHCI_CONTROL);
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MsgLog("USB OHCI reset for device %04x control=0x%x\n", Pci.Hdr.DeviceId, Command);
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break;*/
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case PCI_IF_EHCI:
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//Slice - the algo is reworked from Chameleon
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// it looks like redundant but it works so I will not reduce it
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//
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// Found the EHCI, then disable the legacy support
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//
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Value = 0x0002;
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PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x04, 1, &Value);
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Base = 0;
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Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, 0x10, 1, &Base);
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if (*((UINT8*)(UINTN)Base) < 0x0C) {
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DBG("Config space too small: no legacy implementation\n");
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break;
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}
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// opaddr = Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0)
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opaddr = Base + *((UINT8*)(UINTN)(Base));
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// eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8
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//UEFI
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Status = PciIo->Mem.Read (
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PciIo,
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EfiPciIoWidthUint32,
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0, //EHC_BAR_INDEX
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(UINT64) 0x08, //EHC_HCCPARAMS_OFFSET
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1,
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&HcCapParams
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);
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ExtendCap = (HcCapParams >> 8) & 0xFF;
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DBG("Base=%x Oper=%x eecp=%x\n", Base, opaddr, ExtendCap);
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usbcmd = *((UINT32*)(UINTN)(opaddr)); // Command Register
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usbsts = *((UINT32*)(UINTN)(opaddr + 4)); // Status Register
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usbintr = *((UINT32*)(UINTN)(opaddr + 8)); // Interrupt Enable Register
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DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);
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// read PCI Config 32bit USBLEGSUP (eecp+0)
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Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &usblegsup);
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// informational only
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isBIOSowned = !!((usblegsup) & (1 << (16)));
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isOSowned = !!((usblegsup) & (1 << (24)));
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// read PCI Config 32bit USBLEGCTLSTS (eecp+4)
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &usblegctlsts);
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DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);
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//
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// Disable the SMI in USBLEGCTLSTS firstly
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//
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usblegctlsts &= 0xFFFF0000;
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PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &usblegctlsts);
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//double
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// if delay value is in milliseconds it doesn't appear to work.
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// setting value to anything up to 65535 does not add the expected delay here.
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gBS->Stall (500);
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usbcmd = *((UINT32*)(UINTN)(opaddr)); // Command Register
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usbsts = *((UINT32*)(UINTN)(opaddr + 4)); // Status Register
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usbintr = *((UINT32*)(UINTN)(opaddr + 8)); // Interrupt Enable Register
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DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);
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// clear registers to default
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usbcmd = (usbcmd & 0xffffff00);
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*((UINT32*)(UINTN)(opaddr)) = usbcmd;
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*((UINT32*)(UINTN)(opaddr + 8)) = 0; //usbintr - clear interrupt registers
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*((UINT32*)(UINTN)(opaddr + 4)) = 0x1000; //usbsts - clear status registers
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Value = 1;
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PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);
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// get the results
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usbcmd = *((UINT32*)(UINTN)(opaddr)); // Command Register
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usbsts = *((UINT32*)(UINTN)(opaddr + 4)); // Status Register
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usbintr = *((UINT32*)(UINTN)(opaddr + 8)); // Interrupt Enable Register
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DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);
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// read 32bit USBLEGSUP (eecp+0)
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &usblegsup);
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// informational only
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isBIOSowned = !!((usblegsup) & (1 << (16)));
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isOSowned = !!((usblegsup) & (1 << (24)));
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// read 32bit USBLEGCTLSTS (eecp+4)
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &usblegctlsts);
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DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);
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MsgLog("Legacy USB Off Done\n");
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//
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// Get EHCI Ownership from legacy bios
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//
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &usblegsup);
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isOwnershipConflict = isBIOSowned && isOSowned;
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if (isOwnershipConflict) {
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DBG("EHCI - Ownership conflict - attempting soft reset ...\n");
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Value = 0;
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PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ExtendCap + 3, 1, &Value);
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TimeOut = 40;
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while (TimeOut--) {
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gBS->Stall (500);
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);
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if ((Value & 0x01000000) == 0x0) {
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break;
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}
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}
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}
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);
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Value |= (0x1 << 24);
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PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);
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TimeOut = 40;
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while (TimeOut--) {
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gBS->Stall (500);
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);
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if ((Value & 0x00010000) == 0x0) {
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break;
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}
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}
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isOwnershipConflict = ((Value & 0x00010000) != 0x0);
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if (isOwnershipConflict) {
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// Soft reset has failed. Assume SMI being ignored
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// Hard reset
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DBG("Soft reset has failed - attempting hard reset ...\n");
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Value = 0;
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PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ExtendCap + 2, 1, &Value);
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TimeOut = 40;
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while (TimeOut--) {
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gBS->Stall (500);
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);
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if ((Value & 0x00010000) == 0x0) {
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break;
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}
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}
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// Disable further SMI events
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &usblegctlsts);
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usblegctlsts &= 0xFFFF0000;
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PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &usblegctlsts);
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}
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if (Value & 0x00010000) {
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MsgLog("EHCI controller unable to take control from BIOS\n");
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Status = EFI_NOT_FOUND; //Slice - why? :)
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break;
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}
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MsgLog("USB EHCI Ownership for device %04x value=%x\n", Pci.Hdr.DeviceId, Value);
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break;
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case PCI_IF_XHCI:
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//
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// Found the XHCI, then disable the legacy support, if present
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//
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Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint32, 0 /* BAR0 */, (UINT64) 0x10 /* HCCPARAMS1 */, 1, &HcCapParams);
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ExtendCap = EFI_ERROR(Status) ? 0 : ((HcCapParams >> 14) & 0x3FFFC);
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while (ExtendCap) {
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Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint32, 0 /* BAR0 */, (UINT64) ExtendCap, 1, &Value);
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if (EFI_ERROR(Status))
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break;
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if ((Value & 0xFF) == 1) {
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//
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// Do nothing if Bios Ownership clear
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//
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if (!(Value & (0x1 << 16)))
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break;
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Value |= (0x1 << 24);
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(VOID) PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, 0 /* BAR0 */, (UINT64) ExtendCap, 1, &Value);
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TimeOut = 40;
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while (TimeOut--) {
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gBS->Stall(500);
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Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint32, 0 /* BAR0 */, (UINT64) ExtendCap, 1, &Value);
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if (EFI_ERROR(Status) || !(Value & (0x1 << 16)))
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break;
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}
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//
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// Disable all SMI in USBLEGCTLSTS
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//
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Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint32, 0 /* BAR0 */, (UINT64) ExtendCap + 4, 1, &Value);
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if (EFI_ERROR(Status))
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break;
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Value &= 0x1F1FEE;
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Value |= 0xE0000000;
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(VOID) PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, 0 /* BAR0 */, (UINT64) ExtendCap + 4, 1, &Value);
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//
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// Clear all ownership
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//
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Status = PciIo->Mem.Read(PciIo, EfiPciIoWidthUint32, 0 /* BAR0 */, (UINT64) ExtendCap, 1, &Value);
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if (EFI_ERROR(Status))
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break;
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Value &= ~((0x1 << 24) | (0x1 << 16));
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(VOID) PciIo->Mem.Write(PciIo, EfiPciIoWidthUint32, 0 /* BAR0 */, (UINT64) ExtendCap, 1, &Value);
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break;
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} //Value & FF
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if (!(Value & 0xFF00))
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break;
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ExtendCap += ((Value >> 6) & 0x3FC);
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} //while ExtendCap
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break;
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default:
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break;
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} //switch class code
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}
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}
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}
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}
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} else {
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return Status;
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}
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gBS->FreePool (HandleArray);
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return Status;
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}
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