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189 lines
7.2 KiB
C
189 lines
7.2 KiB
C
/** @file
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This file defines the SPI Host Controller Protocol.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Revision Reference:
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This Protocol was introduced in UEFI PI Specification 1.6.
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**/
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#ifndef __SPI_HC_PROTOCOL_H__
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#define __SPI_HC_PROTOCOL_H__
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#include <Protocol/SpiConfiguration.h>
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#include <Protocol/SpiIo.h>
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///
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/// Global ID for the SPI Host Controller Protocol
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///
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#define EFI_SPI_HOST_GUID \
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{ 0xc74e5db2, 0xfa96, 0x4ae2, \
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{ 0xb3, 0x99, 0x15, 0x97, 0x7f, 0xe3, 0x0, 0x2d }}
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///
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/// EDK2-style name
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///
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#define EFI_SPI_HC_PROTOCOL_GUID EFI_SPI_HOST_GUID
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typedef struct _EFI_SPI_HC_PROTOCOL EFI_SPI_HC_PROTOCOL;
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/**
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Assert or deassert the SPI chip select.
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This routine is called at TPL_NOTIFY.
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Update the value of the chip select line for a SPI peripheral. The SPI bus
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layer calls this routine either in the board layer or in the SPI controller
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to manipulate the chip select pin at the start and end of a SPI transaction.
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@param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure.
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@param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure
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describing the SPI peripheral whose chip select pin
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is to be manipulated. The routine may access the
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ChipSelectParameter field to gain sufficient
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context to complete the operati on.
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@param[in] PinValue The value to be applied to the chip select line of
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the SPI peripheral.
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@retval EFI_SUCCESS The chip select was set as requested
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@retval EFI_NOT_READY Support for the chip select is not properly
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initialized
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@retval EFI_INVALID_PARAMETER The ChipSeLect value or its contents are
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invalid
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**/
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typedef EFI_STATUS
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(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT) (
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IN CONST EFI_SPI_HC_PROTOCOL *This,
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IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,
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IN BOOLEAN PinValue
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);
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/**
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Set up the clock generator to produce the correct clock frequency, phase and
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polarity for a SPI chip.
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This routine is called at TPL_NOTIFY.
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This routine updates the clock generator to generate the correct frequency
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and polarity for the SPI clock.
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@param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure.
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@param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from
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which the routine can access the ClockParameter,
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ClockPhase and ClockPolarity fields. The routine
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also has access to the names for the SPI bus and
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chip which can be used during debugging.
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@param[in] ClockHz Pointer to the requested clock frequency. The SPI
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host controller will choose a supported clock
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frequency which is less then or equal to this
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value. Specify zero to turn the clock generator
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off. The actual clock frequency supported by the
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SPI host controller will be returned.
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@retval EFI_SUCCESS The clock was set up successfully
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@retval EFI_UNSUPPORTED The SPI controller was not able to support the
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frequency requested by ClockHz
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**/
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typedef EFI_STATUS
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(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK) (
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IN CONST EFI_SPI_HC_PROTOCOL *This,
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IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,
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IN UINT32 *ClockHz
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);
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/**
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Perform the SPI transaction on the SPI peripheral using the SPI host
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controller.
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This routine is called at TPL_NOTIFY.
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This routine synchronously returns EFI_SUCCESS indicating that the
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asynchronous SPI transaction was started. The routine then waits for
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completion of the SPI transaction prior to returning the final transaction
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status.
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@param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure.
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@param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing
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the description of the SPI transaction to perform.
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@retval EFI_SUCCESS The transaction completed successfully
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@retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid,
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or the BusTransaction->ReadinBytes value is
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invalid
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@retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is
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unsupported
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**/
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typedef EFI_STATUS
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(EFIAPI *EFI_SPI_HC_PROTOCOL_TRANSACTION) (
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IN CONST EFI_SPI_HC_PROTOCOL *This,
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IN EFI_SPI_BUS_TRANSACTION *BusTransaction
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);
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///
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/// Support a SPI data transaction between the SPI controller and a SPI chip.
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///
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struct _EFI_SPI_HC_PROTOCOL {
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///
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/// Host control attributes, may have zero or more of the following set:
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/// * HC_SUPPORTS_WRITE_ONLY_OPERATIONS
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/// * HC_SUPPORTS_READ_ONLY_OPERATIONS
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/// * HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS
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/// * HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS
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/// - The SPI host controller requires the transmit frame to be in most
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/// significant bits instead of least significant bits.The host driver
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/// will adjust the frames if necessary.
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/// * HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS
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/// - The SPI host controller places the receive frame to be in most
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/// significant bits instead of least significant bits.The host driver
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/// will adjust the frames to be in the least significant bits if
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/// necessary.
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/// * HC_SUPPORTS_2_BIT_DATA_BUS_W1DTH
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/// - The SPI controller supports a 2 - bit data bus
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/// * HC_SUPPORTS_4_B1T_DATA_BUS_WIDTH
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/// - The SPI controller supports a 4 - bit data bus
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/// * HC_TRANSFER_SIZE_INCLUDES_OPCODE
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/// - Transfer size includes the opcode byte
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/// * HC_TRANSFER_SIZE_INCLUDES_ADDRESS
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/// - Transfer size includes the 3 address bytes
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/// The SPI host controller must support full - duplex (receive while
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/// sending) operation.The SPI host controller must support a 1 - bit bus
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/// width.
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///
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UINT32 Attributes;
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///
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/// Mask of frame sizes which the SPI host controller supports. Frame size of
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/// N-bits is supported when bit N-1 is set. The host controller must support
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/// a frame size of 8-bits.
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///
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UINT32 FrameSizeSupportMask;
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///
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/// Maximum transfer size in bytes: 1 - Oxffffffff
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///
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UINT32 MaximumTransferBytes;
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///
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/// Assert or deassert the SPI chip select.
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///
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EFI_SPI_HC_PROTOCOL_CHIP_SELECT ChipSelect;
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///
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/// Set up the clock generator to produce the correct clock frequency, phase
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/// and polarity for a SPI chip.
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///
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EFI_SPI_HC_PROTOCOL_CLOCK Clock;
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///
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/// Perform the SPI transaction on the SPI peripheral using the SPI host
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/// controller.
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///
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EFI_SPI_HC_PROTOCOL_TRANSACTION Transaction;
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};
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extern EFI_GUID gEfiSpiHcProtocolGuid;
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#endif // __SPI_HC_PROTOCOL_H__
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