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https://github.com/CloverHackyColor/CloverBootloader.git
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74 lines
2.1 KiB
ArmAsm
Executable File
74 lines
2.1 KiB
ArmAsm
Executable File
#------------------------------------------------------------------------------
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#*
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#* Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
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#* This program and the accompanying materials
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#* are licensed and made available under the terms and conditions of the BSD License
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#* which accompanies this distribution. The full text of the license may be found at
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#* http://opensource.org/licenses/bsd-license.php
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#*
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#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#*
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#*
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#------------------------------------------------------------------------------
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#
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# Float control word initial value:
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# all exceptions masked, double-precision, round-to-nearest
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#
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ASM_PFX(mFpuControlWord): .word 0x027F
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#
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# Multimedia-extensions control word:
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# all exceptions masked, round-to-nearest, flush to zero for masked underflow
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#
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ASM_PFX(mMmxControlWord): .long 0x01F80
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#
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# Initializes floating point units for requirement of UEFI specification.
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#
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# This function initializes floating-point control word to 0x027F (all exceptions
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# masked,double-precision, round-to-nearest) and multimedia-extensions control word
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# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
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# for masked underflow).
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#
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ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
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ASM_PFX(InitializeFloatingPointUnits):
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pushl %ebx
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#
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# Initialize floating point units
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#
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finit
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fldcw ASM_PFX(mFpuControlWord)
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#
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# Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
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# whether the processor supports SSE instruction.
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#
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movl $1, %eax
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cpuid
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btl $25, %edx
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jnc Done
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#
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# Set OSFXSR bit 9 in CR4
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#
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movl %cr4, %eax
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or $0x200, %eax
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movl %eax, %cr4
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#
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# The processor should support SSE instruction and we can use
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# ldmxcsr instruction
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#
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ldmxcsr ASM_PFX(mMmxControlWord)
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Done:
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popl %ebx
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ret
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#END
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