mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-12-19 15:37:40 +01:00
262 lines
8.0 KiB
C
262 lines
8.0 KiB
C
/** @file
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Set a IDT entry for debug purpose
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Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "ScriptExecute.h"
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//
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// 8 extra pages for PF handler.
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//
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#define EXTRA_PAGE_TABLE_PAGES 8
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#define IA32_PG_P BIT0
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#define IA32_PG_RW BIT1
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#define IA32_PG_PS BIT7
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UINT64 mPhyMask;
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VOID *mOriginalHandler;
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UINTN mPageFaultBuffer;
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UINTN mPageFaultIndex = 0;
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//
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// Store the uplink information for each page being used.
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//
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UINT64 *mPageFaultUplink[EXTRA_PAGE_TABLE_PAGES];
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/**
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Page fault handler.
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**/
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VOID
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EFIAPI
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PageFaultHandlerHook (
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VOID
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);
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/**
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Hook IDT with our page fault handler so that the on-demand paging works on page fault.
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@param IdtEntry a pointer to IDT entry
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**/
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VOID
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HookPageFaultHandler (
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IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
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)
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{
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UINT32 RegEax;
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UINT8 PhysicalAddressBits;
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UINTN PageFaultHandlerHookAddress;
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000008) {
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AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
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PhysicalAddressBits = (UINT8) RegEax;
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} else {
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PhysicalAddressBits = 36;
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}
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mPhyMask = LShiftU64 (1, PhysicalAddressBits) - 1;
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mPhyMask &= (1ull << 48) - SIZE_4KB;
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//
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// Set Page Fault entry to catch >4G access
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//
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PageFaultHandlerHookAddress = (UINTN)PageFaultHandlerHook;
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mOriginalHandler = (VOID *)(UINTN)(LShiftU64 (IdtEntry->Bits.OffsetUpper, 32) + IdtEntry->Bits.OffsetLow + (IdtEntry->Bits.OffsetHigh << 16));
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IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;
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IdtEntry->Bits.Selector = (UINT16)AsmReadCs ();
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IdtEntry->Bits.Reserved_0 = 0;
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IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
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IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);
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IdtEntry->Bits.OffsetUpper = (UINT32)(PageFaultHandlerHookAddress >> 32);
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IdtEntry->Bits.Reserved_1 = 0;
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if (mPage1GSupport) {
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mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(2);
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}else {
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mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(6);
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}
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ZeroMem (mPageFaultUplink, sizeof (mPageFaultUplink));
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}
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/**
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The function will check if current waking vector is long mode.
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@param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT
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@retval TRUE Current context need long mode waking vector.
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@retval FALSE Current context need not long mode waking vector.
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**/
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BOOLEAN
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IsLongModeWakingVector (
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IN ACPI_S3_CONTEXT *AcpiS3Context
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)
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{
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EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *Facs;
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Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable));
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if ((Facs == NULL) ||
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(Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) ||
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((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) {
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// Something wrong with FACS
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return FALSE;
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}
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if (Facs->XFirmwareWakingVector != 0) {
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if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&
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((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&
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((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {
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// Both BIOS and OS wants 64bit vector
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if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
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return TRUE;
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}
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}
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}
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return FALSE;
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}
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/**
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Set a IDT entry for interrupt vector 3 for debug purpose.
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@param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT
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**/
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VOID
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SetIdtEntry (
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IN ACPI_S3_CONTEXT *AcpiS3Context
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)
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{
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IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
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IA32_DESCRIPTOR *IdtDescriptor;
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UINTN S3DebugBuffer;
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EFI_STATUS Status;
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//
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// Restore IDT for debug
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//
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IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);
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AsmWriteIdtr (IdtDescriptor);
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//
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// Setup the default CPU exception handlers
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//
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Status = InitializeCpuExceptionHandlers (NULL);
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ASSERT_EFI_ERROR (Status);
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DEBUG_CODE (
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//
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// Update IDT entry INT3 if the instruction is valid in it
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//
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S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);
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if (*(UINTN *)S3DebugBuffer != (UINTN) -1) {
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IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (3 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));
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IdtEntry->Bits.OffsetLow = (UINT16)S3DebugBuffer;
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IdtEntry->Bits.Selector = (UINT16)AsmReadCs ();
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IdtEntry->Bits.Reserved_0 = 0;
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IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
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IdtEntry->Bits.OffsetHigh = (UINT16)(S3DebugBuffer >> 16);
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IdtEntry->Bits.OffsetUpper = (UINT32)(S3DebugBuffer >> 32);
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IdtEntry->Bits.Reserved_1 = 0;
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}
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);
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//
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// If both BIOS and OS wants long mode waking vector,
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// S3ResumePei should have established 1:1 Virtual to Physical identity mapping page table,
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// no need to hook page fault handler.
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//
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if (!IsLongModeWakingVector (AcpiS3Context)) {
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IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (14 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));
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HookPageFaultHandler (IdtEntry);
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}
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}
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/**
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Acquire page for page fault.
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@param[in, out] Uplink Pointer to up page table entry.
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**/
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VOID
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AcquirePage (
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IN OUT UINT64 *Uplink
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)
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{
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UINTN Address;
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Address = mPageFaultBuffer + EFI_PAGES_TO_SIZE (mPageFaultIndex);
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ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1));
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//
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// Cut the previous uplink if it exists and wasn't overwritten.
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//
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if ((mPageFaultUplink[mPageFaultIndex] != NULL) &&
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((*mPageFaultUplink[mPageFaultIndex] & ~mAddressEncMask & mPhyMask) == Address)) {
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*mPageFaultUplink[mPageFaultIndex] = 0;
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}
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//
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// Link & Record the current uplink.
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//
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*Uplink = Address | mAddressEncMask | IA32_PG_P | IA32_PG_RW;
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mPageFaultUplink[mPageFaultIndex] = Uplink;
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mPageFaultIndex = (mPageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;
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}
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/**
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The page fault handler that on-demand read >4G memory/MMIO.
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@retval TRUE The page fault is correctly handled.
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@retval FALSE The page fault is not handled and is passed through to original handler.
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**/
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BOOLEAN
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EFIAPI
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PageFaultHandler (
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VOID
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)
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{
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UINT64 *PageTable;
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UINT64 PFAddress;
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UINTN PTIndex;
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PFAddress = AsmReadCr2 ();
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DEBUG ((DEBUG_INFO, "BootScript - PageFaultHandler: Cr2 - %lx\n", PFAddress));
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if (PFAddress >= mPhyMask + SIZE_4KB) {
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return FALSE;
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}
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PFAddress &= mPhyMask;
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PageTable = (UINT64*)(UINTN)(AsmReadCr3 () & mPhyMask);
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PTIndex = BitFieldRead64 (PFAddress, 39, 47);
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// PML4E
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if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
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AcquirePage (&PageTable[PTIndex]);
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}
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PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);
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PTIndex = BitFieldRead64 (PFAddress, 30, 38);
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// PDPTE
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if (mPage1GSupport) {
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PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
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} else {
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if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
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AcquirePage (&PageTable[PTIndex]);
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}
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PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);
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PTIndex = BitFieldRead64 (PFAddress, 21, 29);
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// PD
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PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
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}
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return TRUE;
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}
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