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https://github.com/CloverHackyColor/CloverBootloader.git
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302 lines
8.9 KiB
ArmAsm
302 lines
8.9 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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# Copyright (c) 2016, Linaro Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLib.h>
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.set DC_ON, (0x1<<2)
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.set IC_ON, (0x1<<12)
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.set CTRL_M_BIT, (1 << 0)
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.set CTRL_C_BIT, (1 << 2)
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.set CTRL_B_BIT, (1 << 7)
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.set CTRL_I_BIT, (1 << 12)
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ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)
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mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
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bx lr
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ASM_FUNC(ArmCleanDataCacheEntryByMVA)
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mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
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bx lr
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ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)
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mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU
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bx lr
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ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)
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mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU
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mcr p15, 0, r0, c7, c5, 7 @Invalidate branch predictor
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bx lr
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ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
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mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
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bx lr
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ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)
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mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
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bx lr
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ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)
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mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
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bx lr
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ASM_FUNC(ArmCleanDataCacheEntryBySetWay)
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mcr p15, 0, r0, c7, c10, 2 @ Clean this line
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bx lr
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ASM_FUNC(ArmInvalidateInstructionCache)
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mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
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dsb
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isb
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bx LR
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ASM_FUNC(ArmEnableMmu)
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mrc p15,0,R0,c1,c0,0
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orr R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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dsb
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isb
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bx LR
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ASM_FUNC(ArmDisableMmu)
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mrc p15,0,R0,c1,c0,0
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bic R0,R0,#1
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mcr p15,0,R0,c1,c0,0 @Disable MMU
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mcr p15,0,R0,c8,c7,0 @Invalidate TLB
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mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
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dsb
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isb
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bx LR
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ASM_FUNC(ArmDisableCachesAndMmu)
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mrc p15, 0, r0, c1, c0, 0 @ Get control register
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bic r0, r0, #CTRL_M_BIT @ Disable MMU
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bic r0, r0, #CTRL_C_BIT @ Disable D Cache
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bic r0, r0, #CTRL_I_BIT @ Disable I Cache
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mcr p15, 0, r0, c1, c0, 0 @ Write control register
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dsb
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isb
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bx LR
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ASM_FUNC(ArmMmuEnabled)
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mrc p15,0,R0,c1,c0,0
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and R0,R0,#1
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bx LR
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ASM_FUNC(ArmEnableDataCache)
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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orr R0,R0,R1 @Set C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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dsb
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isb
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bx LR
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ASM_FUNC(ArmDisableDataCache)
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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bic R0,R0,R1 @Clear C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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dsb
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isb
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bx LR
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ASM_FUNC(ArmEnableInstructionCache)
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ldr R1,=IC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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orr R0,R0,R1 @Set I bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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dsb
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isb
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bx LR
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ASM_FUNC(ArmDisableInstructionCache)
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ldr R1,=IC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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bic R0,R0,R1 @Clear I bit.
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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dsb
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isb
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bx LR
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ASM_FUNC(ArmEnableSWPInstruction)
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000400
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mcr p15, 0, r0, c1, c0, 0
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isb
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bx LR
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ASM_FUNC(ArmEnableBranchPrediction)
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000800
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mcr p15, 0, r0, c1, c0, 0
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dsb
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isb
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bx LR
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ASM_FUNC(ArmDisableBranchPrediction)
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00000800
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mcr p15, 0, r0, c1, c0, 0
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dsb
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isb
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bx LR
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ASM_FUNC(ArmSetLowVectors)
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mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
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bic r0, r0, #0x00002000 @ clear V bit
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mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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ASM_FUNC(ArmSetHighVectors)
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mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
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orr r0, r0, #0x00002000 @ Set V bit
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mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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ASM_FUNC(ArmV7AllDataCachesOperation)
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stmfd SP!,{r4-r12, LR}
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mov R1, R0 @ Save Function call in R1
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mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
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ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)
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mov R3, R3, LSR #23 @ Cache level value (naturally aligned)
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beq L_Finished
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mov R10, #0
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Loop1:
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add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
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mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
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and R12, R12, #7 @ get those 3 bits alone
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cmp R12, #2
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blt L_Skip @ no cache or only instruction cache at this level
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mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
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isb @ isb to sync the change to the CacheSizeID reg
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mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
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and R2, R12, #0x7 @ extract the line length field
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add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
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@ ldr R4, =0x3FF
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mov R4, #0x400
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sub R4, R4, #1
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ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
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clz R5, R4 @ R5 is the bit position of the way size increment
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@ ldr R7, =0x00007FFF
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mov R7, #0x00008000
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sub R7, R7, #1
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ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
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Loop2:
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mov R9, R4 @ R9 working copy of the max way size (right aligned)
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Loop3:
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orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
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orr R0, R0, R7, LSL R2 @ factor in the index number
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blx R1
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subs R9, R9, #1 @ decrement the way number
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bge Loop3
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subs R7, R7, #1 @ decrement the index
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bge Loop2
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L_Skip:
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add R10, R10, #2 @ increment the cache number
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cmp R3, R10
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bgt Loop1
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L_Finished:
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dsb
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ldmfd SP!, {r4-r12, lr}
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bx LR
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ASM_FUNC(ArmDataMemoryBarrier)
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dmb
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bx LR
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ASM_FUNC(ArmDataSynchronizationBarrier)
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dsb
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bx LR
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ASM_FUNC(ArmInstructionSynchronizationBarrier)
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isb
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bx LR
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ASM_FUNC(ArmReadVBar)
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# Set the Address of the Vector Table in the VBAR register
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mrc p15, 0, r0, c12, c0, 0
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bx lr
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ASM_FUNC(ArmWriteVBar)
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# Set the Address of the Vector Table in the VBAR register
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mcr p15, 0, r0, c12, c0, 0
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# Ensure the SCTLR.V bit is clear
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mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
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bic r0, r0, #0x00002000 @ clear V bit
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mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
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isb
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bx lr
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ASM_FUNC(ArmEnableVFP)
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# Read CPACR (Coprocessor Access Control Register)
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mrc p15, 0, r0, c1, c0, 2
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# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
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orr r0, r0, #0x00f00000
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# Write back CPACR (Coprocessor Access Control Register)
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mcr p15, 0, r0, c1, c0, 2
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isb
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# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
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mov r0, #0x40000000
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#ifndef __clang__
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mcr p10,#0x7,r0,c8,c0,#0
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#else
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# Set the FPU model so Clang does not choke on the next instruction
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.fpu neon
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vmsr fpexc, r0
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#endif
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bx lr
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ASM_FUNC(ArmCallWFI)
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wfi
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bx lr
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#Note: Return 0 in Uniprocessor implementation
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ASM_FUNC(ArmReadCbar)
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mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
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bx lr
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ASM_FUNC(ArmReadMpidr)
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mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
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bx lr
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ASM_FUNC(ArmReadTpidrurw)
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mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW
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bx lr
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ASM_FUNC(ArmWriteTpidrurw)
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mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW
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bx lr
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ASM_FUNC(ArmIsArchTimerImplemented)
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mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1
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and r0, r0, #0x000F0000
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bx lr
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ASM_FUNC(ArmReadIdPfr1)
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mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register
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bx lr
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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