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https://github.com/CloverHackyColor/CloverBootloader.git
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169 lines
7.6 KiB
C
169 lines
7.6 KiB
C
/** @file
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x64 Long Mode Virtual Memory Management Definitions
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References:
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1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
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2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
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3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
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4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
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Copyright (c) 2011, dmazar. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef VIRTUAL_MEMORY_H
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#define VIRTUAL_MEMORY_H
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#pragma pack(push, 1)
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//
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// Page-Map Level-4 Offset (PML4) and
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// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
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//
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typedef union {
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struct {
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UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Reserved : 1; // Reserved
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UINT64 MustBeZero : 2; // Must Be Zero
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UINT64 Available : 3; // Available for use by system software
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UINT64 PageTableBaseAddress : 40; // Page Table Base Address
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UINT64 AvabilableHigh : 11; // Available for use by system software
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UINT64 Nx : 1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} PAGE_MAP_AND_DIRECTORY_POINTER;
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//
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// Page Table Entry 4KB
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//
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typedef union {
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struct {
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UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 PAT : 1; // Combines with CD, WT and MTRR to define true caching type
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UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available : 3; // Available for use by system software
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UINT64 PageTableBaseAddress : 40; // Page Table Base Address
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UINT64 AvabilableHigh : 11; // Available for use by system software
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UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_4K_ENTRY;
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//
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// Page Table Entry 2MB
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//
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typedef union {
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struct {
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UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 MustBe1 : 1; // Must be 1
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UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available : 3; // Available for use by system software
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UINT64 PAT : 1; // Combines with CD, WT and MTRR to define true caching type
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UINT64 MustBeZero : 8; // Must be zero;
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UINT64 PageTableBaseAddress : 31; // Page Table Base Address
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UINT64 AvabilableHigh : 11; // Available for use by system software
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UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_2M_ENTRY;
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//
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// Page Table Entry 1GB
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//
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typedef union {
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struct {
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UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 MustBe1 : 1; // Must be 1
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UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available : 3; // Available for use by system software
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UINT64 PAT : 1; // Combines with CD, WT and MTRR to define true caching type
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UINT64 MustBeZero : 17; // Must be zero;
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UINT64 PageTableBaseAddress : 22; // Page Table Base Address
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UINT64 AvabilableHigh : 11; // Available for use by system software
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UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_1G_ENTRY;
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//
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// PAT index bits.
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//
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typedef union {
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struct {
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UINT8 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT8 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT8 PAT : 1; // Combines with CD, WT and MTRR to define true caching type
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UINT8 Reserved : 5; // Reserved
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} Bits;
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UINT8 Index;
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} PAT_INDEX;
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typedef union {
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struct {
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UINT64 PhysPgOffset : 12; // 0 = Physical Page Offset
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UINT64 PTOffset : 9; // 0 = Page Table Offset
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UINT64 PDOffset : 9; // 0 = Page Directory Offset
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UINT64 PDPOffset : 9; // 0 = Page Directory Pointer Offset
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UINT64 PML4Offset : 9; // 0 = Page Map Level 4 Offset
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UINT64 SignExtend : 16; // 0 = Sign Extend
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} Pg4K;
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struct {
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UINT64 PhysPgOffset : 21; // 0 = Physical Page Offset
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UINT64 PDOffset : 9; // 0 = Page Directory Offset
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UINT64 PDPOffset : 9; // 0 = Page Directory Pointer Offset
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UINT64 PML4Offset : 9; // 0 = Page Map Level 4 Offset
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UINT64 SignExtend : 16; // 0 = Sign Extend
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} Pg2M;
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struct {
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UINT64 PhysPgOffset : 30; // 0 = Physical Page Offset
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UINT64 PDPOffset : 9; // 0 = Page Directory Pointer Offset
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UINT64 PML4Offset : 9; // 0 = Page Map Level 4 Offset
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UINT64 SignExtend : 16; // 0 = Sign Extend
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} Pg1G;
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UINT64 Uint64;
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} VIRTUAL_ADDR;
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#define VA_FIX_SIGN_EXTEND(VA) ((VA).Pg4K.SignExtend = ((VA).Pg4K.PML4Offset & 0x100U) ? 0xFFFFU : 0U);
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#pragma pack(pop)
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#define CR0_WP BIT16
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#define CR3_ADDR_MASK 0x000FFFFFFFFFF000ull
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#define CR3_FLAG_PWT 0x0000000000000008ull
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#define CR3_FLAG_PCD 0x0000000000000010ull
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#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
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#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
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#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
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#endif // VIRTUAL_MEMORY_H
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