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100 lines
3.2 KiB
C
100 lines
3.2 KiB
C
/** @file
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Public include file for I/O APIC library.
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I/O APIC library assumes I/O APIC is enabled. It does not
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handles cases where I/O APIC is disabled.
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Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __IO_APIC_LIB_H__
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#define __IO_APIC_LIB_H__
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/**
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Read a 32-bit I/O APIC register.
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If Index is >= 0x100, then ASSERT().
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@param Index Specifies the I/O APIC register to read.
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@return The 32-bit value read from the I/O APIC register specified by Index.
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**/
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UINT32
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EFIAPI
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IoApicRead (
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IN UINTN Index
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);
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/**
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Write a 32-bit I/O APIC register.
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If Index is >= 0x100, then ASSERT().
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@param Index Specifies the I/O APIC register to write.
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@param Value Specifies the value to write to the I/O APIC register specified by Index.
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@return The 32-bit value written to I/O APIC register specified by Index.
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**/
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UINT32
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EFIAPI
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IoApicWrite (
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IN UINTN Index,
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IN UINT32 Value
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);
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/**
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Set the interrupt mask of an I/O APIC interrupt.
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If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
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@param Irq Specifies the I/O APIC interrupt to enable or disable.
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@param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq.
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If FALSE, then disable the I/O APIC interrupt specified by Irq.
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**/
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VOID
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EFIAPI
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IoApicEnableInterrupt (
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IN UINTN Irq,
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IN BOOLEAN Enable
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);
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/**
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Configures an I/O APIC interrupt.
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Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical
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mode to the Local APIC of the currntly executing CPU. The default state of the
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entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must
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be used to enable(unmask) the I/O APIC Interrupt.
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If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
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If Vector >= 0x100, then ASSERT().
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If DeliveryMode is not supported, then ASSERT().
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@param Irq Specifies the I/O APIC interrupt to initialize.
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@param Vector The 8-bit interrupt vector associated with the I/O APIC
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Interrupt. Must be in the range 0x10..0xFE.
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@param DeliveryMode A 3-bit value that specifies how the recept of the I/O APIC
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interrupt is handled. The only supported values are:
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0: IO_APIC_DELIVERY_MODE_FIXED
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1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY
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2: IO_APIC_DELIVERY_MODE_SMI
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4: IO_APIC_DELIVERY_MODE_NMI
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5: IO_APIC_DELIVERY_MODE_INIT
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7: IO_APIC_DELIVERY_MODE_EXTINT
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@param LevelTriggered TRUE specifies a level triggered interrupt.
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FALSE specifies an edge triggered interrupt.
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@param AssertionLevel TRUE specified an active high interrupt.
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FALSE specifies an active low interrupt.
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**/
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VOID
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EFIAPI
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IoApicConfigureInterrupt (
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IN UINTN Irq,
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IN UINTN Vector,
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IN UINTN DeliveryMode,
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IN BOOLEAN LevelTriggered,
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IN BOOLEAN AssertionLevel
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);
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#endif
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