mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
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01f33f7552
stylish change: remove space between func and brace Signed-off-by: SergeySlice <sergey.slice@gmail.com>
1655 lines
55 KiB
C
1655 lines
55 KiB
C
/** @file
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Functions in this library instance make use of MMIO functions in IoLib to
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access memory mapped PCI configuration space.
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All assertions for I/O operations are handled in MMIO functions in the IoLib
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Library.
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiDxe.h>
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#include <Guid/EventGroup.h>
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#include <Library/BaseLib.h>
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#include <Library/PciExpressLib.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include <Library/UefiRuntimeLib.h>
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///
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/// Define table for mapping PCI Express MMIO physical addresses to virtual addresses at OS runtime
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///
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typedef struct {
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UINTN PhysicalAddress;
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UINTN VirtualAddress;
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} PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE;
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///
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/// Set Virtual Address Map Event
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///
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EFI_EVENT mDxeRuntimePciExpressLibVirtualNotifyEvent = NULL;
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///
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/// Module global that contains the base physical address of the PCI Express MMIO range.
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///
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UINTN mDxeRuntimePciExpressLibPciExpressBaseAddress = 0;
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///
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/// The number of PCI devices that have been registered for runtime access.
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///
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UINTN mDxeRuntimePciExpressLibNumberOfRuntimeRanges = 0;
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///
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/// The table of PCI devices that have been registered for runtime access.
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///
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PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE *mDxeRuntimePciExpressLibRegistrationTable = NULL;
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///
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/// The table index of the most recent virtual address lookup.
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///
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UINTN mDxeRuntimePciExpressLibLastRuntimeRange = 0;
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/**
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Convert the physical PCI Express MMIO addresses for all registered PCI devices
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to virtual addresses.
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@param[in] Event The event that is being processed.
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@param[in] Context The Event Context.
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**/
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VOID
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EFIAPI
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DxeRuntimePciExpressLibVirtualNotify (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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UINTN Index;
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//
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// If there have been no runtime registrations, then just return
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//
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if (mDxeRuntimePciExpressLibRegistrationTable == NULL) {
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return;
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}
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//
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// Convert physical addresses associated with the set of registered PCI devices to
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// virtual addresses.
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//
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for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {
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EfiConvertPointer (0, (VOID **) &(mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress));
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}
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//
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// Convert table pointer that is allocated from EfiRuntimeServicesData to a virtual address.
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//
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EfiConvertPointer (0, (VOID **) &mDxeRuntimePciExpressLibRegistrationTable);
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}
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/**
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The constructor function caches the PCI Express Base Address and creates a
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Set Virtual Address Map event to convert physical address to virtual addresses.
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@param ImageHandle The firmware allocated handle for the EFI image.
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@param SystemTable A pointer to the EFI System Table.
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@retval EFI_SUCCESS The constructor completed successfully.
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@retval Other value The constructor did not complete successfully.
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**/
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EFI_STATUS
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EFIAPI
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DxeRuntimePciExpressLibConstructor (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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//
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// Cache the physical address of the PCI Express MMIO range into a module global variable
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//
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mDxeRuntimePciExpressLibPciExpressBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
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//
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// Register SetVirtualAddressMap () notify function
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//
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Status = gBS->CreateEventEx (
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EVT_NOTIFY_SIGNAL,
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TPL_NOTIFY,
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DxeRuntimePciExpressLibVirtualNotify,
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NULL,
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&gEfiEventVirtualAddressChangeGuid,
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&mDxeRuntimePciExpressLibVirtualNotifyEvent
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);
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ASSERT_EFI_ERROR(Status);
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return Status;
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}
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/**
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The destructor function frees any allocated buffers and closes the Set Virtual
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Address Map event.
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@param ImageHandle The firmware allocated handle for the EFI image.
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@param SystemTable A pointer to the EFI System Table.
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@retval EFI_SUCCESS The destructor completed successfully.
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@retval Other value The destructor did not complete successfully.
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**/
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EFI_STATUS
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EFIAPI
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DxeRuntimePciExpressLibDestructor (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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//
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// If one or more PCI devices have been registered for runtime access, then
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// free the registration table.
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//
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if (mDxeRuntimePciExpressLibRegistrationTable != NULL) {
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FreePool(mDxeRuntimePciExpressLibRegistrationTable);
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}
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//
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// Close the Set Virtual Address Map event
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//
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Status = gBS->CloseEvent (mDxeRuntimePciExpressLibVirtualNotifyEvent);
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ASSERT_EFI_ERROR(Status);
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return Status;
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}
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/**
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Gets the base address of PCI Express.
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This internal functions retrieves PCI Express Base Address via a PCD entry
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PcdPciExpressBaseAddress.
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@param Address The address that encodes the PCI Bus, Device, Function and Register.
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@return The base address of PCI Express.
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**/
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UINTN
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GetPciExpressAddress (
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IN UINTN Address
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)
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{
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UINTN Index;
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//
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// Make sure Address is valid
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//
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ASSERT (((Address) & ~0xfffffff) == 0);
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//
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// Convert Address to a physical address in the MMIO PCI Express range
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//
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Address += mDxeRuntimePciExpressLibPciExpressBaseAddress;
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//
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// If SetVirtualAddressMap() has not been called, then just return the physical address
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//
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if (!EfiGoneVirtual ()) {
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return Address;
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}
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//
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// See if there is a physical address match at the exact same index as the last address match
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//
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if (mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].PhysicalAddress == (Address & (~0x00000fff))) {
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//
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// Convert the physical address to a virtual address and return the virtual address
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//
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return (Address & 0x00000fff) + mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].VirtualAddress;
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}
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//
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// Search the entire table for a physical address match
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//
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for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {
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if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == (Address & (~0x00000fff))) {
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//
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// Cache the matching index value
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//
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mDxeRuntimePciExpressLibLastRuntimeRange = Index;
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//
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// Convert the physical address to a virtual address and return the virtual address
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//
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return (Address & 0x00000fff) + mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress;
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}
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}
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//
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// No match was found. This is a critical error at OS runtime, so ASSERT() and force a breakpoint.
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//
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ASSERT (FALSE);
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CpuBreakpoint();
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//
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// Return the physical address
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//
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return Address;
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}
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/**
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Registers a PCI device so PCI configuration registers may be accessed after
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SetVirtualAddressMap().
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Registers the PCI device specified by Address so all the PCI configuration
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registers associated with that PCI device may be accessed after SetVirtualAddressMap()
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is called.
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If Address > 0x0FFFFFFF, then ASSERT().
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@param Address The address that encodes the PCI Bus, Device, Function and
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Register.
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@retval RETURN_SUCCESS The PCI device was registered for runtime access.
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@retval RETURN_UNSUPPORTED An attempt was made to call this function
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after ExitBootServices().
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@retval RETURN_UNSUPPORTED The resources required to access the PCI device
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at runtime could not be mapped.
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@retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
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complete the registration.
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**/
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RETURN_STATUS
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EFIAPI
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PciExpressRegisterForRuntimeAccess (
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IN UINTN Address
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)
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{
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EFI_STATUS Status;
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EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
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UINTN Index;
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VOID *NewTable;
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//
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// Return an error if this function is called after ExitBootServices().
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//
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if (EfiAtRuntime ()) {
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return RETURN_UNSUPPORTED;
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}
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//
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// Make sure Address is valid
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//
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ASSERT (((Address) & ~0xfffffff) == 0);
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//
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// Convert Address to a physical address in the MMIO PCI Express range
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// at the beginning of the PCI Configuration header for the specified
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// PCI Bus/Dev/Func
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//
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Address = GetPciExpressAddress (Address & 0x0ffff000);
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//
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// See if Address has already been registerd for runtime access
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//
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for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {
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if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == Address) {
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return RETURN_SUCCESS;
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}
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}
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//
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// Get the GCD Memory Descriptor for the PCI Express Bus/Dev/Func specified by Address
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//
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Status = gDS->GetMemorySpaceDescriptor (Address, &Descriptor);
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if (EFI_ERROR(Status)) {
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return RETURN_UNSUPPORTED;
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}
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//
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// Mark the 4KB region for the PCI Express Bus/Dev/Func as EFI_RUNTIME_MEMORY so the OS
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// will allocate a virtual address range for the 4KB PCI Configuration Header.
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//
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Status = gDS->SetMemorySpaceAttributes (Address, 0x1000, Descriptor.Attributes | EFI_MEMORY_RUNTIME);
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if (EFI_ERROR(Status)) {
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return RETURN_UNSUPPORTED;
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}
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//
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// Grow the size of the registration table
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//
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NewTable = ReallocateRuntimePool (
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(mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 0) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE),
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(mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 1) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE),
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mDxeRuntimePciExpressLibRegistrationTable
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);
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if (NewTable == NULL) {
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return RETURN_OUT_OF_RESOURCES;
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}
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mDxeRuntimePciExpressLibRegistrationTable = NewTable;
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mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibNumberOfRuntimeRanges].PhysicalAddress = Address;
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mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibNumberOfRuntimeRanges].VirtualAddress = Address;
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mDxeRuntimePciExpressLibNumberOfRuntimeRanges++;
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return RETURN_SUCCESS;
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}
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/**
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Reads an 8-bit PCI configuration register.
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Reads and returns the 8-bit PCI configuration register specified by Address.
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This function must guarantee that all PCI read and write operations are
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serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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@param Address The address that encodes the PCI Bus, Device, Function and
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Register.
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@return The read value from the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciExpressRead8 (
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IN UINTN Address
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)
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{
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return MmioRead8 (GetPciExpressAddress (Address));
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}
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/**
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Writes an 8-bit PCI configuration register.
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Writes the 8-bit PCI configuration register specified by Address with the
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value specified by Value. Value is returned. This function must guarantee
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that all PCI read and write operations are serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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@param Address The address that encodes the PCI Bus, Device, Function and
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Register.
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@param Value The value to write.
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@return The value written to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciExpressWrite8 (
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IN UINTN Address,
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IN UINT8 Value
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)
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{
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return MmioWrite8 (GetPciExpressAddress (Address), Value);
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}
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/**
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Performs a bitwise OR of an 8-bit PCI configuration register with
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an 8-bit value.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise OR between the read result and the value specified by
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OrData, and writes the result to the 8-bit PCI configuration register
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specified by Address. The value written to the PCI configuration register is
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returned. This function must guarantee that all PCI read and write operations
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are serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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@param Address The address that encodes the PCI Bus, Device, Function and
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Register.
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@param OrData The value to OR with the PCI configuration register.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciExpressOr8 (
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IN UINTN Address,
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IN UINT8 OrData
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)
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{
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return MmioOr8 (GetPciExpressAddress (Address), OrData);
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}
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/**
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Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
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value.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise AND between the read result and the value specified by AndData, and
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writes the result to the 8-bit PCI configuration register specified by
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Address. The value written to the PCI configuration register is returned.
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This function must guarantee that all PCI read and write operations are
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serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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@param Address The address that encodes the PCI Bus, Device, Function and
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Register.
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@param AndData The value to AND with the PCI configuration register.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciExpressAnd8 (
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IN UINTN Address,
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IN UINT8 AndData
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)
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{
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return MmioAnd8 (GetPciExpressAddress (Address), AndData);
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}
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/**
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Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
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value, followed a bitwise OR with another 8-bit value.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise AND between the read result and the value specified by AndData,
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performs a bitwise OR between the result of the AND operation and
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the value specified by OrData, and writes the result to the 8-bit PCI
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configuration register specified by Address. The value written to the PCI
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configuration register is returned. This function must guarantee that all PCI
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read and write operations are serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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@param Address The address that encodes the PCI Bus, Device, Function and
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Register.
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@param AndData The value to AND with the PCI configuration register.
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@param OrData The value to OR with the result of the AND operation.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciExpressAndThenOr8 (
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IN UINTN Address,
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IN UINT8 AndData,
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IN UINT8 OrData
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)
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{
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return MmioAndThenOr8 (
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GetPciExpressAddress (Address),
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AndData,
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OrData
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);
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}
|
|
|
|
/**
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Reads a bit field of a PCI configuration register.
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|
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|
Reads the bit field in an 8-bit PCI configuration register. The bit field is
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specified by the StartBit and the EndBit. The value of the bit field is
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returned.
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|
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If Address > 0x0FFFFFFF, then ASSERT().
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If StartBit is greater than 7, then ASSERT().
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If EndBit is greater than 7, then ASSERT().
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If EndBit is less than StartBit, then ASSERT().
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|
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@param Address The PCI configuration register to read.
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@param StartBit The ordinal of the least significant bit in the bit field.
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Range 0..7.
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@param EndBit The ordinal of the most significant bit in the bit field.
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Range 0..7.
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@return The value of the bit field read from the PCI configuration register.
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|
**/
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|
UINT8
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EFIAPI
|
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PciExpressBitFieldRead8 (
|
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IN UINTN Address,
|
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IN UINTN StartBit,
|
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IN UINTN EndBit
|
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)
|
|
{
|
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return MmioBitFieldRead8 (
|
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GetPciExpressAddress (Address),
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StartBit,
|
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EndBit
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);
|
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}
|
|
|
|
/**
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|
Writes a bit field to a PCI configuration register.
|
|
|
|
Writes Value to the bit field of the PCI configuration register. The bit
|
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field is specified by the StartBit and the EndBit. All other bits in the
|
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destination PCI configuration register are preserved. The new value of the
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8-bit register is returned.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
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If StartBit is greater than 7, then ASSERT().
|
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If EndBit is greater than 7, then ASSERT().
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If EndBit is less than StartBit, then ASSERT().
|
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If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
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|
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@param Address The PCI configuration register to write.
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@param StartBit The ordinal of the least significant bit in the bit field.
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Range 0..7.
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@param EndBit The ordinal of the most significant bit in the bit field.
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Range 0..7.
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@param Value The new value of the bit field.
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@return The value written back to the PCI configuration register.
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|
|
**/
|
|
UINT8
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EFIAPI
|
|
PciExpressBitFieldWrite8 (
|
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IN UINTN Address,
|
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IN UINTN StartBit,
|
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IN UINTN EndBit,
|
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IN UINT8 Value
|
|
)
|
|
{
|
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return MmioBitFieldWrite8 (
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GetPciExpressAddress (Address),
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StartBit,
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EndBit,
|
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Value
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);
|
|
}
|
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|
|
/**
|
|
Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
|
|
writes the result back to the bit field in the 8-bit port.
|
|
|
|
Reads the 8-bit PCI configuration register specified by Address, performs a
|
|
bitwise OR between the read result and the value specified by
|
|
OrData, and writes the result to the 8-bit PCI configuration register
|
|
specified by Address. The value written to the PCI configuration register is
|
|
returned. This function must guarantee that all PCI read and write operations
|
|
are serialized. Extra left bits in OrData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If StartBit is greater than 7, then ASSERT().
|
|
If EndBit is greater than 7, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address The PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..7.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..7.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT8
|
|
EFIAPI
|
|
PciExpressBitFieldOr8 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT8 OrData
|
|
)
|
|
{
|
|
return MmioBitFieldOr8 (
|
|
GetPciExpressAddress (Address),
|
|
StartBit,
|
|
EndBit,
|
|
OrData
|
|
);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
|
|
AND, and writes the result back to the bit field in the 8-bit register.
|
|
|
|
Reads the 8-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData, and
|
|
writes the result to the 8-bit PCI configuration register specified by
|
|
Address. The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are
|
|
serialized. Extra left bits in AndData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If StartBit is greater than 7, then ASSERT().
|
|
If EndBit is greater than 7, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address The PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..7.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..7.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT8
|
|
EFIAPI
|
|
PciExpressBitFieldAnd8 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT8 AndData
|
|
)
|
|
{
|
|
return MmioBitFieldAnd8 (
|
|
GetPciExpressAddress (Address),
|
|
StartBit,
|
|
EndBit,
|
|
AndData
|
|
);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
|
|
bitwise OR, and writes the result back to the bit field in the
|
|
8-bit port.
|
|
|
|
Reads the 8-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND followed by a bitwise OR between the read result and
|
|
the value specified by AndData, and writes the result to the 8-bit PCI
|
|
configuration register specified by Address. The value written to the PCI
|
|
configuration register is returned. This function must guarantee that all PCI
|
|
read and write operations are serialized. Extra left bits in both AndData and
|
|
OrData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If StartBit is greater than 7, then ASSERT().
|
|
If EndBit is greater than 7, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address The PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..7.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..7.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
@param OrData The value to OR with the result of the AND operation.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT8
|
|
EFIAPI
|
|
PciExpressBitFieldAndThenOr8 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT8 AndData,
|
|
IN UINT8 OrData
|
|
)
|
|
{
|
|
return MmioBitFieldAndThenOr8 (
|
|
GetPciExpressAddress (Address),
|
|
StartBit,
|
|
EndBit,
|
|
AndData,
|
|
OrData
|
|
);
|
|
}
|
|
|
|
/**
|
|
Reads a 16-bit PCI configuration register.
|
|
|
|
Reads and returns the 16-bit PCI configuration register specified by Address.
|
|
This function must guarantee that all PCI read and write operations are
|
|
serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
|
|
@return The read value from the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciExpressRead16 (
|
|
IN UINTN Address
|
|
)
|
|
{
|
|
return MmioRead16 (GetPciExpressAddress (Address));
|
|
}
|
|
|
|
/**
|
|
Writes a 16-bit PCI configuration register.
|
|
|
|
Writes the 16-bit PCI configuration register specified by Address with the
|
|
value specified by Value. Value is returned. This function must guarantee
|
|
that all PCI read and write operations are serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param Value The value to write.
|
|
|
|
@return The value written to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciExpressWrite16 (
|
|
IN UINTN Address,
|
|
IN UINT16 Value
|
|
)
|
|
{
|
|
return MmioWrite16 (GetPciExpressAddress (Address), Value);
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise OR of a 16-bit PCI configuration register with
|
|
a 16-bit value.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise OR between the read result and the value specified by
|
|
OrData, and writes the result to the 16-bit PCI configuration register
|
|
specified by Address. The value written to the PCI configuration register is
|
|
returned. This function must guarantee that all PCI read and write operations
|
|
are serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciExpressOr16 (
|
|
IN UINTN Address,
|
|
IN UINT16 OrData
|
|
)
|
|
{
|
|
return MmioOr16 (GetPciExpressAddress (Address), OrData);
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
|
|
value.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData, and
|
|
writes the result to the 16-bit PCI configuration register specified by
|
|
Address. The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are
|
|
serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciExpressAnd16 (
|
|
IN UINTN Address,
|
|
IN UINT16 AndData
|
|
)
|
|
{
|
|
return MmioAnd16 (GetPciExpressAddress (Address), AndData);
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
|
|
value, followed a bitwise OR with another 16-bit value.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData,
|
|
performs a bitwise OR between the result of the AND operation and
|
|
the value specified by OrData, and writes the result to the 16-bit PCI
|
|
configuration register specified by Address. The value written to the PCI
|
|
configuration register is returned. This function must guarantee that all PCI
|
|
read and write operations are serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
@param OrData The value to OR with the result of the AND operation.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciExpressAndThenOr16 (
|
|
IN UINTN Address,
|
|
IN UINT16 AndData,
|
|
IN UINT16 OrData
|
|
)
|
|
{
|
|
return MmioAndThenOr16 (
|
|
GetPciExpressAddress (Address),
|
|
AndData,
|
|
OrData
|
|
);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field of a PCI configuration register.
|
|
|
|
Reads the bit field in a 16-bit PCI configuration register. The bit field is
|
|
specified by the StartBit and the EndBit. The value of the bit field is
|
|
returned.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
|
|
@param Address The PCI configuration register to read.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
|
|
@return The value of the bit field read from the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciExpressBitFieldRead16 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit
|
|
)
|
|
{
|
|
return MmioBitFieldRead16 (
|
|
GetPciExpressAddress (Address),
|
|
StartBit,
|
|
EndBit
|
|
);
|
|
}
|
|
|
|
/**
|
|
Writes a bit field to a PCI configuration register.
|
|
|
|
Writes Value to the bit field of the PCI configuration register. The bit
|
|
field is specified by the StartBit and the EndBit. All other bits in the
|
|
destination PCI configuration register are preserved. The new value of the
|
|
16-bit register is returned.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address The PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
@param Value The new value of the bit field.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciExpressBitFieldWrite16 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT16 Value
|
|
)
|
|
{
|
|
return MmioBitFieldWrite16 (
|
|
GetPciExpressAddress (Address),
|
|
StartBit,
|
|
EndBit,
|
|
Value
|
|
);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
|
|
writes the result back to the bit field in the 16-bit port.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise OR between the read result and the value specified by
|
|
OrData, and writes the result to the 16-bit PCI configuration register
|
|
specified by Address. The value written to the PCI configuration register is
|
|
returned. This function must guarantee that all PCI read and write operations
|
|
are serialized. Extra left bits in OrData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address The PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciExpressBitFieldOr16 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT16 OrData
|
|
)
|
|
{
|
|
return MmioBitFieldOr16 (
|
|
GetPciExpressAddress (Address),
|
|
StartBit,
|
|
EndBit,
|
|
OrData
|
|
);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
|
|
AND, and writes the result back to the bit field in the 16-bit register.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData, and
|
|
writes the result to the 16-bit PCI configuration register specified by
|
|
Address. The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are
|
|
serialized. Extra left bits in AndData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address The PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciExpressBitFieldAnd16 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT16 AndData
|
|
)
|
|
{
|
|
return MmioBitFieldAnd16 (
|
|
GetPciExpressAddress (Address),
|
|
StartBit,
|
|
EndBit,
|
|
AndData
|
|
);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
|
|
bitwise OR, and writes the result back to the bit field in the
|
|
16-bit port.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND followed by a bitwise OR between the read result and
|
|
the value specified by AndData, and writes the result to the 16-bit PCI
|
|
configuration register specified by Address. The value written to the PCI
|
|
configuration register is returned. This function must guarantee that all PCI
|
|
read and write operations are serialized. Extra left bits in both AndData and
|
|
OrData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address The PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
@param OrData The value to OR with the result of the AND operation.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciExpressBitFieldAndThenOr16 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT16 AndData,
|
|
IN UINT16 OrData
|
|
)
|
|
{
|
|
return MmioBitFieldAndThenOr16 (
|
|
GetPciExpressAddress (Address),
|
|
StartBit,
|
|
EndBit,
|
|
AndData,
|
|
OrData
|
|
);
|
|
}
|
|
|
|
/**
|
|
Reads a 32-bit PCI configuration register.
|
|
|
|
Reads and returns the 32-bit PCI configuration register specified by Address.
|
|
This function must guarantee that all PCI read and write operations are
|
|
serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
|
|
@return The read value from the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciExpressRead32 (
|
|
IN UINTN Address
|
|
)
|
|
{
|
|
return MmioRead32 (GetPciExpressAddress (Address));
|
|
}
|
|
|
|
/**
|
|
Writes a 32-bit PCI configuration register.
|
|
|
|
Writes the 32-bit PCI configuration register specified by Address with the
|
|
value specified by Value. Value is returned. This function must guarantee
|
|
that all PCI read and write operations are serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param Value The value to write.
|
|
|
|
@return The value written to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciExpressWrite32 (
|
|
IN UINTN Address,
|
|
IN UINT32 Value
|
|
)
|
|
{
|
|
return MmioWrite32 (GetPciExpressAddress (Address), Value);
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise OR of a 32-bit PCI configuration register with
|
|
a 32-bit value.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise OR between the read result and the value specified by
|
|
OrData, and writes the result to the 32-bit PCI configuration register
|
|
specified by Address. The value written to the PCI configuration register is
|
|
returned. This function must guarantee that all PCI read and write operations
|
|
are serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciExpressOr32 (
|
|
IN UINTN Address,
|
|
IN UINT32 OrData
|
|
)
|
|
{
|
|
return MmioOr32 (GetPciExpressAddress (Address), OrData);
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
|
|
value.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData, and
|
|
writes the result to the 32-bit PCI configuration register specified by
|
|
Address. The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are
|
|
serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciExpressAnd32 (
|
|
IN UINTN Address,
|
|
IN UINT32 AndData
|
|
)
|
|
{
|
|
return MmioAnd32 (GetPciExpressAddress (Address), AndData);
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
|
|
value, followed a bitwise OR with another 32-bit value.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData,
|
|
performs a bitwise OR between the result of the AND operation and
|
|
the value specified by OrData, and writes the result to the 32-bit PCI
|
|
configuration register specified by Address. The value written to the PCI
|
|
configuration register is returned. This function must guarantee that all PCI
|
|
read and write operations are serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
@param OrData The value to OR with the result of the AND operation.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciExpressAndThenOr32 (
|
|
IN UINTN Address,
|
|
IN UINT32 AndData,
|
|
IN UINT32 OrData
|
|
)
|
|
{
|
|
return MmioAndThenOr32 (
|
|
GetPciExpressAddress (Address),
|
|
AndData,
|
|
OrData
|
|
);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field of a PCI configuration register.
|
|
|
|
Reads the bit field in a 32-bit PCI configuration register. The bit field is
|
|
specified by the StartBit and the EndBit. The value of the bit field is
|
|
returned.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
|
|
@param Address The PCI configuration register to read.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
|
|
@return The value of the bit field read from the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciExpressBitFieldRead32 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit
|
|
)
|
|
{
|
|
return MmioBitFieldRead32 (
|
|
GetPciExpressAddress (Address),
|
|
StartBit,
|
|
EndBit
|
|
);
|
|
}
|
|
|
|
/**
|
|
Writes a bit field to a PCI configuration register.
|
|
|
|
Writes Value to the bit field of the PCI configuration register. The bit
|
|
field is specified by the StartBit and the EndBit. All other bits in the
|
|
destination PCI configuration register are preserved. The new value of the
|
|
32-bit register is returned.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address The PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
@param Value The new value of the bit field.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciExpressBitFieldWrite32 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT32 Value
|
|
)
|
|
{
|
|
return MmioBitFieldWrite32 (
|
|
GetPciExpressAddress (Address),
|
|
StartBit,
|
|
EndBit,
|
|
Value
|
|
);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
|
|
writes the result back to the bit field in the 32-bit port.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise OR between the read result and the value specified by
|
|
OrData, and writes the result to the 32-bit PCI configuration register
|
|
specified by Address. The value written to the PCI configuration register is
|
|
returned. This function must guarantee that all PCI read and write operations
|
|
are serialized. Extra left bits in OrData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address The PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciExpressBitFieldOr32 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT32 OrData
|
|
)
|
|
{
|
|
return MmioBitFieldOr32 (
|
|
GetPciExpressAddress (Address),
|
|
StartBit,
|
|
EndBit,
|
|
OrData
|
|
);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
|
|
AND, and writes the result back to the bit field in the 32-bit register.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData, and
|
|
writes the result to the 32-bit PCI configuration register specified by
|
|
Address. The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are
|
|
serialized. Extra left bits in AndData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address The PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciExpressBitFieldAnd32 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT32 AndData
|
|
)
|
|
{
|
|
return MmioBitFieldAnd32 (
|
|
GetPciExpressAddress (Address),
|
|
StartBit,
|
|
EndBit,
|
|
AndData
|
|
);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
|
|
bitwise OR, and writes the result back to the bit field in the
|
|
32-bit port.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND followed by a bitwise OR between the read result and
|
|
the value specified by AndData, and writes the result to the 32-bit PCI
|
|
configuration register specified by Address. The value written to the PCI
|
|
configuration register is returned. This function must guarantee that all PCI
|
|
read and write operations are serialized. Extra left bits in both AndData and
|
|
OrData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address The PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
@param OrData The value to OR with the result of the AND operation.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciExpressBitFieldAndThenOr32 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT32 AndData,
|
|
IN UINT32 OrData
|
|
)
|
|
{
|
|
return MmioBitFieldAndThenOr32 (
|
|
GetPciExpressAddress (Address),
|
|
StartBit,
|
|
EndBit,
|
|
AndData,
|
|
OrData
|
|
);
|
|
}
|
|
|
|
/**
|
|
Reads a range of PCI configuration registers into a caller supplied buffer.
|
|
|
|
Reads the range of PCI configuration registers specified by StartAddress and
|
|
Size into the buffer specified by Buffer. This function only allows the PCI
|
|
configuration registers from a single PCI function to be read. Size is
|
|
returned. When possible 32-bit PCI configuration read cycles are used to read
|
|
from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
|
|
and 16-bit PCI configuration read cycles may be used at the beginning and the
|
|
end of the range.
|
|
|
|
If StartAddress > 0x0FFFFFFF, then ASSERT().
|
|
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
|
If Size > 0 and Buffer is NULL, then ASSERT().
|
|
|
|
@param StartAddress The starting address that encodes the PCI Bus, Device,
|
|
Function and Register.
|
|
@param Size The size in bytes of the transfer.
|
|
@param Buffer The pointer to a buffer receiving the data read.
|
|
|
|
@return Size read data from StartAddress.
|
|
|
|
**/
|
|
UINTN
|
|
EFIAPI
|
|
PciExpressReadBuffer (
|
|
IN UINTN StartAddress,
|
|
IN UINTN Size,
|
|
OUT VOID *Buffer
|
|
)
|
|
{
|
|
UINTN ReturnValue;
|
|
|
|
//
|
|
// Make sure Address is valid
|
|
//
|
|
ASSERT (((StartAddress) & ~0xfffffff) == 0);
|
|
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
|
|
|
if (Size == 0) {
|
|
return Size;
|
|
}
|
|
|
|
ASSERT (Buffer != NULL);
|
|
|
|
//
|
|
// Save Size for return
|
|
//
|
|
ReturnValue = Size;
|
|
|
|
if ((StartAddress & 1) != 0) {
|
|
//
|
|
// Read a byte if StartAddress is byte aligned
|
|
//
|
|
*(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
|
|
StartAddress += sizeof (UINT8);
|
|
Size -= sizeof (UINT8);
|
|
Buffer = (UINT8*)Buffer + 1;
|
|
}
|
|
|
|
if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
|
|
//
|
|
// Read a word if StartAddress is word aligned
|
|
//
|
|
WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
|
|
|
|
StartAddress += sizeof (UINT16);
|
|
Size -= sizeof (UINT16);
|
|
Buffer = (UINT16*)Buffer + 1;
|
|
}
|
|
|
|
while (Size >= sizeof (UINT32)) {
|
|
//
|
|
// Read as many double words as possible
|
|
//
|
|
WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));
|
|
|
|
StartAddress += sizeof (UINT32);
|
|
Size -= sizeof (UINT32);
|
|
Buffer = (UINT32*)Buffer + 1;
|
|
}
|
|
|
|
if (Size >= sizeof (UINT16)) {
|
|
//
|
|
// Read the last remaining word if exist
|
|
//
|
|
WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
|
|
StartAddress += sizeof (UINT16);
|
|
Size -= sizeof (UINT16);
|
|
Buffer = (UINT16*)Buffer + 1;
|
|
}
|
|
|
|
if (Size >= sizeof (UINT8)) {
|
|
//
|
|
// Read the last remaining byte if exist
|
|
//
|
|
*(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
|
|
}
|
|
|
|
return ReturnValue;
|
|
}
|
|
|
|
/**
|
|
Copies the data in a caller supplied buffer to a specified range of PCI
|
|
configuration space.
|
|
|
|
Writes the range of PCI configuration registers specified by StartAddress and
|
|
Size from the buffer specified by Buffer. This function only allows the PCI
|
|
configuration registers from a single PCI function to be written. Size is
|
|
returned. When possible 32-bit PCI configuration write cycles are used to
|
|
write from StartAdress to StartAddress + Size. Due to alignment restrictions,
|
|
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
|
|
and the end of the range.
|
|
|
|
If StartAddress > 0x0FFFFFFF, then ASSERT().
|
|
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
|
If Size > 0 and Buffer is NULL, then ASSERT().
|
|
|
|
@param StartAddress The starting address that encodes the PCI Bus, Device,
|
|
Function and Register.
|
|
@param Size The size in bytes of the transfer.
|
|
@param Buffer The pointer to a buffer containing the data to write.
|
|
|
|
@return Size written to StartAddress.
|
|
|
|
**/
|
|
UINTN
|
|
EFIAPI
|
|
PciExpressWriteBuffer (
|
|
IN UINTN StartAddress,
|
|
IN UINTN Size,
|
|
IN VOID *Buffer
|
|
)
|
|
{
|
|
UINTN ReturnValue;
|
|
|
|
//
|
|
// Make sure Address is valid
|
|
//
|
|
ASSERT (((StartAddress) & ~0xfffffff) == 0);
|
|
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
|
|
|
if (Size == 0) {
|
|
return 0;
|
|
}
|
|
|
|
ASSERT (Buffer != NULL);
|
|
|
|
//
|
|
// Save Size for return
|
|
//
|
|
ReturnValue = Size;
|
|
|
|
if ((StartAddress & 1) != 0) {
|
|
//
|
|
// Write a byte if StartAddress is byte aligned
|
|
//
|
|
PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
|
|
StartAddress += sizeof (UINT8);
|
|
Size -= sizeof (UINT8);
|
|
Buffer = (UINT8*)Buffer + 1;
|
|
}
|
|
|
|
if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
|
|
//
|
|
// Write a word if StartAddress is word aligned
|
|
//
|
|
PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
|
|
StartAddress += sizeof (UINT16);
|
|
Size -= sizeof (UINT16);
|
|
Buffer = (UINT16*)Buffer + 1;
|
|
}
|
|
|
|
while (Size >= sizeof (UINT32)) {
|
|
//
|
|
// Write as many double words as possible
|
|
//
|
|
PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));
|
|
StartAddress += sizeof (UINT32);
|
|
Size -= sizeof (UINT32);
|
|
Buffer = (UINT32*)Buffer + 1;
|
|
}
|
|
|
|
if (Size >= sizeof (UINT16)) {
|
|
//
|
|
// Write the last remaining word if exist
|
|
//
|
|
PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
|
|
StartAddress += sizeof (UINT16);
|
|
Size -= sizeof (UINT16);
|
|
Buffer = (UINT16*)Buffer + 1;
|
|
}
|
|
|
|
if (Size >= sizeof (UINT8)) {
|
|
//
|
|
// Write the last remaining byte if exist
|
|
//
|
|
PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
|
|
}
|
|
|
|
return ReturnValue;
|
|
}
|