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56 lines
2.0 KiB
C
56 lines
2.0 KiB
C
/** @file
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Generic definitions for registers in the Intel Ich devices.
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These definitions should work for any version of Ich.
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Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _GENERIC_ICH_H_
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#define _GENERIC_ICH_H_
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/** GenericIchDefs Generic ICH Definitions.
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Definitions beginning with "R_" are registers.
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Definitions beginning with "B_" are bits within registers.
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Definitions beginning with "V_" are meaningful values of bits within the registers.
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**/
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///@{
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/// IchPciAddressing PCI Bus Address for ICH.
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///@{
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#define PCI_BUS_NUMBER_ICH 0x00 ///< ICH is on PCI Bus 0.
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#define PCI_DEVICE_NUMBER_ICH_LPC 31 ///< ICH is Device 31.
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#define PCI_FUNCTION_NUMBER_ICH_LPC 0 ///< ICH is Function 0.
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///@}
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/// IchAcpiCntr Control for the ICH's ACPI Counter.
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///@{
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#define R_ICH_LPC_ACPI_BASE 0x40
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#define B_ICH_LPC_ACPI_BASE_BAR 0x0000FF80
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#define R_ICH_LPC_ACPI_CNT 0x44
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#define B_ICH_LPC_ACPI_CNT_ACPI_EN 0x80
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///@}
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/// IchAcpiTimer The ICH's ACPI Timer.
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///@{
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#define R_ACPI_PM1_TMR 0x08
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#define V_ACPI_TMR_FREQUENCY 3579545
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#define V_ACPI_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow.
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///@}
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/// Macro to generate the PCI address of any given ICH Register.
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#define PCI_ICH_LPC_ADDRESS(Register) \
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((UINTN)(PCI_LIB_ADDRESS (PCI_BUS_NUMBER_ICH, PCI_DEVICE_NUMBER_ICH_LPC, PCI_FUNCTION_NUMBER_ICH_LPC, Register)))
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///@}
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#endif // _GENERIC_ICH_H_
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