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https://github.com/CloverHackyColor/CloverBootloader.git
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239 lines
9.0 KiB
C
239 lines
9.0 KiB
C
/** @file
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This header file contains the platform independent parts of ARM Mali DP
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Copyright (c) 2017-2018, Arm Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef ARMMALIDP_H_
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#define ARMMALIDP_H_
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#define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBase))
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// MALI DP Ids
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#define MALIDP_NOT_PRESENT 0xFFF
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#define MALIDP_500 0x500
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#define MALIDP_550 0x550
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#define MALIDP_650 0x650
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// DP500 Peripheral Ids
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#define DP500_ID_PART_0 0x00
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#define DP500_ID_DES_0 0xB
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#define DP500_ID_PART_1 0x5
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#define DP500_ID_REVISION 0x1
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#define DP500_ID_JEDEC 0x1
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#define DP500_ID_DES_1 0x3
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#define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0)
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#define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \
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| DP500_ID_PART_1)
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#define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \
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| (DP500_ID_JEDEC << 3) \
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| (DP500_ID_DES_1))
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// DP550 Peripheral Ids
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#define DP550_ID_PART_0 0x50
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#define DP550_ID_DES_0 0xB
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#define DP550_ID_PART_1 0x5
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#define DP550_ID_REVISION 0x0
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#define DP550_ID_JEDEC 0x1
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#define DP550_ID_DES_1 0x3
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#define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0)
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#define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \
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| DP550_ID_PART_1)
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#define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \
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| (DP550_ID_JEDEC << 3) \
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| (DP550_ID_DES_1))
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// DP650 Peripheral Ids
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#define DP650_ID_PART_0 0x50
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#define DP650_ID_DES_0 0xB
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#define DP650_ID_PART_1 0x6
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#define DP650_ID_REVISION 0x0
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#define DP650_ID_JEDEC 0x1
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#define DP650_ID_DES_1 0x3
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#define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0)
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#define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \
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| DP650_ID_PART_1)
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#define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \
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| (DP650_ID_JEDEC << 3) \
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| (DP650_ID_DES_1))
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// Display Engine (DE) control register offsets for DP550/DP650
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#define DP_DE_STATUS 0x00000
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#define DP_DE_IRQ_SET 0x00004
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#define DP_DE_IRQ_MASK 0x00008
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#define DP_DE_IRQ_CLEAR 0x0000C
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#define DP_DE_CONTROL 0x00010
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#define DP_DE_PROG_LINE 0x00014
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#define DP_DE_AXI_CONTROL 0x00018
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#define DP_DE_AXI_QOS 0x0001C
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#define DP_DE_DISPLAY_FUNCTION 0x00020
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#define DP_DE_H_INTERVALS 0x00030
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#define DP_DE_V_INTERVALS 0x00034
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#define DP_DE_SYNC_CONTROL 0x00038
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#define DP_DE_HV_ACTIVESIZE 0x0003C
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#define DP_DE_DISPLAY_SIDEBAND 0x00040
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#define DP_DE_BACKGROUND_COLOR 0x00044
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#define DP_DE_DISPLAY_SPLIT 0x00048
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#define DP_DE_OUTPUT_DEPTH 0x0004C
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// Display Engine (DE) control register offsets for DP500
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#define DP_DE_DP500_CORE_ID 0x00018
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#define DP_DE_DP500_CONTROL 0x0000C
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#define DP_DE_DP500_PROG_LINE 0x00010
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#define DP_DE_DP500_H_INTERVALS 0x00028
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#define DP_DE_DP500_V_INTERVALS 0x0002C
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#define DP_DE_DP500_SYNC_CONTROL 0x00030
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#define DP_DE_DP500_HV_ACTIVESIZE 0x00034
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#define DP_DE_DP500_BG_COLOR_RG 0x0003C
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#define DP_DE_DP500_BG_COLOR_B 0x00040
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/* Display Engine (DE) graphics layer (LG) register offsets
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* NOTE: For DP500 it will be LG2.
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*/
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#define DE_LG_OFFSET 0x00300
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#define DP_DE_LG_FORMAT (DE_LG_OFFSET)
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#define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04)
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#define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08)
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#define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C)
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#define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10)
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#define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14)
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#define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18)
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#define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C)
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#define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20)
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#define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C)
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#define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30)
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#define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48)
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// Display core (DC) control register offsets.
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#define DP_DC_OFFSET 0x0C000
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#define DP_DC_STATUS (DP_DC_OFFSET + 0x00)
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#define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04)
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#define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08)
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#define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C)
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#define DP_DC_CONTROL (DP_DC_OFFSET + 0x10)
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#define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14)
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#define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18)
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// DP500 has a global configuration register.
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#define DP_DP500_CONFIG_VALID (0xF00)
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// Display core ID register offsets.
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#define DP_DC_ID_OFFSET 0x0FF00
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#define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0)
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#define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4)
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#define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0)
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#define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4)
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#define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8)
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#define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0)
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#define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4)
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#define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8)
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#define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC)
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#define DP_DP500_ID_OFFSET 0x0F00
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#define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0)
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#define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4)
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#define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0)
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#define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4)
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#define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8)
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#define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0)
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#define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4)
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#define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8)
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#define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC)
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// Display status configuration mode activation flag
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#define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16)
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// Display core control configuration mode
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#define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18)
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#define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17)
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#define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16)
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#define DP_DE_DP500_CONTROL_SOFTRESET_REQ (0x1U << 16)
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#define DP_DE_DP500_CONTROL_CONFIG_REQ (0x1U << 17)
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// Display core configuration valid register
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#define DP_DC_CONFIG_VALID_CVAL (0x1U)
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// DC_CORE_ID
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// Display core version register PRODUCT_ID
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#define DP_DC_CORE_ID_SHIFT 16
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#define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT
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// Timing settings
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#define DP_DE_HBACKPORCH_SHIFT 16
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#define DP_DE_VBACKPORCH_SHIFT 16
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#define DP_DE_VSP_SHIFT 28
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#define DP_DE_VSYNCWIDTH_SHIFT 16
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#define DP_DE_HSP_SHIFT 13
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#define DP_DE_V_ACTIVE_SHIFT 16
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// BACKGROUND_COLOR
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#define DP_DE_BG_R_PIXEL_SHIFT 16
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#define DP_DE_BG_G_PIXEL_SHIFT 8
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// Graphics layer LG_FORMAT Pixel Format
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#define DP_PIXEL_FORMAT_ARGB_8888 0x8
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#define DP_PIXEL_FORMAT_ABGR_8888 0x9
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#define DP_PIXEL_FORMAT_RGBA_8888 0xA
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#define DP_PIXEL_FORMAT_BGRA_8888 0xB
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#define DP_PIXEL_FORMAT_XRGB_8888 0x10
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#define DP_PIXEL_FORMAT_XBGR_8888 0x11
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#define DP_PIXEL_FORMAT_RGBX_8888 0x12
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#define DP_PIXEL_FORMAT_BGRX_8888 0x13
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#define DP_PIXEL_FORMAT_RGB_888 0x18
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#define DP_PIXEL_FORMAT_BGR_888 0x19
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// DP500 format code are different than DP550/DP650
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#define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2
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#define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3
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#define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4
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#define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5
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// Graphics layer LG_PTR_LOW and LG_PTR_HIGH
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#define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU
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#define DP_DE_LG_PTR_HIGH_SHIFT 32
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// Graphics layer LG_CONTROL register characteristics
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#define DP_DE_LG_L_ALPHA_SHIFT 16
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#define DP_DE_LG_CHK_SHIFT 15
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#define DP_DE_LG_PMUL_SHIFT 14
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#define DP_DE_LG_COM_SHIFT 12
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#define DP_DE_LG_VFP_SHIFT 11
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#define DP_DE_LG_HFP_SHIFT 10
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#define DP_DE_LG_ROTATION_SHIFT 8
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#define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U
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#define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U
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#define DP_DE_LG_LAYER_BLEND_BG 0x2U
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#define DP_DE_LG_PIXEL_BLEND_BG 0x3U
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#define DP_DE_LG_ENABLE 0x1U
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// Graphics layer LG_IN_SIZE register characteristics
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#define DP_DE_LG_V_IN_SIZE_SHIFT 16
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// Graphics layer LG_CMP_SIZE register characteristics
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#define DP_DE_LG_V_CMP_SIZE_SHIFT 16
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#define DP_DE_LG_V_OFFSET_SHIFT 16
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// Helper display timing macro functions.
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#define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hfp)
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#define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vfp)
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#define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hsw)
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#define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Hor)
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// Helper layer graphics macros.
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#define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | Hor)
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#define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) | Hor)
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#endif /* ARMMALIDP_H_ */
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