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https://github.com/CloverHackyColor/CloverBootloader.git
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146 lines
5.6 KiB
C
146 lines
5.6 KiB
C
/** @file
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The NvmExpressPei driver is used to manage non-volatile memory subsystem
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which follows NVM Express specification at PEI phase.
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Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _NVM_EXPRESS_PEI_HCI_H_
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#define _NVM_EXPRESS_PEI_HCI_H_
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//
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// NVME host controller registers operation definitions
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//
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#define NVME_GET_CAP(Private, Cap) NvmeMmioRead (Cap, Private->MmioBase + NVME_CAP_OFFSET, sizeof (NVME_CAP))
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#define NVME_GET_CC(Private, Cc) NvmeMmioRead (Cc, Private->MmioBase + NVME_CC_OFFSET, sizeof (NVME_CC))
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#define NVME_SET_CC(Private, Cc) NvmeMmioWrite (Private->MmioBase + NVME_CC_OFFSET, Cc, sizeof (NVME_CC))
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#define NVME_GET_CSTS(Private, Csts) NvmeMmioRead (Csts, Private->MmioBase + NVME_CSTS_OFFSET, sizeof (NVME_CSTS))
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#define NVME_GET_AQA(Private, Aqa) NvmeMmioRead (Aqa, Private->MmioBase + NVME_AQA_OFFSET, sizeof (NVME_AQA))
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#define NVME_SET_AQA(Private, Aqa) NvmeMmioWrite (Private->MmioBase + NVME_AQA_OFFSET, Aqa, sizeof (NVME_AQA))
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#define NVME_GET_ASQ(Private, Asq) NvmeMmioRead (Asq, Private->MmioBase + NVME_ASQ_OFFSET, sizeof (NVME_ASQ))
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#define NVME_SET_ASQ(Private, Asq) NvmeMmioWrite (Private->MmioBase + NVME_ASQ_OFFSET, Asq, sizeof (NVME_ASQ))
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#define NVME_GET_ACQ(Private, Acq) NvmeMmioRead (Acq, Private->MmioBase + NVME_ACQ_OFFSET, sizeof (NVME_ACQ))
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#define NVME_SET_ACQ(Private, Acq) NvmeMmioWrite (Private->MmioBase + NVME_ACQ_OFFSET, Acq, sizeof (NVME_ACQ))
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#define NVME_GET_VER(Private, Ver) NvmeMmioRead (Ver, Private->MmioBase + NVME_VER_OFFSET, sizeof (NVME_VER))
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#define NVME_SET_SQTDBL(Private, Qid, Sqtdbl) NvmeMmioWrite (Private->MmioBase + NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd), Sqtdbl, sizeof (NVME_SQTDBL))
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#define NVME_SET_CQHDBL(Private, Qid, Cqhdbl) NvmeMmioWrite (Private->MmioBase + NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd), Cqhdbl, sizeof (NVME_CQHDBL))
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//
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// Base memory address enum types
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//
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enum {
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BASEMEM_ASQ,
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BASEMEM_ACQ,
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BASEMEM_SQ,
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BASEMEM_CQ,
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BASEMEM_PRP,
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MAX_BASEMEM_COUNT
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};
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//
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// All of base memories are 4K(0x1000) alignment
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//
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#define ALIGN(v, a) (UINTN)((((v) - 1) | ((a) - 1)) + 1)
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#define NVME_MEM_BASE(Private) ((UINTN)(Private->Buffer))
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#define NVME_ASQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
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#define NVME_ACQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
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#define NVME_SQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
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#define NVME_CQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
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#define NVME_PRP_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
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/**
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Transfer MMIO Data to memory.
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@param[in,out] MemBuffer Destination: Memory address.
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@param[in] MmioAddr Source: MMIO address.
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@param[in] Size Size for read.
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@retval EFI_SUCCESS MMIO read sucessfully.
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**/
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EFI_STATUS
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NvmeMmioRead (
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IN OUT VOID *MemBuffer,
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IN UINTN MmioAddr,
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IN UINTN Size
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);
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/**
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Transfer memory data to MMIO.
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@param[in,out] MmioAddr Destination: MMIO address.
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@param[in] MemBuffer Source: Memory address.
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@param[in] Size Size for write.
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@retval EFI_SUCCESS MMIO write sucessfully.
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**/
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EFI_STATUS
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NvmeMmioWrite (
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IN OUT UINTN MmioAddr,
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IN VOID *MemBuffer,
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IN UINTN Size
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);
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/**
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Get the page offset for specific NVME based memory.
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@param[in] BaseMemIndex The Index of BaseMem (0-based).
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@retval - The page count for specific BaseMem Index
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**/
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UINT32
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NvmeBaseMemPageOffset (
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IN UINTN BaseMemIndex
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);
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/**
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Initialize the Nvm Express controller.
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@param[in] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
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@retval EFI_SUCCESS The NVM Express Controller is initialized successfully.
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@retval Others A device error occurred while initializing the controller.
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**/
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EFI_STATUS
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NvmeControllerInit (
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IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
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);
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/**
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Get specified identify namespace data.
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@param[in] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
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@param[in] NamespaceId The specified namespace identifier.
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@param[in] Buffer The buffer used to store the identify namespace data.
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@return EFI_SUCCESS Successfully get the identify namespace data.
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@return EFI_DEVICE_ERROR Fail to get the identify namespace data.
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**/
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EFI_STATUS
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NvmeIdentifyNamespace (
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IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN UINT32 NamespaceId,
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IN VOID *Buffer
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);
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/**
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Free the DMA resources allocated by an NVME controller.
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@param[in] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
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**/
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VOID
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NvmeFreeDmaResource (
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IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
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);
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#endif
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