mirror of
https://github.com/CloverHackyColor/CloverBootloader.git
synced 2024-11-30 12:43:41 +01:00
285 lines
5.5 KiB
Raku
285 lines
5.5 KiB
Raku
#!/usr/bin/env perl
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$flavour = shift;
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$output = shift;
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if ($flavour =~ /\./) { $output = $flavour; undef $flavour; }
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$win64=0; $win64=1 if ($flavour =~ /[nm]asm|mingw64/ || $output =~ /\.asm$/);
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
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( $xlate="${dir}perlasm/x86_64-xlate.pl" and -f $xlate) or
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die "can't locate x86_64-xlate.pl";
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open OUT,"| \"$^X\" $xlate $flavour $output";
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*STDOUT=*OUT;
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($arg1,$arg2,$arg3,$arg4)=$win64?("%rcx","%rdx","%r8", "%r9") : # Win64 order
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("%rdi","%rsi","%rdx","%rcx"); # Unix order
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print<<___;
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.extern OPENSSL_cpuid_setup
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.hidden OPENSSL_cpuid_setup
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.section .init
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call OPENSSL_cpuid_setup
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.hidden OPENSSL_ia32cap_P
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.comm OPENSSL_ia32cap_P,8,4
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.text
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.globl OPENSSL_atomic_add
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.type OPENSSL_atomic_add,\@abi-omnipotent
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.align 16
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OPENSSL_atomic_add:
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movl ($arg1),%eax
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.Lspin: leaq ($arg2,%rax),%r8
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.byte 0xf0 # lock
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cmpxchgl %r8d,($arg1)
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jne .Lspin
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movl %r8d,%eax
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.byte 0x48,0x98 # cltq/cdqe
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ret
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.size OPENSSL_atomic_add,.-OPENSSL_atomic_add
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.globl OPENSSL_rdtsc
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.type OPENSSL_rdtsc,\@abi-omnipotent
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.align 16
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OPENSSL_rdtsc:
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rdtsc
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shl \$32,%rdx
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or %rdx,%rax
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ret
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.size OPENSSL_rdtsc,.-OPENSSL_rdtsc
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.globl OPENSSL_ia32_cpuid
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.type OPENSSL_ia32_cpuid,\@abi-omnipotent
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.align 16
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OPENSSL_ia32_cpuid:
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mov %rbx,%r8 # save %rbx
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xor %eax,%eax
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cpuid
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mov %eax,%r11d # max value for standard query level
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xor %eax,%eax
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cmp \$0x756e6547,%ebx # "Genu"
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setne %al
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mov %eax,%r9d
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cmp \$0x49656e69,%edx # "ineI"
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setne %al
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or %eax,%r9d
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cmp \$0x6c65746e,%ecx # "ntel"
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setne %al
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or %eax,%r9d # 0 indicates Intel CPU
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jz .Lintel
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cmp \$0x68747541,%ebx # "Auth"
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setne %al
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mov %eax,%r10d
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cmp \$0x69746E65,%edx # "enti"
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setne %al
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or %eax,%r10d
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cmp \$0x444D4163,%ecx # "cAMD"
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setne %al
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or %eax,%r10d # 0 indicates AMD CPU
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jnz .Lintel
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# AMD specific
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mov \$0x80000000,%eax
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cpuid
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cmp \$0x80000001,%eax
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jb .Lintel
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mov %eax,%r10d
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mov \$0x80000001,%eax
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cpuid
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or %ecx,%r9d
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and \$0x00000801,%r9d # isolate AMD XOP bit, 1<<11
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cmp \$0x80000008,%r10d
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jb .Lintel
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mov \$0x80000008,%eax
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cpuid
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movzb %cl,%r10 # number of cores - 1
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inc %r10 # number of cores
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mov \$1,%eax
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cpuid
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bt \$28,%edx # test hyper-threading bit
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jnc .Lgeneric
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shr \$16,%ebx # number of logical processors
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cmp %r10b,%bl
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ja .Lgeneric
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and \$0xefffffff,%edx # ~(1<<28)
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jmp .Lgeneric
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.Lintel:
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cmp \$4,%r11d
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mov \$-1,%r10d
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jb .Lnocacheinfo
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mov \$4,%eax
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mov \$0,%ecx # query L1D
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cpuid
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mov %eax,%r10d
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shr \$14,%r10d
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and \$0xfff,%r10d # number of cores -1 per L1D
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.Lnocacheinfo:
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mov \$1,%eax
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cpuid
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and \$0xbfefffff,%edx # force reserved bits to 0
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cmp \$0,%r9d
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jne .Lnotintel
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or \$0x40000000,%edx # set reserved bit#30 on Intel CPUs
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and \$15,%ah
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cmp \$15,%ah # examine Family ID
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jne .Lnotintel
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or \$0x00100000,%edx # set reserved bit#20 to engage RC4_CHAR
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.Lnotintel:
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bt \$28,%edx # test hyper-threading bit
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jnc .Lgeneric
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and \$0xefffffff,%edx # ~(1<<28)
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cmp \$0,%r10d
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je .Lgeneric
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or \$0x10000000,%edx # 1<<28
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shr \$16,%ebx
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cmp \$1,%bl # see if cache is shared
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ja .Lgeneric
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and \$0xefffffff,%edx # ~(1<<28)
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.Lgeneric:
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and \$0x00000800,%r9d # isolate AMD XOP flag
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and \$0xfffff7ff,%ecx
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or %ecx,%r9d # merge AMD XOP flag
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mov %edx,%r10d # %r9d:%r10d is copy of %ecx:%edx
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bt \$27,%r9d # check OSXSAVE bit
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jnc .Lclear_avx
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xor %ecx,%ecx # XCR0
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.byte 0x0f,0x01,0xd0 # xgetbv
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and \$6,%eax # isolate XMM and YMM state support
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cmp \$6,%eax
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je .Ldone
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.Lclear_avx:
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mov \$0xefffe7ff,%eax # ~(1<<28|1<<12|1<<11)
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and %eax,%r9d # clear AVX, FMA and AMD XOP bits
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.Ldone:
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shl \$32,%r9
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mov %r10d,%eax
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mov %r8,%rbx # restore %rbx
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or %r9,%rax
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ret
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.size OPENSSL_ia32_cpuid,.-OPENSSL_ia32_cpuid
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.globl OPENSSL_cleanse
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.type OPENSSL_cleanse,\@abi-omnipotent
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.align 16
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OPENSSL_cleanse:
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xor %rax,%rax
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cmp \$15,$arg2
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jae .Lot
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cmp \$0,$arg2
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je .Lret
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.Little:
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mov %al,($arg1)
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sub \$1,$arg2
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lea 1($arg1),$arg1
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jnz .Little
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.Lret:
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ret
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.align 16
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.Lot:
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test \$7,$arg1
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jz .Laligned
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mov %al,($arg1)
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lea -1($arg2),$arg2
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lea 1($arg1),$arg1
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jmp .Lot
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.Laligned:
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mov %rax,($arg1)
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lea -8($arg2),$arg2
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test \$-8,$arg2
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lea 8($arg1),$arg1
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jnz .Laligned
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cmp \$0,$arg2
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jne .Little
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ret
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.size OPENSSL_cleanse,.-OPENSSL_cleanse
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___
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print<<___ if (!$win64);
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.globl OPENSSL_wipe_cpu
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.type OPENSSL_wipe_cpu,\@abi-omnipotent
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.align 16
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OPENSSL_wipe_cpu:
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pxor %xmm0,%xmm0
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pxor %xmm1,%xmm1
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pxor %xmm2,%xmm2
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pxor %xmm3,%xmm3
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pxor %xmm4,%xmm4
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pxor %xmm5,%xmm5
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pxor %xmm6,%xmm6
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pxor %xmm7,%xmm7
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pxor %xmm8,%xmm8
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pxor %xmm9,%xmm9
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pxor %xmm10,%xmm10
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pxor %xmm11,%xmm11
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pxor %xmm12,%xmm12
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pxor %xmm13,%xmm13
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pxor %xmm14,%xmm14
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pxor %xmm15,%xmm15
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xorq %rcx,%rcx
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xorq %rdx,%rdx
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xorq %rsi,%rsi
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xorq %rdi,%rdi
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xorq %r8,%r8
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xorq %r9,%r9
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xorq %r10,%r10
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xorq %r11,%r11
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leaq 8(%rsp),%rax
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ret
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.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
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___
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print<<___ if ($win64);
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.globl OPENSSL_wipe_cpu
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.type OPENSSL_wipe_cpu,\@abi-omnipotent
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.align 16
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OPENSSL_wipe_cpu:
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pxor %xmm0,%xmm0
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pxor %xmm1,%xmm1
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pxor %xmm2,%xmm2
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pxor %xmm3,%xmm3
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pxor %xmm4,%xmm4
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pxor %xmm5,%xmm5
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xorq %rcx,%rcx
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xorq %rdx,%rdx
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xorq %r8,%r8
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xorq %r9,%r9
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xorq %r10,%r10
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xorq %r11,%r11
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leaq 8(%rsp),%rax
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ret
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.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
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___
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print<<___;
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.globl OPENSSL_ia32_rdrand
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.type OPENSSL_ia32_rdrand,\@abi-omnipotent
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.align 16
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OPENSSL_ia32_rdrand:
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mov \$8,%ecx
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.Loop_rdrand:
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rdrand %rax
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jc .Lbreak_rdrand
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loop .Loop_rdrand
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.Lbreak_rdrand:
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cmp \$0,%rax
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cmove %rcx,%rax
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ret
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.size OPENSSL_ia32_rdrand,.-OPENSSL_ia32_rdrand
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___
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close STDOUT; # flush
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