551 lines
19 KiB
C
551 lines
19 KiB
C
/**
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Virtual memory functions.
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by dmazar
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**/
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#include <Library/UefiLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include "VMem.h"
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#include "Lib.h"
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#include "NVRAMDebug.h"
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// DBG_TO: 0=no debug, 1=serial, 2=console
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// serial requires
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// [PcdsFixedAtBuild]
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// gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x07
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// gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xFFFFFFFF
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// in package DSC file
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#define DBG_TO 0
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#if DBG_TO == 2
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#define DBG(...) AsciiPrint(__VA_ARGS__);
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#elif DBG_TO == 1
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#define DBG(...) DebugPrint(1, __VA_ARGS__);
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#else
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#define DBG(...)
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#endif
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/** Memory allocation for VM map pages that we will create with VmMapVirtualPage.
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* We need to have it preallocated during boot services.
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*/
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UINT8 *VmMemoryPool = NULL;
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INTN VmMemoryPoolFreePages = 0;
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VOID
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GetCurrentPageTable(PAGE_MAP_AND_DIRECTORY_POINTER **PageTable, UINTN *Flags)
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{
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UINTN CR3;
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CR3 = AsmReadCr3();
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DBG("GetCurrentPageTable: CR3 = 0x%lx\n", CR3);
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*PageTable = (PAGE_MAP_AND_DIRECTORY_POINTER*)(UINTN)(CR3 & CR3_ADDR_MASK);
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*Flags = CR3 & (CR3_FLAG_PWT | CR3_FLAG_PCD);
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}
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VOID
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PrintPageTablePTE(PAGE_TABLE_4K_ENTRY *PTE, VIRTUAL_ADDR VA)
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{
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#if DBG_TO
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UINTN Index;
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UINT64 Start;
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for (Index = 0; Index < 10; Index++) {
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VA.Pg4K.PTOffset = Index;
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DBG(" PTE %03x at %p = %lx => ", Index, PTE, PTE->Uint64);
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// 4KB PTE
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Start = (PTE->Uint64 & PT_ADDR_MASK_4K);
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DBG("4KB Fl: %lx VA: %lx - %lx ==> PH %lx - %lx\n",
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(PTE->Uint64 & ~PT_ADDR_MASK_4K), VA.Uint64, VA.Uint64 + 0x1000 - 1, Start, Start + 0x1000 - 1);
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PTE++;
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}
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//WaitForKeyPress(L"more ...");
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#endif
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}
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VOID
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PrintPageTablePDE(PAGE_MAP_AND_DIRECTORY_POINTER *PDE, VIRTUAL_ADDR VA)
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{
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#if DBG_TO
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UINTN Index;
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PAGE_TABLE_2M_ENTRY *PT2M;
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PAGE_TABLE_4K_ENTRY *PTE;
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UINT64 Start;
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for (Index = 0; Index < 10; Index++) {
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VA.Pg4K.PDOffset = Index;
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DBG(" PDE %03x at %p = %lx => ", Index, PDE, PDE->Uint64);
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if (PDE->Bits.MustBeZero & 0x1) {
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// 2MB PDE
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PT2M = (PAGE_TABLE_2M_ENTRY *)PDE;
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Start = (PT2M->Uint64 & PT_ADDR_MASK_2M);
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DBG("2MB Fl: %lx VA: %lx - %lx ==> PH %lx - %lx\n",
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(PT2M->Uint64 & ~PT_ADDR_MASK_2M), VA.Uint64, VA.Uint64 + 0x200000 - 1, Start, Start + 0x200000 - 1);
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} else {
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DBG(" Fl: %lx %lx ->\n", (PDE->Uint64 & ~PT_ADDR_MASK_4K), (PDE->Uint64 & PT_ADDR_MASK_4K));
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PTE = (PAGE_TABLE_4K_ENTRY *)(PDE->Uint64 & PT_ADDR_MASK_4K);
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PrintPageTablePTE(PTE, VA);
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}
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PDE++;
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}
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//WaitForKeyPress(L"more ...");
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#endif
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}
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VOID
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PrintPageTablePDPE(PAGE_MAP_AND_DIRECTORY_POINTER *PDPE, VIRTUAL_ADDR VA)
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{
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#if DBG_TO
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UINTN Index;
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PAGE_TABLE_1G_ENTRY *PT1G;
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PAGE_MAP_AND_DIRECTORY_POINTER *PDE;
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UINT64 Start;
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for (Index = 0; Index < 10; Index++) {
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VA.Pg4K.PDPOffset = Index;
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DBG(" PDPE %03x at %p = %lx => ", Index, PDPE, PDPE->Uint64);
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if (PDPE->Bits.MustBeZero & 0x1) {
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// 1GB PDPE
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PT1G = (PAGE_TABLE_1G_ENTRY *)PDPE;
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Start = (PT1G->Uint64 & PT_ADDR_MASK_1G);
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DBG("1GB Fl: %lx VA: %lx - %lx ==> PH %lx - %lx\n",
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(PT1G->Uint64 & ~PT_ADDR_MASK_1G), VA.Uint64, VA.Uint64 + 0x40000000 - 1, Start, Start + 0x40000000 - 1);
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} else {
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DBG(" Fl: %lx %lx ->\n", (PDPE->Uint64 & ~PT_ADDR_MASK_4K), (PDPE->Uint64 & PT_ADDR_MASK_4K));
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PDE = (PAGE_MAP_AND_DIRECTORY_POINTER *)(PDPE->Uint64 & PT_ADDR_MASK_4K);
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PrintPageTablePDE(PDE, VA);
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}
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PDPE++;
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}
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//WaitForKeyPress(L"more ...");
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#endif
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}
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VOID
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PrintPageTable(PAGE_MAP_AND_DIRECTORY_POINTER *PageTable, UINTN Flags)
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{
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UINTN Index;
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VIRTUAL_ADDR VA;
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PAGE_MAP_AND_DIRECTORY_POINTER *PML4;
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PAGE_MAP_AND_DIRECTORY_POINTER *PDPE;
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DBG("PrintPageTable: %p, Flags: PWT: %d, PCD: %d\n", PageTable, (Flags & CR3_FLAG_PWT), (Flags & CR3_FLAG_PCD));
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PML4 = PageTable;
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for (Index = 0; Index < 3; Index++) {
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VA.Uint64 = 0;
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VA.Pg4K.PML4Offset = Index;
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VA_FIX_SIGN_EXTEND(VA);
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DBG("PML4 %03x at %p = %lx => Fl: %lx %lx ->\n", Index, PML4, PML4->Uint64, (PML4->Uint64 & ~PT_ADDR_MASK_4K), (PML4->Uint64 & PT_ADDR_MASK_4K));
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PDPE = (PAGE_MAP_AND_DIRECTORY_POINTER *)(PML4->Uint64 & PT_ADDR_MASK_4K);
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PrintPageTablePDPE(PDPE, VA);
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PML4++;
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}
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//WaitForKeyPress(L"END");
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}
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EFI_STATUS
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GetPhysicalAddr(PAGE_MAP_AND_DIRECTORY_POINTER *PageTable, EFI_VIRTUAL_ADDRESS VirtualAddr, EFI_PHYSICAL_ADDRESS *PhysicalAddr)
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{
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EFI_PHYSICAL_ADDRESS Start;
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VIRTUAL_ADDR VA;
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VIRTUAL_ADDR VAStart;
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VIRTUAL_ADDR VAEnd;
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PAGE_MAP_AND_DIRECTORY_POINTER *PML4;
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PAGE_MAP_AND_DIRECTORY_POINTER *PDPE;
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PAGE_MAP_AND_DIRECTORY_POINTER *PDE;
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PAGE_TABLE_4K_ENTRY *PTE4K;
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PAGE_TABLE_2M_ENTRY *PTE2M;
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PAGE_TABLE_1G_ENTRY *PTE1G;
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VA.Uint64 = (UINT64)VirtualAddr;
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//VA_FIX_SIGN_EXTEND(VA);
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DBG("PageTable: %p\n", PageTable);
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DBG("VA: %lx => Indexes PML4=%x, PDP=%x, PD=%x, PT=%x\n",
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VA.Uint64, VA.Pg4K.PML4Offset, VA.Pg4K.PDPOffset, VA.Pg4K.PDOffset, VA.Pg4K.PTOffset);
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// PML4
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PML4 = PageTable;
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PML4 += VA.Pg4K.PML4Offset;
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// prepare region start and end
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VAStart.Uint64 = 0;
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VAStart.Pg4K.PML4Offset = VA.Pg4K.PML4Offset;
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VA_FIX_SIGN_EXTEND(VAStart);
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VAEnd.Uint64 = ~(UINT64)0;
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VAEnd.Pg4K.PML4Offset = VA.Pg4K.PML4Offset;
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VA_FIX_SIGN_EXTEND(VAEnd);
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// print it
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DBG("PML4[%03x] at %p = %lx Region: %lx - %lx\n", VA.Pg4K.PML4Offset, PML4, PML4->Uint64, VAStart.Uint64, VAEnd.Uint64);
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if (!PML4->Bits.Present) {
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DBG("-> Mapping not present!\n");
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return EFI_NO_MAPPING;
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}
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DBG("-> Nx:%x|A:%x|PCD:%x|PWT:%x|US:%x|RW:%x|P:%x -> %lx\n",
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PML4->Bits.Nx, PML4->Bits.Accessed,
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PML4->Bits.CacheDisabled, PML4->Bits.WriteThrough,
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PML4->Bits.UserSupervisor, PML4->Bits.ReadWrite, PML4->Bits.Present,
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(PML4->Uint64 & PT_ADDR_MASK_4K)
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);
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// PDPE
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PDPE = (PAGE_MAP_AND_DIRECTORY_POINTER *)(PML4->Uint64 & PT_ADDR_MASK_4K);
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PDPE += VA.Pg4K.PDPOffset;
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VAStart.Pg4K.PDPOffset = VA.Pg4K.PDPOffset;
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VAEnd.Pg4K.PDPOffset = VA.Pg4K.PDPOffset;
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DBG("PDPE[%03x] at %p = %lx Region: %lx - %lx\n", VA.Pg4K.PDPOffset, PDPE, PDPE->Uint64, VAStart.Uint64, VAEnd.Uint64);
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if (!PDPE->Bits.Present) {
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DBG("-> Mapping not present!\n");
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return EFI_NO_MAPPING;
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}
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if (PDPE->Bits.MustBeZero & 0x1) {
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// 1GB PDPE
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PTE1G = (PAGE_TABLE_1G_ENTRY *)PDPE;
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DBG("-> Nx:%x|G:%x|PAT:%x|D:%x|A:%x|PCD:%x|PWT:%x|US:%x|RW:%x|P:%x\n",
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PTE1G->Bits.Nx, PTE1G->Bits.Global, PTE1G->Bits.PAT,
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PTE1G->Bits.Dirty, PTE1G->Bits.Accessed,
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PTE1G->Bits.CacheDisabled, PTE1G->Bits.WriteThrough,
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PTE1G->Bits.UserSupervisor, PTE1G->Bits.ReadWrite, PTE1G->Bits.Present
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);
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Start = (PTE1G->Uint64 & PT_ADDR_MASK_1G);
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*PhysicalAddr = Start + VA.Pg1G.PhysPgOffset;
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DBG("-> 1GB page %lx - %lx => %lx\n", Start, Start + 0x40000000 - 1, *PhysicalAddr);
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return EFI_SUCCESS;
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}
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DBG("-> Nx:%x|A:%x|PCD:%x|PWT:%x|US:%x|RW:%x|P:%x -> %lx\n",
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PDPE->Bits.Nx, PDPE->Bits.Accessed,
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PDPE->Bits.CacheDisabled, PDPE->Bits.WriteThrough,
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PDPE->Bits.UserSupervisor, PDPE->Bits.ReadWrite, PDPE->Bits.Present,
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(PDPE->Uint64 & PT_ADDR_MASK_4K)
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);
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// PDE
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PDE = (PAGE_MAP_AND_DIRECTORY_POINTER *)(PDPE->Uint64 & PT_ADDR_MASK_4K);
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PDE += VA.Pg4K.PDOffset;
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VAStart.Pg4K.PDOffset = VA.Pg4K.PDOffset;
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VAEnd.Pg4K.PDOffset = VA.Pg4K.PDOffset;
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DBG("PDE[%03x] at %p = %lx Region: %lx - %lx\n", VA.Pg4K.PDOffset, PDE, PDE->Uint64, VAStart.Uint64, VAEnd.Uint64);
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if (!PDE->Bits.Present) {
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DBG("-> Mapping not present!\n");
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return EFI_NO_MAPPING;
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}
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if (PDE->Bits.MustBeZero & 0x1) {
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// 2MB PDE
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PTE2M = (PAGE_TABLE_2M_ENTRY *)PDE;
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DBG("-> Nx:%x|G:%x|PAT:%x|D:%x|A:%x|PCD:%x|PWT:%x|US:%x|RW:%x|P:%x\n",
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PTE2M->Bits.Nx, PTE2M->Bits.Global, PTE2M->Bits.PAT,
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PTE2M->Bits.Dirty, PTE2M->Bits.Accessed,
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PTE2M->Bits.CacheDisabled, PTE2M->Bits.WriteThrough,
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PTE2M->Bits.UserSupervisor, PTE2M->Bits.ReadWrite, PTE2M->Bits.Present
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);
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Start = (PTE2M->Uint64 & PT_ADDR_MASK_2M);
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*PhysicalAddr = Start + VA.Pg2M.PhysPgOffset;
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DBG("-> 2MB page %lx - %lx => %lx\n", Start, Start + 0x200000 - 1, *PhysicalAddr);
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return EFI_SUCCESS;
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}
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DBG("-> Nx:%x|A:%x|PCD:%x|PWT:%x|US:%x|RW:%x|P:%x -> %lx\n",
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PDE->Bits.Nx, PDE->Bits.Accessed,
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PDE->Bits.CacheDisabled, PDE->Bits.WriteThrough,
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PDE->Bits.UserSupervisor, PDE->Bits.ReadWrite, PDE->Bits.Present,
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(PDE->Uint64 & PT_ADDR_MASK_4K)
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);
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// PTE
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PTE4K = (PAGE_TABLE_4K_ENTRY *)(PDE->Uint64 & PT_ADDR_MASK_4K);
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PTE4K += VA.Pg4K.PTOffset;
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VAStart.Pg4K.PTOffset = VA.Pg4K.PTOffset;
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VAEnd.Pg4K.PTOffset = VA.Pg4K.PTOffset;
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DBG("PTE[%03x] at %p = %lx Region: %lx - %lx\n", VA.Pg4K.PTOffset, PTE4K, PTE4K->Uint64, VAStart.Uint64, VAEnd.Uint64);
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if (!PTE4K->Bits.Present) {
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DBG("-> Mapping not present!\n");
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return EFI_NO_MAPPING;
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}
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DBG("-> Nx:%x|G:%x|PAT:%x|D:%x|A:%x|PCD:%x|PWT:%x|US:%x|RW:%x|P:%x -> %lx\n",
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PTE4K->Bits.Nx, PTE4K->Bits.Global, PTE4K->Bits.PAT,
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PTE4K->Bits.Dirty, PTE4K->Bits.Accessed,
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PTE4K->Bits.CacheDisabled, PTE4K->Bits.WriteThrough,
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PTE4K->Bits.UserSupervisor, PTE4K->Bits.ReadWrite, PTE4K->Bits.Present,
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(PTE4K->Uint64 & PT_ADDR_MASK_4K)
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);
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Start = (PTE4K->Uint64 & PT_ADDR_MASK_4K);
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*PhysicalAddr = Start + VA.Pg4K.PhysPgOffset;
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return EFI_SUCCESS;
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}
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/** Inits vm memory pool. Should be called while boot services are still usable. */
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EFI_STATUS
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VmAllocateMemoryPool(VOID)
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{
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EFI_STATUS Status;
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EFI_PHYSICAL_ADDRESS Addr;
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if (VmMemoryPool != NULL) {
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// already allocated
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return EFI_SUCCESS;
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}
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VmMemoryPoolFreePages = 0x200; // 2 MB should be enough
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Addr = 0x100000000; // max address
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Status = AllocatePagesFromTop(EfiBootServicesData, VmMemoryPoolFreePages, &Addr);
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if (Status != EFI_SUCCESS) {
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Print(L"VmAllocateMemoryPool: AllocatePagesFromTop(EfiBootServicesData) = %r\n", Status);
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} else {
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VmMemoryPool = (UINT8*)Addr;
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DBG("VmMemoryPool = %lx - %lx\n", VmMemoryPool, VmMemoryPool + EFI_PAGES_TO_SIZE(VmMemoryPoolFreePages) - 1);
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DBGnvr("VmMemoryPool = %lx - %lx\n", VmMemoryPool, VmMemoryPool + EFI_PAGES_TO_SIZE(VmMemoryPoolFreePages) - 1);
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}
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return Status;
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}
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/** Central method for allocating pages for VM page maps. */
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VOID *
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VmAllocatePages(UINTN NumPages)
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{
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VOID *AllocatedPages = NULL;
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/*
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EFI_STATUS Status;
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EFI_PHYSICAL_ADDRESS Addr;
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// for now, just allocate EfiBootServicesData as usuall.
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// if needed, we'll allocate somwhere from the top of mem.
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Status = gBS->AllocatePages(AllocateAnyPages, EfiBootServicesData, NumPages, &Addr);
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if (EFI_ERROR(Status)) {
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Addr = 0;
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}
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return (VOID*)Addr;
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*/
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if (VmMemoryPoolFreePages >= (INTN)NumPages) {
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AllocatedPages = VmMemoryPool;
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VmMemoryPool += EFI_PAGES_TO_SIZE(NumPages);
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VmMemoryPoolFreePages -= NumPages;
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} else {
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DBGnvr("VmAllocatePages - no more pages!\n");
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CpuDeadLoop();
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}
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return AllocatedPages;
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}
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/** Maps (remaps) 4K page given by VirtualAddr to PhysicalAddr page in PageTable. */
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EFI_STATUS
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VmMapVirtualPage(PAGE_MAP_AND_DIRECTORY_POINTER *PageTable, EFI_VIRTUAL_ADDRESS VirtualAddr, EFI_PHYSICAL_ADDRESS PhysicalAddr)
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{
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EFI_PHYSICAL_ADDRESS Start;
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VIRTUAL_ADDR VA;
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VIRTUAL_ADDR VAStart;
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VIRTUAL_ADDR VAEnd;
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PAGE_MAP_AND_DIRECTORY_POINTER *PML4;
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PAGE_MAP_AND_DIRECTORY_POINTER *PDPE;
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PAGE_MAP_AND_DIRECTORY_POINTER *PDE;
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PAGE_TABLE_4K_ENTRY *PTE4K;
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PAGE_TABLE_4K_ENTRY *PTE4KTmp;
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PAGE_TABLE_2M_ENTRY *PTE2M;
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PAGE_TABLE_1G_ENTRY *PTE1G;
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UINTN Index;
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VA.Uint64 = (UINT64)VirtualAddr;
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//VA_FIX_SIGN_EXTEND(VA);
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DBG("VmMapVirtualPage VA %lx => PA %lx\nPageTable: %p\n", VirtualAddr, PhysicalAddr, PageTable);
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DBG("VA: %lx => Indexes PML4=%x, PDP=%x, PD=%x, PT=%x\n",
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VA.Uint64, VA.Pg4K.PML4Offset, VA.Pg4K.PDPOffset, VA.Pg4K.PDOffset, VA.Pg4K.PTOffset);
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// PML4
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PML4 = PageTable;
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PML4 += VA.Pg4K.PML4Offset;
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// there is a problem if our PML4 points to the same table as first PML4 entry
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// since we may mess the mapping of first virtual region (happens in VBox and probably DUET).
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// check for this on first call and if true, just clear our PML4 - we'll rebuild it in later step
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if (PML4 != PageTable && PML4->Bits.Present && PageTable->Bits.PageTableBaseAddress == PML4->Bits.PageTableBaseAddress) {
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DBG("PML4 points to the same table as first PML4 - releasing it and rebuiding in a separate table\n");
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PML4->Uint64 = 0;
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}
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// prepare region start and end
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VAStart.Uint64 = 0;
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VAStart.Pg4K.PML4Offset = VA.Pg4K.PML4Offset;
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VA_FIX_SIGN_EXTEND(VAStart);
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VAEnd.Uint64 = ~(UINT64)0;
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VAEnd.Pg4K.PML4Offset = VA.Pg4K.PML4Offset;
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VA_FIX_SIGN_EXTEND(VAEnd);
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// print it
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DBG("PML4[%03x] at %p = %lx Region: %lx - %lx\n", VA.Pg4K.PML4Offset, PML4, PML4->Uint64, VAStart.Uint64, VAEnd.Uint64);
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if (!PML4->Bits.Present) {
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DBG("-> Mapping not present, creating new PML4 entry and page with PDPE entries!\n");
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PDPE = (PAGE_MAP_AND_DIRECTORY_POINTER *)VmAllocatePages(1);
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if (PDPE == NULL) {
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DBG("No memory - exiting.\n");
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return EFI_NO_MAPPING;
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}
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ZeroMem(PDPE, EFI_PAGE_SIZE);
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// init this whole 512GB region with 512 1GB entry pages to map first 512GB phys space
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PTE1G = (PAGE_TABLE_1G_ENTRY *)PDPE;
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Start = 0;
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for (Index = 0; Index < 512; Index++) {
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PTE1G->Uint64 = Start & PT_ADDR_MASK_1G;
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PTE1G->Bits.ReadWrite = 1;
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PTE1G->Bits.Present = 1;
|
|
PTE1G->Bits.MustBe1 = 1;
|
|
PTE1G++;
|
|
Start += 0x40000000;
|
|
}
|
|
|
|
// put it to PML4
|
|
PML4->Uint64 = ((UINT64)PDPE) & PT_ADDR_MASK_4K;
|
|
PML4->Bits.ReadWrite = 1;
|
|
PML4->Bits.Present = 1;
|
|
DBG("added to PLM4 as %lx\n", PML4->Uint64);
|
|
// and continue with mapping ...
|
|
}
|
|
DBG("-> Nx:%x|A:%x|PCD:%x|PWT:%x|US:%x|RW:%x|P:%x -> %lx\n",
|
|
PML4->Bits.Nx, PML4->Bits.Accessed,
|
|
PML4->Bits.CacheDisabled, PML4->Bits.WriteThrough,
|
|
PML4->Bits.UserSupervisor, PML4->Bits.ReadWrite, PML4->Bits.Present,
|
|
(PML4->Uint64 & PT_ADDR_MASK_4K)
|
|
);
|
|
|
|
// PDPE
|
|
PDPE = (PAGE_MAP_AND_DIRECTORY_POINTER *)(PML4->Uint64 & PT_ADDR_MASK_4K);
|
|
PDPE += VA.Pg4K.PDPOffset;
|
|
VAStart.Pg4K.PDPOffset = VA.Pg4K.PDPOffset;
|
|
VAEnd.Pg4K.PDPOffset = VA.Pg4K.PDPOffset;
|
|
DBG("PDPE[%03x] at %p = %lx Region: %lx - %lx\n", VA.Pg4K.PDPOffset, PDPE, PDPE->Uint64, VAStart.Uint64, VAEnd.Uint64);
|
|
if (!PDPE->Bits.Present || (PDPE->Bits.MustBeZero & 0x1)) {
|
|
DBG("-> Mapping not present or mapped as 1GB page, creating new PDPE entry and page with PDE entries!\n");
|
|
PDE = (PAGE_MAP_AND_DIRECTORY_POINTER *)VmAllocatePages(1);
|
|
if (PDE == NULL) {
|
|
DBG("No memory - exiting.\n");
|
|
return EFI_NO_MAPPING;
|
|
}
|
|
ZeroMem(PDE, EFI_PAGE_SIZE);
|
|
|
|
if (PDPE->Bits.MustBeZero & 0x1) {
|
|
// was 1GB page - init new PDE array to get the same mapping but with 2MB pages
|
|
DBG("-> was 1GB page, initing new PDE array to get the same mapping but with 2MB pages!\n");
|
|
PTE2M = (PAGE_TABLE_2M_ENTRY *)PDE;
|
|
Start = (PDPE->Uint64 & PT_ADDR_MASK_1G);
|
|
for (Index = 0; Index < 512; Index++) {
|
|
PTE2M->Uint64 = Start & PT_ADDR_MASK_2M;
|
|
PTE2M->Bits.ReadWrite = 1;
|
|
PTE2M->Bits.Present = 1;
|
|
PTE2M->Bits.MustBe1 = 1;
|
|
PTE2M++;
|
|
Start += 0x200000;
|
|
}
|
|
}
|
|
|
|
// put it to PDPE
|
|
PDPE->Uint64 = ((UINT64)PDE) & PT_ADDR_MASK_4K;
|
|
PDPE->Bits.ReadWrite = 1;
|
|
PDPE->Bits.Present = 1;
|
|
DBG("added to PDPE as %lx\n", PDPE->Uint64);
|
|
// and continue with mapping ...
|
|
}
|
|
DBG("-> Nx:%x|A:%x|PCD:%x|PWT:%x|US:%x|RW:%x|P:%x -> %lx\n",
|
|
PDPE->Bits.Nx, PDPE->Bits.Accessed,
|
|
PDPE->Bits.CacheDisabled, PDPE->Bits.WriteThrough,
|
|
PDPE->Bits.UserSupervisor, PDPE->Bits.ReadWrite, PDPE->Bits.Present,
|
|
(PDPE->Uint64 & PT_ADDR_MASK_4K)
|
|
);
|
|
|
|
// PDE
|
|
PDE = (PAGE_MAP_AND_DIRECTORY_POINTER *)(PDPE->Uint64 & PT_ADDR_MASK_4K);
|
|
PDE += VA.Pg4K.PDOffset;
|
|
VAStart.Pg4K.PDOffset = VA.Pg4K.PDOffset;
|
|
VAEnd.Pg4K.PDOffset = VA.Pg4K.PDOffset;
|
|
DBG("PDE[%03x] at %p = %lx Region: %lx - %lx\n", VA.Pg4K.PDOffset, PDE, PDE->Uint64, VAStart.Uint64, VAEnd.Uint64);
|
|
if (!PDE->Bits.Present || (PDE->Bits.MustBeZero & 0x1)) {
|
|
DBG("-> Mapping not present or mapped as 2MB page, creating new PDE entry and page with PTE4K entries!\n");
|
|
PTE4K = (PAGE_TABLE_4K_ENTRY *)VmAllocatePages(1);
|
|
if (PTE4K == NULL) {
|
|
DBG("No memory - exiting.\n");
|
|
return EFI_NO_MAPPING;
|
|
}
|
|
ZeroMem(PTE4K, EFI_PAGE_SIZE);
|
|
|
|
if (PDE->Bits.MustBeZero & 0x1) {
|
|
// was 2MB page - init new PTE array to get the same mapping but with 4KB pages
|
|
DBG("-> was 2MB page - initing new PTE array to get the same mapping but with 4KB pages!\n");
|
|
PTE4KTmp = (PAGE_TABLE_4K_ENTRY *)PTE4K;
|
|
Start = (PDE->Uint64 & PT_ADDR_MASK_2M);
|
|
for (Index = 0; Index < 512; Index++) {
|
|
PTE4KTmp->Uint64 = Start & PT_ADDR_MASK_4K;
|
|
PTE4KTmp->Bits.ReadWrite = 1;
|
|
PTE4KTmp->Bits.Present = 1;
|
|
PTE4KTmp++;
|
|
Start += 0x1000;
|
|
}
|
|
}
|
|
|
|
// put it to PDE
|
|
PDE->Uint64 = ((UINT64)PTE4K) & PT_ADDR_MASK_4K;
|
|
PDE->Bits.ReadWrite = 1;
|
|
PDE->Bits.Present = 1;
|
|
DBG("added to PDE as %lx\n", PDE->Uint64);
|
|
// and continue with mapping ...
|
|
}
|
|
DBG("-> Nx:%x|A:%x|PCD:%x|PWT:%x|US:%x|RW:%x|P:%x -> %lx\n",
|
|
PDE->Bits.Nx, PDE->Bits.Accessed,
|
|
PDE->Bits.CacheDisabled, PDE->Bits.WriteThrough,
|
|
PDE->Bits.UserSupervisor, PDE->Bits.ReadWrite, PDE->Bits.Present,
|
|
(PDE->Uint64 & PT_ADDR_MASK_4K)
|
|
);
|
|
|
|
// PTE
|
|
PTE4K = (PAGE_TABLE_4K_ENTRY *)(PDE->Uint64 & PT_ADDR_MASK_4K);
|
|
PTE4K += VA.Pg4K.PTOffset;
|
|
VAStart.Pg4K.PTOffset = VA.Pg4K.PTOffset;
|
|
VAEnd.Pg4K.PTOffset = VA.Pg4K.PTOffset;
|
|
DBG("PTE[%03x] at %p = %lx Region: %lx - %lx\n", VA.Pg4K.PTOffset, PTE4K, PTE4K->Uint64, VAStart.Uint64, VAEnd.Uint64);
|
|
if (PTE4K->Bits.Present) {
|
|
DBG("mapping already present - remapping!\n");
|
|
}
|
|
DBG("-> Nx:%x|G:%x|PAT:%x|D:%x|A:%x|PCD:%x|PWT:%x|US:%x|RW:%x|P:%x -> %lx\n",
|
|
PTE4K->Bits.Nx, PTE4K->Bits.Global, PTE4K->Bits.PAT,
|
|
PTE4K->Bits.Dirty, PTE4K->Bits.Accessed,
|
|
PTE4K->Bits.CacheDisabled, PTE4K->Bits.WriteThrough,
|
|
PTE4K->Bits.UserSupervisor, PTE4K->Bits.ReadWrite, PTE4K->Bits.Present,
|
|
(PTE4K->Uint64 & PT_ADDR_MASK_4K)
|
|
);
|
|
// put it to PTE
|
|
PTE4K->Uint64 = ((UINT64)PhysicalAddr) & PT_ADDR_MASK_4K;
|
|
PTE4K->Bits.ReadWrite = 1;
|
|
PTE4K->Bits.Present = 1;
|
|
DBG("added to PTE4K as %lx\n", PTE4K->Uint64);
|
|
|
|
return EFI_SUCCESS;
|
|
|
|
}
|
|
|
|
/** Maps (remaps) NumPages 4K pages given by VirtualAddr to PhysicalAddr pages in PageTable. */
|
|
EFI_STATUS
|
|
VmMapVirtualPages(PAGE_MAP_AND_DIRECTORY_POINTER *PageTable, EFI_VIRTUAL_ADDRESS VirtualAddr, UINTN NumPages, EFI_PHYSICAL_ADDRESS PhysicalAddr)
|
|
{
|
|
EFI_STATUS Status;
|
|
|
|
Status = EFI_SUCCESS;
|
|
while (NumPages > 0 && (Status == EFI_SUCCESS)) {
|
|
Status = VmMapVirtualPage(PageTable, VirtualAddr, PhysicalAddr);
|
|
VirtualAddr += 0x1000;
|
|
PhysicalAddr += 0x1000;
|
|
NumPages--;
|
|
DBG("NumPages: %d, %lx => %lx\n", NumPages, VirtualAddr, PhysicalAddr);
|
|
//WaitForKeyPress(L"press a key to continue\n");
|
|
}
|
|
return Status;
|
|
}
|
|
|
|
/** Flashes TLB caches. */
|
|
VOID
|
|
VmFlashCaches(VOID)
|
|
{
|
|
|
|
// just reload CR3
|
|
AsmWriteCr3(AsmReadCr3());
|
|
}
|